A Novel PSR Enhancement Technique for Full on-chip Low-Dropout Regulator

Transcription

1 3r International onference on oputer an Electrical Enineerin (IEE ) IPSIT ol. 53 () () IASIT Press, Sinapore DOI:.7763/IPSIT..V53.No..77 A Noel PS Enhanceent Technique for Full on-hip Low-Dp eulator Lin Din, Shuyin Zhan, Yan Liu, Yinyin Yuan an Yuchun han + State Key Laboratory on Interate Optoelectnics, ollee of Electnic Science an Enineerin, Jilin Uniersity, hanchun, hina Abstract. A noel feeback-factor-contl (FF) technique is presente to ipe i-frequency power supply rejection (PS) of full on-chip low p reulator (LDO). With this etho, the zes of PS are rearrane in a neste Miller copensation (NM) base full on-chip LDO. The i-frequency PS is enhance when the oinant ze of PS is oe to hiher frequency by FF circuit. The full on-chip LDO ipleente with hartere.35μ MOS pcess, features alost -9B PS at khz an ab - 45B at MHz. When the loa current chane f.5a to 5A, the axiu put-oltae ariation is less than 7V. Keywors: low p reulator; full on-chip; power-supply rejection.. Intuction With the rapi eelopent of F syste-on-chip (So), power supply noise attracts ore an ore concentration. A typical LDO usually nees a lare off-chip put capacitor, which akes it not suitable for So esins []. ecently, full on-chip LDO has been wiely eelope; howeer, it suffers f poor ifrequency PS. Nueus techniques hae been use to oercoe this issue []-[6]. One is usin cascain two reulators [4], but this leas to a hih p- oltae. Another etho is usin a feeforwar ripple cancellation (FF) technique [5]. The rawback is that a 4μF off-chip capacitor is still require, too lare to apply in So applications. ascain an NMOS to the PMOS pass eice of LDO is another solution [6], in which the NMOS is booste usin a chare pup. Howeer, the usin of the chare pup increases quiescent current, an reuces the efficiency. Fiure. The PS characteristics iara with FF an with FF To ipe i-frequency PS of full on-chip LDOs, a noel feeback-factor-contl (FF) technique is presente in this paper. The PS characteristics iara with FF an with FF is shown in Fi.. By contllin the feeback factor, the two zes z an z are force to cobine a ze-oublet z, which can be oe to hiher frequency, resultin in ipin the i-frequency PS. + orresponin author. E-ail aress: chanyc@jlu.eu.cn.

2 . Syste Desin an Analysis. PS of full on-chip LDO with traitional NM Fi. shows the basic structure of LDO with the traitional NM [7][8]. The PS transfer function is PS p s p + s + rs () s p + s p + p β where β fb /, is the feeback factor of PS path. p, r s an are the transconuctance, channel resistance an ate-rain capacitor of the power transistor. is a Miller copensation capacitor fe back to the put of the first stae.,, r an r are the transconuctance of the first stae aplifier, the transconuctance of the secon stae aplifier, the put resistance of the first stae, an the put resistance of the secon stae, respectiely. Here, β is enote by β f β () f + f We hae PS c r r r β A p o o s z, r r p o s z lp _ c r o (3) p β, (4) p where A lp-c is the D loop ain. Obiously, at low frequencies, PS is eterine by the D loop ain. Fiure. Basic LDO reulator with traitional NM structure circuit Since poles are uch reater than zes, only zes are consiere in followin iscussions. learly, z << z, leas to low i-frequency PS, shown in Fi. with ash line. Howeer, if we push the oinant ze z to hiher frequency, the i-frequency PS can be ipe.. The Ppose LDO With FF To boost the i-frequency PS of the circuit, the ppose FF circuit is intuce, shown in Fi. 3. The sall sinal for PS equialent circuit is inicate in Fi. 4. With FF circuit,

3 β fb ( f // f )[ f 3( ) + sf ] β + (5) r r ( + s ) of of where f3 is the transconuctance of M f3. For siplicity, equation () an (5) are written as as + as + a b s + b s + b β where, f 3 f (6) c s + c β β + (7) s + a p, a p, a, rs b p, b p, b, p ( f // f ) f f 3( f // f )( ) c c,, f f 3, Fiure 3. FF circuit structure Fiure 4. Sall sinal oe for PS of FF circuit Therefore, the final syste PS is PS s ( a + a ) + s ( a + a bc ) + ( a ( s b + s b + b β )( s + ) α ) (8)

4 where α b c / > is intuce by FF. Therefore, the feeback factor β can be contlle by aryin α to obtain a hiher i-frequency PS. ) PS at low frequencies F equation (8), syste PS at low frequencies is expresse by PS c a α (9) b β a) Heay loa When the loa current is lare, a - α is positie; therefore, PS c (a - α)/(b β ). Larer α will lea to hiher PS at low frequencies. b) Liht loa This situation is exactly opposite with heay loa. In orer to obtain hiher low frequency PS at liht loa, α shoul be sall. ) Zes of PS In orer to analyze the zes of PS, we hae to siplify the expression. The iscriinant of the nuerator in equation (8) is Δ ( α a + a b c ) 4 ( a + a )( a ) () a) Heay loa Lare loa current results in positie a -α. Thus, Δ is neatie, intucin a pair of coplex conjuate zes in PS It can be obsere that coplex ze can be increase by ecreasin α. a α () z coplex ( a + a ) b) Liht loa With this conition, a -α is neatie an the Δ is positie, leain to two real zes z, ( a + a ( a bc ) Δ () + a ) z can be increase by reucin α, z can be increase by increasin α. F the analysis aboe, it s iportant to note that both the alue of low frequency PS an the frequency of zes in PS cure all are epenent on α. There is a trae-off between the. In orer to obtain a better PS characteristic in full loa rane, we hae to sacrifice the low-frequency PS. In aition, the syste frequency response feeback factor is f f fb f of of 4 f (3) + of of 4 f + f This is to say, if r of, r of4 >> f, f is satisfie, the influence of FF circuit on the syste stability can be inore. 3. ircuit Ipleentation an Siulation esults The ppose LDO is copose of a two-stae aplifier, a power transistor, feeback resistors an FF circuit, as shown in Fi.5. In orer to achiee a oo transient response of LDO, the secon stae aplifier

5 utilizes -boostin circuit [9]. To eet the conition r of, r of4 >> f, f, a cascae structure is use. Meanwhile, a source follower stae is use to uarantee noral operation of M f. Fi.6 shows that the PS perforance of the LDO with (soli line) an with FF (ashe line) with 5A loa current. The low frequency PS increases 6B. It is clear to see that there is a pair of the coplex ze, locate between the low frequency ze an the hih frequency ze of the LDO with FF, which intuces a 36B increasin of PS at the ile frequency. Just like preicte in equation (), at the liht loa, for exaple,.5a, there are two real zes on the PS cure. opare with the zes with FF, the two zes are tenin to cobine toether at the liht loa conition, as seen f the Fi.7, resultin in the i-frequency PS boostin ab 8B. Howeer, the penalty is that the low-frequency PS with FF (soli line) is 6B lower than that of with FF (ashe line). Fiure 5. Ppose LDO reulator Een so, since the D loop ain of the syste is hih enouh when the loa current is low, the lowfrequency PS can be aintaine a hih alue. It can be seen f the Fi.7 that the low frequency PS is still hiher than 95B. PS (B) -4-8 Fiure Freq (Hz) oparison of PS between LDOs with an with FF with 5A loa current. PS (B) -4-8 Fiure Freq (Hz) oparison of PS between LDOs with an with FF with.5a loa current. Loa urrent (A) Output Voltae (V) Tie (us) Fiure 8. Loa transient response of the ppose LDO.

6 Fi.8 illustrates the transient response. When the loa current is chane f.5a to 5A an back to.5a in μs, the oershoot an unershoot of this LDO is 35V an 7V, respectiely. 4. onclusions A full on-chip MOS LDO with hih i-frequency PS is presente in this paper, base on the FF circuit. The ppose LDO not only ipes the i-frequency PS, but also occupies saller chip area. With total internal copensation capacitors as sall as.5pf, -9B PS at khz an ab -45B at MHz are achiee for this full on-chip LDO. Therefore, the ppose structure offers a oo choice for the esin of full on-chip power anaeent. 5. Acknowleent This work is financially supporte by Science Fntier an Interisciplinary Innoation pject of Jilin Uniersity with No.9388, National Natural Science Founation of hina with No an Jilin Pincial Science & Technoloy Departent Pject with No eferences [] G. A. incon-mora,an P. E. Allen, Optiize frequency shapin circuit topoloies for LDOs, IEEE Trans. ircuits Syst. Ⅱ, ol. 45, no. 6, pp ,Jun. 998.oi:.9/ [] P. Hazucha, T. Karnik, B.A. Bloechel, an. Parsons, Area-Efficient Linear eulator With Ultra-Fast Loa eulation, IEEE J. Soli-State ircuits, ol.4, no.4, April 5, pp [3] G.A. incon-mora, an P. E. Allen, A Low-Voltae,low Quiesent urrent, Low Dp-Out eulator, IEEE J. Soli State ircuits, ol. 33, no., Jan. 988, pp [4] Dallas Seiconuctor/Maxi, Application. Note 883. Ipe Power Supply ejection for I Linear eulators.[db/ol].[--] [5] M. El-Nozai, A. Aer an J. Torres, A 5A.3μ MOS LDO reulator with power-supply rejection better than -56B up to MHz usin a feeforwar ripple-cancellation technique, IEEE International Soli-State ircuits onference, ISS, 9,pp.33-33,33a, oi:.9/iss [6] V. Gupta an G. A. incon-mora, A 5A.6μ MOS Miller-opensate LDO eulator with -7B Worst-ase Power-Supply ejection Usin 6pF of On-hip apacitance, IEEE International Soli-State ircuits onference, ISS, 7,pp.5-5, oi:.9/iss [7]. G. H. Eschauzier, L. P. T. Kerklaan, an J. H. Huijsin, A MHz B Operational A plifier with Muktipath Neste Miller opensation Structure, IEEE Journal of Soli-State ircuits, 99,7(): [8].K. haa an J. Sila-Martinez, A Frequency opensation Schee for LDO Voltae eulators, IEEE Trans. ircuits Syst. I:reular paper, ol.5, no. 6, June. 4. [9] K. N. Leun an P. K. T. Mok, A capacitor-free MOS low-p reulator with apin-factor-contl frequency copensation, IEEE J. Soli State ircuits, ol. 38, no., pp.69-7,oct. 3.