V. Transistors. 3.1 III. Bipolar-Junction (BJT) Transistors

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1 V. Transistors 3.1 III. Bipolar-Junction (BJT) Transistors A bipolar junction transistor is formed by joining three sections of semiconductors with alternatiely different dopings. The middle section (base) is narrow and one of the other two regions (emitter) is heaily doped. Two ariants of BJT are possible: NPN and PNP. C NPN Transistor C PNP Transistor B n p C B B C B p n C B B C n p Circuit Symbols Circuit Symbols We will focus on NPN BJTs. Operation of a PNP transistor is analogous to that of a NPN transistor except that the role of majority charge carries reersed. In NPN transistors, electron flow is dominant while PNP transistors rely mostly on the flow of holes. Therefore, to zeroth order, NPN and PNP transistors behae similarly except the sign of current and oltages are reersed. i.e., PNP = NPN! In practice, NPN transistors are much more popular than PNP transistors because electrons moe faster in a semiconductor. As a results, a NPN transistor has a faster response time compared to a PNP transistor. At the first glance, a BJT looks like 2 diodes placed back to back. Indeed this is the case if we apply oltage to only two of the three terminals, letting the third terminal float. This is also the way that we check if a transistor is working: use an ohm-meter to ensure both diodes are in working conditions. (One should also check the resistance between C terminals and read a ary high resistance as one may hae a burn through the base connecting collector and emitter.) The behaior of the BJT is different, howeer, when oltage sources are attached to both B and C terminals. The B junction acts like a diode. When this junction is forward biased, electrons flow from emitter to the base (and a small current of holes from base to emitter). The base region is narrow and when a oltage is applied between collector and emitter, most of the electrons that were flowing from emitter to base, cross the narrow base region and are collected at the collector region. So while the BC junction is reersed biased, a large current can flow through that region and BC junction does not act as a diode. The amount of the current that crosses from emitter to collector region depends strongly on the oltage applied to the B junction, B. (It also depends weakly on oltage applied C65 Lecture Notes (F. Najmabadi), Fall

2 between collector and emitter, C.) As such, small changes in B or i B controls a much larger collector current. Note that the transistor does not generate. It acts as a ale controlling the current that can flow through it. The source of current (and power) is the power supply that feeds the C terminals. A BJT has three terminals. Six parameters;, i B, i, C, B, and CB ; define the state of the transistor. Howeer, because BJT has three terminals, KVL and KCL should hold for these terminals, i.e., i = i B BC = B C i B CB B C i Thus, only four of these 6 parameters are independent parameters. The relationship among these four parameters represents the i characteristics of the BJT, usually shown as i B s B and s C graphs. The aboe graphs show seeral characteristics of BJT. First, the B junction acts likes a diode. Secondly, BJT has three main states: cut-off, actie-linear, and saturation. A description of these regions are gien below. Lastly, The transistor can be damaged if (1) a large positie oltage is applied across the C junction (breakdown region), or (2) product of C exceed power handling of the transistor, or (3) a large reerse oltage is applied between any two terminals. Similar to diodes, seeral models aailable for a BJT. These are typically diided into two general categories: large-signal models that apply to the entire range of alues of current and oltages, and small-signal models that apply to AC signals with small amplitudes (we will discuss these in the context of amplifiers later). Low-frequency and high-frequency models also exist (high-frequency models account for capacitance of each junction). Obiously, the simpler the model, the easier the circuit calculations are. More complex models describe the behaior of a BJT more accurately but analytical calculations become difficult. For analytical calculations here, we will start with a simple low-frequency, large-signal model (below). C65 Lecture Notes (F. Najmabadi), Fall

3 3.2 Large Signal Model for BJT First let s consider a NPN transistor. As the B junction acts like a diode, a simple piece-wise linear model can be used : B Junction ON: B = γ, and i B > 0 B Junction OFF: B < γ, and i B = 0 where γ is the forward bias oltage ( γ 0.7 V for Si semiconductors). When the B junction is reersed-biased, transistor is OFF as no charge carriers enter the base and moe to the collector. The oltage applied between collector and emitter has no effect. This region is called the cut-off region: Cut-Off: B < γ, i B = 0, i 0 Since the collector and emitter currents are ery small for any C, the effectie resistance between collector and emitter is ery large (100 s of MΩ) making the transistor behae as an open circuit in the cut-off region. When the B junction is forward-biased, transistor is ON. The behaior of the transistor, howeer, depends on how much oltage is applied between collector and emitter. If C > γ, the B junction is forward biased while BC junction is reersed-biased and transistor is in actie-linear region. In this region, scales linearly with i B and transistor acts as an amplifier. Actie-Linear: B = γ, i B > 0, i B = β constant, C γ If C < γ, both B and BC junctions are forward biased. This region is called the saturation region. As C is small while can be substantial, the effectie resistance between collector and emitter in saturation region is small and the BJT acts as a closedcircuit. Saturation: B = γ, i B > 0, i B < β, C sat Our model specifies C sat, the saturation oltage. In reality in the saturation region 0 < C < γ. As we are mainly interested in the alue of the collector current in this region, C is set to a alue in the middle of its range in our simple model (Typically a alue of sat V for Si BJTs). This alue is justified later in the context of bers-moll model (Sec ) C65 Lecture Notes (F. Najmabadi), Fall

4 The aboe simple, large-signal model is shown below. A comparison of this simple model with the real BJT characteristics demonstrates the degree of approximation used. i B i C Saturation BJT ON Actie Linear BJT OFF γ B sat C Cut Off A similar large signal model for PNP transistor can also constructed noting all oltages in a NPN transistor are negatie: Summary of BJT large-signal Models: NPN PNP Cut-off: i B = 0, B < γ i B = 0, B < γ = 0 = 0 Actie Linear: B = γ, i B > 0 B = γ, i B > 0 = βi B > 0, C > γ = βi B > 0, C > γ Saturation: B = γ, i B > 0 B = γ, i B > 0 C = sat, < βi B C = sat, < βi B i B CB B C i B CB B C i i C65 Lecture Notes (F. Najmabadi), Fall

5 How to sole BJT circuits: Similar to diode circuits, we need assume that BJT is in a particular state, use BJT model for that state to sole the circuit and check the alidity of our assumption. Recipe for soling NPN BJT circuits (PNP in parenthesis): 1) Write down a KVL including the B junction (call it B-KVL). 2) Write down a KVL including C terminals (call it C-KVL). 3) Assume BJT is in cut-off (this is the simplest). Set i B = 0. Calculate B from B-KVL. 3a) If B < γ (PNP: B < γ ), then BJT is in cut-off, i B = 0 and B is what you just calculated. Set = i = 0, and calculate C from C-KVL. You are done. 3b) If B > γ (PNP: B > γ ), then BJT is not in cut-off. Set B = γ (PNP: B = γ ). Sole aboe KVL to find i B. You should get i B > 0. 4) Assume that BJT is in actie linear region. Let i = βi B. Calculate C from C-KVL. 4a) If C > γ (PNP: C > γ ), then BJT is in actie-linear region. You are done. 4b) If C < γ (PNP: C < γ ), then BJT is not in actie-linear region. It is in saturation. Let C = sat (PNP: C = sat ) and compute from C-KVL. You should find that < βi B. You are done. Note that the difference in the recipes for NPN and PNP transistor is just replacing B with B and replacing C with C. xample 1: Compute the parameters of this circuit (β = 100). 12 V Following the procedure aboe (for NPN transistor): 1k B-KVL: 4 = i B B C-KVL: 12 = 10 3 C, 40k 4 V i B CB B C i Assume BJT is in cut-off. Set i B = 0 in B-KVL: B-KVL: 4 = i B B B = 4 > γ = 0.7 V So BJT is not in cut off and BJT is ON. Set B = 0.7 V and use B-KVL to find i B. B-KVL: 4 = i B B i B = , 000 = 82.5 µa Assume BJT is in actie linear, Find = βi B and use C-KVL to find C : C65 Lecture Notes (F. Najmabadi), Fall

6 = βi B = 100i B = 8.25 ma C-KVL: 12 = 1, 000 C, C = = 3.75 V As C = 3.75 > γ, the BJT is indeed in actie-linear and we hae: B = 0.7 V, i B = 82.5 µa, i = 8.25 ma, and C = 3.75 V. xample 2: Compute the parameters of this circuit (β = 100). 12 V Following the procedure aboe (for PNP transistor): 1k B-KVL: 4 = i B B C-KVL: 12 = 10 3 C, 40k 4 V i B CB B C i Assume BJT is in cut-off. Set i B = 0 in B-KVL: B-KVL: 4 = i B B B = 4 V B = 4 > γ = 0.7 V So BJT is not in cut off and BJT is ON. Set B = 0.7 V and use B-KVL to find i B. B-KVL: 4 = i B B i B = , 000 = 82.5 µa Assume BJT is in actie linear, Find = βi B and use C-KVL to find C : = βi B = 100i B = 8.25 ma C-KVL: 12 = 10 3 C, C = = 3.75 V As C = 3.75 > γ, the BJT is indeed in actie-linear and we hae: B = 0.7 V, i B = 82.5 µa, i = 8.25 ma, and C = 3.75 V. xample 3: Compute the parameters of this circuit (β = 100). Following the procedure aboe: 1k 12 V B-KVL: C-KVL: 4 = i B B 10 3 i 12 = 1, 000 C 1, 000i 40k 4 V i B CB B 1k C i Assume BJT is in cut-off. Set i B = 0 and i = = 0 in B-KVL: C65 Lecture Notes (F. Najmabadi), Fall

7 B-KVL: 4 = i B B 10 3 i B = 4 > 0.7 V So BJT is not in cut off and B = 0.7 V and i B > 0. Here, we cannot find i B right away from B-KVL as it also contains i. Assume BJT is in actie linear, i = βi B : B-KVL: 4 = i B B 10 3 βi B = 0.7 ( )i B i B = 24 µa i = βi B = 2.4 ma C-KVL: 12 = 1, 000 C 1, 000i, C = = 7.2 V As C = 7.2 > γ, the BJT is indeed in actie-linear and we hae: B = 0.7 V, i B = 24 µa, i = 2.4 ma, and C = 7.2 V. xample 4: Compute the parameters of the Si transistor (β = 100) in the circuit below. Since there is a 10 V supply in the B-loop, it is a good starting assumption that BJT is ON (PNP: B = γ = 0.7 V and i B > 0) B-KVL: 10 = i B i = = 4.65 ma Since i > 0, the assumption of B ON is justified (since i > 0 requires both i B and > 0). Assuming BJT in actie: i B 10 V 2k B 1k 10 V i C i = i B = (β 1)i B i B = 4.65/ µa = i i B 4.6 ma C-KVL: 10 = i C = 9.3 C = C 3.9 C = 6.1 V Since C = 6.1 > 0.7 = γ (PNP BJT), the assumption of BJT in actie is justified and B = 0.7 V, i B = 50 µa, C = 6.1 V, and = 4.6 ma, C65 Lecture Notes (F. Najmabadi), Fall

8 Load line The operating point of a BJT can be found graphically using the concept of a load line. For BJTs, the load line is the relationship between and C that is imposed on BJT by the external circuit. For a gien alue of i B, the C characteristics cure of a BJT is the relationship between and C as is set by BJT internals. The intersection of the load line with the BJT characteristics represent a pair of and C alues which satisfy both conditions and, therefore, is the operating point of the BJT (often called the Q point for Quiescent point) The equation of a load line for a BJT should include only and C (no other unknowns). This equation is usually found by writing a KVL around a loop containing C. For the circuit shown, we hae: i 40k V KVL: 15 = 375 C which is the equation of a line in the C space. This load line and the C characteristics lines of the BJT are shown below. The operating point of the BJT (Q-point) is also shown for i B = 150 µa (or i = 6.7 V in the example aboe). Note that if an emitter resistor is present (e.g., xample 3 in page 68), the load line can still be constructed noting that i : KVL: 12 = 1, 000 C 1, 000i 2, 000 C = 12 C65 Lecture Notes (F. Najmabadi), Fall

9 3.3 BJT Switches and Logic Gates The basic element of logic circuits is the transistor switch. A schematic of such a switch is shown. When the switch is open, = 0 and o = V CC. When the switch is closed, o = 0 and = V CC /R C. i i B R C V CC o In an electronic circuit, mechanical switches are not used. The switching action is performed by a transistor with an input oltage switching the circuit, as is shown. When i = 0, BJT will be in cut-off, = 0, and o = V CC (open switch). When i is in high state, BJT can be in saturation with o = C = sat 0.2 V and = (V CC sat )/R C (closed switch). When R c is replaced with a load, this circuit can switch a load ON or OFF (see e.g., Problems 12 & 13). i R B i B R C V CC o Logic Gates You hae seen binary mathematics and logic gates in C25. We will explore some electronic logic gates in this course. Binary mathematics is built upon two states: 0, and 1. We need to relate the binary states to currents or oltages as these are the parameters that we can manipulate in electronic circuits. Similar to our discussion of analog circuits, it is adantageous (from power point of iew) to relate these the binary states to oltages. As such, we choose two oltages to represent the binary states: L for state 0 or Low state and H for state 1 or High state (for example, 0 V to represent state 0 and 5 V to represent state 1). These oltages are quite arbitrary and can be chosen to hae any alue. Similar to analog circuits, we can plot the oltage transfer characteristics of a gate. For example, the oltage transfer characteristics of an ideal inerter is shown in the figure: when the input is low, the output is high and the when the input is high, the output is low. We can see a difficulty right away. In a practical circuit, there would be an output oltage for any input oltage, so the output oltage makes a smooth transition for the high oltage to the low oltage as the input oltage is aried. We hae to be careful as it is extremely difficult, if not impossible, to design an electronic circuit to gie exactly a oltage like 5 V (what if the input oltage was 4.99 V?). So, we need to define a range of oltages (instead of one alue) to represent high and low states. We will try ery hard to make sure that the output of our gates to be as close as possible to V H and V L, But, we need to design our gates such that they respond to a range of oltages, i.e., the gate would think that the input is low if the input oltage is smaller than IL and would think that the input is high if the input oltage is larger than IH (see figure). C65 Lecture Notes (F. Najmabadi), Fall

10 With these definitions, the oltage transfer characteristics of a practical inerter (plot of o as a function of i ) is shown. The range of oltages, L to IL and IH to H are called the noise margins. The range of oltages between IL to IH is the forbidden region as in this range, the output of the gate does not correspond to any binary state. The maximum speed that a logic gate can operate is set by the time it takes to traerse this region as the input oltage is aried from one state to another state. V o Vo V H V H V L V i VL V i V L V H VL VIL V IH V H Resistor-Transistor Logic (RTL) The BJT switch circuit discussed aboe is also an inerter or a NOT logic gate. This circuit is a member of RTL family of logic gates. Let s assume that the low state is at L = 0.2 V ( sat ) and the high state is H = V CC. To find the transfer characteristics of this gate, we need to find o for a range of i alues. This plot will also help identify the alues of IL and IH. From B-KVL, i = R B i B B, we find that for i < γ, BJT will be in cut-off, = 0 and o = V CC (high state). Therefore, when i = L = sat, o = V CC = H. Moreoer, The output will be high as long as i < γ, or IL = γ. Note that IL corresponds to the case where B = γ and i B > 0 but small such that the term i B R B can be ignored compared to B. When i exceeds γ, B junction will be forward biased and a current i B flows into BJT: i B = i γ R B As B junction is forward biased, BJT can be either in saturation or actie-linear. Let s assume BJT is is in saturation. In that case, o = C = sat and /i B < β. Then: i R B i B R C V CC o = V CC sat R C i B > β = V CC sat βr C C65 Lecture Notes (F. Najmabadi), Fall

11 Therefore, BJT will be in saturation only if i B exceeds the alue gien by the formula aboe. This occurs when i become large enough: i = γ R B i B > γ R B V CC sat βr C = IH If we choose R B and R C such that IH < V CC, then for i = V CC, BJT will be in saturation, and C = sat. Oerall, for i = L = sat, o = V CC = H and for i = H = V CC, o = sat = L. Thus, this is a NOT gate. For i alues between IL and IH, the B junction is forward biased but the BJT is NOT in saturation, and thus, it is in actie linear. In this case, the output oltage smoothly changes for its high alue to its low alue as is shown in the plot of transfer characteristics. This range of i is the forbidden region and the gate would not work properly in this region. This behaior can also seen in the plot of the BJT load line. For small alues of i (i B = 0) BJT is in cut-off. As i is increased, i B is increased and the operating point moes to the left and up on the load line and enters the actie-linear region. When i B is raised aboe certain limit, the operating point enters the saturation region. A major drawback of the this RTL inerter gate is the limited input range for the low signal ( IL ). For high state, the noise margin for high state can be controlled by adjusting alues of R C and R B. Howeer, our analysis indicated that IL = γ, that is the gate input is low for oltages between 0.2 V and γ 0.7 V which is quite a small noise margin. For the aboe analysis, we hae been using a constant-oltage piecewise linear model for the B junction diode. In reality, the BJT will come out of cut-off (B junction will conduct) at smaller oltages ( 0.5 V), making the noise margin for low state een smaller. In order to build a gate with a larger noise margin for low oltage, we examine the B- KVL: i = R B i B B. Note that i = IL corresponds to B = γ and i B > 0 but small. Two approaches are possible: 1) Add an element in series with R B which would hae a large oltage drop for a small current, e.g., a diode, 2) Allow the current in R B to be larger than i B. We explore both options below: C65 Lecture Notes (F. Najmabadi), Fall

12 For this circuit, B-KVL gies: i = D R B i B B. Then to find IL, we substitute for B = γ and i B > 0 but small to get: IL D γ. Since i D = i B > 0 but small, the diode should also be forward biased and D = γ. Thus, IL 2 γ = 1.4 V. Note that IL can be increased further in increments of γ by adding more diodes in the input. i R B i B R C V CC o This approach works reasonably well in ICs as the diode and B junction can be constructed with similar reerse saturation currents. Howeer, for a circuit built with discrete components (e.g., a BJT switch) this approach may not work well as the reersed saturation current for discrete diodes, I sd, is typically 2 to 3 orders of magnitude larger than reersed saturation current for the B junction. As such, the small current needed to make B γ only leads to D = V. (see Lab 4 for a solution to this problem). The second method to increase the noise margin is to add a resistor between the base and ground as is shown. To see the impact of this resistor, note that V IL is the input oltage when BJT is just leaing the cut-off region. At this point, B = γ, and i B is positie but ery small (effectiely zero). Since a oltage B has appeared across R 1, we hae: i i 2 R B R 1 i B i 1 V CC R C o i 1 = B R 1 i 2 = i B i 1 i 1 = B R 1 IL = i = R B i 2 B = B R B R 1 B = γ ( 1 R B R 1 ) This alue should be compared with IL = γ in the absence of resistor R 1. It can be seen that for R B = R 1, IL can be raised from 0.7 to 1.4 V. Moreoer, arbitrary alues of IL can be achieed by proper choice of R B and R 1. Typically, R 1 does not affect IH as i B needed to put the BJT in saturation is typically seeral times larger than i 1. C65 Lecture Notes (F. Najmabadi), Fall

13 RTL NOR Gate Logic circuits are typically constructed from basic logic gates like NOR or NAND. You hae seen in C25 that all higher leel logic gates, e.g., flip-flops, can be made by a combination of NOR gates or NAND gates. So, for each logic gate that we will work on, we hae to remember that the output of the logic gate is attached to the input of another logic gate. V By combining two or more RTL inerters, one obtains the basic logic gate circuit of RTL family, a NOR gate, as is shown (see Problem 15). More BJTs can be added for additional input signals. R 1 2 B CC RB R C o RTLs were the first digital logic circuits using transistors. They require at least one resistor and one BJT per input. They were replaced with diode-transistor logic, DTL (reduced number of resistors and BJTs) and transistor-transistor logic, TTL (which packs all of the didoes in a special transistor). Most popular BJT gates today are TTL or emitter coupled logic, CL. With the adent of CMOS technology, BJT-based gates are now only used for special purpose circuits (for example, high speed gates utilizing CL) Diode-Transistor Logic (DTL) The basic gate of DTL logic circuits is a NAND gate which is constructed by a combination of a diode AND gate (analyzed in pages 35 and 36) and a BJT inerter gate as is shown below (left figure). Because R B is large, on ICs, this resistor is usually replaced with two diodes. The combination of the two diodes and the B junction diode leads to a oltage of 2.1 V for the inerter to switch and a IL = 1.4 V for the NAND gate (Why?). Resistor R 1 is necessary because without this resistor, current i B will be too small and the oltage across D 3 and D 4 will not reach 0.7 V although they are both forward biased. V CC V CC i A R A R C i A R A R C 1 D 1 i 1 3 i B o 1 D 1 i 1 3 D D 3 4 i B o 2 D 2 i 2 R B 2 D 2 i 2 i 4 i 5 R 1 C65 Lecture Notes (F. Najmabadi), Fall

14 xample: Verify that the DTL circuit aboe (with R A = 5 kω, R C = 1 kω, R 1 = 5 kω, and V CC = 5 V) is a NAND gate. Assume that low state is 0.2 V, high state is 5 V, and BJT β min = 40. Case 1: 1 = 2 = 0.2 V It appears that the 5-V supply will forward bias D 1 and D 2. Assume D 1 and D 2 are forward biased: D1 = D2 = γ = 0.7 V and i 1 > 0, i 2 > 0. In this case: 3 = 1 D1 = 2 D2 = = 0.9 V Voltage 3 = 0.9 V is not sufficient to froward bias D 3 and D 4 as 3 = D3 D4 B and we need at least 1.4 V to forward bias the two diodes. So both D 3 and D 4 are OFF and i 4 = 0. (Note that D 3 and D 4 can be forward biased without B junction being forward biased as long as the current i 4 is small enough such that oltage drop across the 5 kω resistor parallel to B junction is smaller than 0.7 V. In this case, i 5 = i 4 and i B = 0.) Then: i 1 i 2 = i A = 5 3 5, 000 = = 0.82 ma 5, 000 And by symmetry, i 1 = i 2 = 0.5i A = 0.41 ma. Since both i 1 and i 2 are positie, our assumption of D 1 and D 2 being ON are justified. Since i 4 = 0, i B = 0 and BJT will be in cut-off with = 0 and o = 5 V. So, in this case, D 1 and D 2 are ON, D 3 and D 4 are OFF, BJT is in cut-off, and o = 5 V. Case 2: 1 = 0.2 V, 2 = 5 V Following arguments of case 1, assume D 1 is ON. Again, 3 = = 0.9 V, and D 3 and D 4 will be OFF with i 4 = 0. We find that oltage across D 2 is D2 = 3 2 = = 4.1 V and, thus, D 2 will be OFF and i 2 = 0. Then: i 1 = i A = 5 3 5, 000 = = 0.82 ma 5, 000 and since i 1 > 0, our assumption of D 1 ON is justified. Since i 4 = 0, i B = 0 and BJT will be in cut-off with = 0 and o = 5 V. So, in this case, D 1 is ON, D 2 is OFF, D 3 and D 4 are OFF, BJT is in cut-off, and o = 5 V. Case 3: 1 = 5 V, 2 = 0.2 V Because of the symmetry in the circuit, this is exactly the same as case 2 with roles of D 1 and D 2 reersed. So, in this case, D 1 is OFF, D 2 is ON, D 3 and D 4 are OFF, BJT is in cut-off, and o = 5 V. Case 4: 1 = 2 = 5 V xamining the circuit, it appears that the 5-V supply will NOT be able to forward bias D 1 and D 2. Assume D 1 and D 2 are OFF: i 1 = i 2 = 0, D1 < γ and C65 Lecture Notes (F. Najmabadi), Fall

15 D2 < γ. On the other hand, it appears that D 3 and D 4 will be forward biased. Assume D 3 and D 4 are forward biased: D3 = D4 = γ = 0.7 V and i 4 > 0. Further, assume the BJT is not in cut-off B = γ = 0.7 V and i B > 0. In this case: 3 = D3 D4 B = = 2.1 V D1 = 3 1 = = 2.9 V < γ D2 = 3 2 = = 2.9 V < γ Thus, our assumption of D 1 and D 2 being OFF are justified. Furthermore: i 4 = i A = 5 3 5, 000 = = 0.58 ma 5, 000 i 5 = B 5, 000 = 0.7 = 0.14 ma 5, 000 i B = i 4 i 5 = = 0.44 ma and since i 4 > 0 our assumption of D 3 and D 4 being ON are justified and since i B > 0 our assumption of BJT not in cut-off is justified. We still do not know if BJT is in actie-linear or saturation. Assume BJT is in saturation: o = C = sat = 0.2 V and /i B < β. Then, assuming no gate is attached to the circuit, we hae = 5 sat 1, 000 = = 4.8 ma 1, 000 and since /i B = 4.8/0.44 = 11 < β = 40, our assumption of BJT in saturation is justified. So, in this case, D 1 and D 2 are OFF, D 3 and D 4 are ON, BJT is in saturation and o = 0.2 V. Oerall, the output in low only if both inputs are high, thus, this is a NAND gate. Note: It is interesting to note that at the input of this gate, the current actually flows out of the gate. In the example aboe, when both inputs were high i 1 = i 2 = 0, when both were low i 1 = i 2 = 0.4 ma, and when one input was low, e.g., 1 was low, i 1 = 0.8mA. The input current flowing in (or out of the gate in this case) has an important implication as this current should be supplied by the preious logic gate. As such, an important parameter for a logic gate is its fan-out (defined as the maximum number of similar gates that can be attached to it). C65 Lecture Notes (F. Najmabadi), Fall

16 3.3.4 Transistor-Transistor Logic (TTL) A simplified ersion of an IC-chip NPN transistor is shown. The deice is fabricated on a p-type substrate (or body) in a ertical manner by embedding alternating layers of N and P-type semiconductors. By embedding more than one N-type emitter region, one can obtain a multiple-emitter NPN transistor as shown. The multiple-emitter NPN transistors can be used to replace the input diodes of a DTL NAND gate and arrie at a NAND gate entirely made of transistors, hence Transistor-Transistor Logic (TTL) gates. Circuit Symbol A simple TTL gate is shown with the multiple-emitter BJT replacing the input diodes. This transistor operates in reerse-actie mode, i.e., like a NPN transistor in actie-linear mode but with collector and emitter switched. Operationally, this BJT acts as two diodes back to back as shown in the circle at the bottom of the figure. As such the operation of this gate is essentially similar to the DTL NAND gate described aboe (note position of drier transistor and D 4 diode is switched). Similar to DTL NAND gates, a typical TTL NAND gate has three stages: 1) Input stage (multi-emitter transistor), 2) drier stage, and 3) output stage. Modern TTL gates basically hae the same configuration as is shown with the exception that the output stage is replaced with the Totem- Pole output stage to increase switching speed and gate fanout. For a detailed description of TTL gate with Totem- Pole output stage, consult Sedra and Smith (pages 1175 to 1180). 1 2 V R 1 CC R A R 2 R C o C65 Lecture Notes (F. Najmabadi), Fall

17 3.4 Other BJT Models π and T Models In this section, we explore a few other large-signal BJT models. It should be noted that for analytical circuit calculations, the simple large-signal model deeloped preiously is adequate and more sophisticated models are rarely used. The models deeloped here are useful for special cases when a more detailed behaior of BJT is necessary (e.g., response of BJT to a change in ambient temperature). They are, howeer, the basis for the small signal model which we will deelop later. We focus on models for a NPN BJT here. Starting with the actie-linear region, we note that the B junction acts like a diode and the collector current is proportional to i B, i.e., i c = βi B. The corresponding circuit model is shown below (to the left). This model is correct also for cut-off region as in cut-off i B = 0 and the controlled current source βi B will become an open circuit and = 0. Note that if we substitute for the diode, its constant-oltage piece-wise linear model (i B = 0, B γ or i B 0, B = γ ) we arrie at our simple large-signal model for the BJT. We can improe the accuracy of the model below by using the full diode equation for the B junction: i B = I sb exp( B /V T ). In this case, the collector current will be = βi B = I s exp( B /V T ) where I s is called the BJT reerse saturation current and I sb = I s /β. This notation is shown in the model below (right). While the two model are mathematically identical, they represent different physicsal pictures of the BJT operation. The model to the left portrays BJT as a current-controlled deice (controlled by i B ) while the model to right portrays BJT as a oltage-controlled deice (controlled by B ). Note that our simple large signal model where diode was replaced by its constant oltage model ( B = γ ) portrays BJT only as a current-controlled deice. B ΒΕ i Β D β i Β C C B B i Β D I sb = I s / β C I exp( /V ) s B T The model aboe is referred to as the Common-mitter configuration or the π model (as it looks like an inerted π). The circuit elements can be configured differently to arrie at the T model for the BJT as is shown below (left). In this case, current i = i B flows through the diode. Therefore I s = I sb I s = ( ) 1 β 1 I s = I s α with α β β 1 C65 Lecture Notes (F. Najmabadi), Fall

18 Where I s is the D diode saturation current (this D diode, of course, is different than the D in the π model). It is straight-forward to show that = βi B : i B = i = I s e B/V T I s e B/V T = (I s I s )e B/V T = I s β e B/V T = β The model (below left) is a oltage-controlled model for BJT. Similar to the π model, an equialent current-controlled model can be constructed (below right) C C αi Ε B i Β B I exp( /V ) s B T D I s = I s / α B i Β D i Ε Similar models can also be constructed for a PNP transistor but with the direction of currents reersed ( and ib Flowing out of BJT while i flowing in) requiring that both the diode and the controlled current source to be flipped upside-down in the circuit model. B should also be replaced by B in the oltage-controlled model. B ΒΕ i Β D β i Β C C B i Β I = I / β sb s D B C I exp( /V ) s B T C C αi Ε B i Β B I exp( /V ) s B T D I s = I s / α B i Β D i Ε C65 Lecture Notes (F. Najmabadi), Fall

19 3.4.2 arly ffect Detailed examination of the i c C characteristic cures of a BJT show that in the actie region and for a gien i B (or B ) cure is a straight line but has a finite slope as opposed to our model of = βi B which is a straight line but with a zero slope. In fact, all characteristics lines, if extrapolated, meet at a negatie oltage C = V A as is shown below. The oltage V A (which is positie) is particular to each BJT (depends on its manufacturing) and has a typical alue of 50 to 100 V. It is called the arly oltage and the change in with C is called the arly effect. This linear relationship can be accounted for by the following equation: ( i c = I s e B/V T 1 ) C V A The arly effect can be modeled by adding a resistor r o between the collector and emitter as is shown. The alue of r o is inersely proportional to the slope of the line (for a gien i B or B ). Considering the figure aboe, it is obious that slope of the line (and thus, r o ) changes for different alues of i B or B. It is rarely necessary to include the arly ffect in the DC analysis of BJTs but it has an impact on the AC behaior of BJT as we will see in the amplifier section. B ΒΕ i Β D β i Β r ο C C C65 Lecture Notes (F. Najmabadi), Fall

20 3.4.3 Reerse-Actie Operation The cross section of an NPN BJT on an integrated circuit is shown. As discussed before, although an NPN BJT consists of a p-doped layer sandwiched between two n-doped layers, the deice construction (increased doping of mitter and/or larger area of CB junction compared to B junction) makes the deice asymmetrical and allows amplification of i B in the actie mode. A NPN transistor can be biased in the reersed mode, i.e., the BC junction can be forward-biased (instead of B junction forward biased) and a oltage can be applied between and C (here C < 0 for a NPN transistor). In such an arrangement, the deice acts as a poor BJT, i.e., it operates in an actie mode but with much reduced β alue. This mode of operation is called the reerse actie mode with = β R i B where β R typically ranges from 0.5 to 1 (compare to β ranging from 50 to 400 in the actie mode). The corresponding T model for reerse actie mode is shown.) Note that in a NPN transistor, currents and oltages will be negatie in the reerse actie mode. B i Β C D C α R i Ε bers-moll Model Combining the T models for the actie and reerse actie modes, one l arries at the bers-moll model for the BJT. bers and Moll hae shown that such a model in fact can be used to predict the BJT operation in all of its possible modes including saturation. PSpice uses a high-frequency ersion of bers-moll model which includes junction capacitance. B i Β D C D i DC i D C α F i D α R i DC i Ε An important contribution of the bers-moll model is an accurate description for transition from actie to saturation regions. In our simple large-signal models, we had assumed that in the actie region B junction is forward biased ( B = γ ) and a positie oltage is applied between C and B ( CB 0), thus arriing at the condition of C > γ for the actie mode. bers-moll model shows actie mode of operation can be maintained for negatie CB alues down to 0.4 V. As such, a Si BJT will moe from actie to saturation region at C 0.3 V (instead of 0.7 V). This is the reason for using sat = 0.2 V in our large-signal model. C65 Lecture Notes (F. Najmabadi), Fall

21 3.5 Field-ffect (FT) Transistors In a field-effect transistor (FT), the width of a conducting channel in a semiconductor and, therefore, its current-carrying capability, is aried by the application of an electric field (thus, the name field-effect transistor). As such, a FT is a oltage-controlled deice. The most widely used FTs are Metal-Oxide-Semiconductor FTs (or MOSFT). MOSFT can be manufactured as enhancement-type or depletion-type MOSFTs. Another type of FT is the Junction Field-ffect Transistors (JFT) which is not based on metal-oxide fabrication technique. FTs in each of these three categories can be fabricated either as a n-channel deice or a p-channel deice. As transistors in these 6 FT categories behae in a ery similar fashion, we will focus below on the operation of enhancement MOSFTs that are the most popular. n-channel nhancement-type MOSFT (NMOS) The physical structure of a n-channel nhancement-type MOSFT (NMOS) is shown. The deice is fabricated on a p-type substrate (or Body). Two heaily doped n-type regions (Source and Drain) are created in the substrate. A thin (fraction of micron) layer of SiO 2, which is an excellent electrical insulator, is deposited between source and drain region. Metal is deposited on the insulator to form the Gate of the deice (thus, metal-oxide semiconductor). Metal contacts are also made to the source, drain, and body region. To see the operation of a NMOS, let s ground the source and the body and apply a oltage GS between the gate and the source, as is shown aboe. This oltage repels the holes in the p-type substrate near the gate region, lowering the concentration of the holes. As GS increases, hole concentration decreases, and the region near gate behaes progressiely more like intrinsic semiconductor material (when excess hole concentration is zero) and then, finally, like a n-type material as electrons from n electrodes (source and drain) enter this region. As a result, when GS become larger than a threshold oltage, V t, a narrow layer between source and drain regions is created that is populated with n-type charges (see figure). The thickness of this channel is controlled by the applied GS (it is proportional to GS V t ). C65 Lecture Notes (F. Najmabadi), Fall

22 As can be seen, this deice works as a channel is induced in the semiconductor and this channel contains n-type charges (thus, n-channel MOSFT). In addition, increasing GS increases channel width (enhances it). Therefore, this is an n-channel nhancement-type MOSFT or nhancement-type NMOS. Now for a gien alues of GS > V t (so that the channel is formed), let s apply a small and positie oltage DS between drain and source. Then, electrons from n source region enter the channel and reach the drain. If DS is increased, current i D flowing through the channel increases. ffectiely, the deice acts like a resistor; its resistance is set by the dimension of the channel and its n-type charge concentration. In this region, plot of i D ersus DS is a straight line (for a gien alues of GS > V t ) as is shown. The slope of i D ersus DS line is the conductance of the channel. For GS V t no channel exists (zero conductance). As alue of GS V t increases, channel becomes wider and its conductiity increases (because its n-type charge concentration increases). Therefore, the channel conductance (slope of i D ersus DS line) increases with any increase in GS V t as is shown aboe. The aboe description is correct for small alues of DS as in that case, GD = GS DS GS and the induced channel is fairly uniform (i.e., has the same width near the drain as it has near the source). For a gien GS > V t, if we now increase DS, GD = GS DS becomes smaller than GS. As such the size of channel near drain becomes smaller compared to its size near the source, as is shown. As the size of channel become smaller, its resistance increases and the cure of i D ersus DS starts to roll oer, as is shown below. For alues of GD = V t (or DS = GS V t ), width of the channel approaches zero near the drain (channel is pinched off). Increasing DS beyond this alue has little effect (no effect in our simple picture) on the channel shape, and the current through the channel remains constant at the alue reached when DS = GS V t. So when the channel is pinched off, i D only depends on GS (right figure below). C65 Lecture Notes (F. Najmabadi), Fall

23 NMOS Characteristic Cures i D ersus GS in the saturation (or actie) region In sum, a FT can operate in three regions: 1) Cut-off region in which no channel exists ( GS < V t for NMOS) and i D = 0 for any DS. 2) Triode or Ohmic region in which the channel is formed and not pinched off ( GS > V t and DS GS V t for NMOS) and FT behaes as a oltage-controlled resistor. 3) Saturation or Actie region in which the channel is pinched off ( GS V t and DS > GS V t for NMOS) and i D does not change with DS. As can be seen from NMOS physical structure, the deice is symmetric, that is position of drain and source can be replaced without any change in deice properties. The circuit symbol for a NMOS is shown on the right. For most applications, howeer, the body is connected to the source, leading to a 3-terminal element. In that case, source and drain are not interchangeable. A simplified circuit symbol for this configuration is usually used. By conention, current i D flows into the drain for a NMOS (see figure). As i G = 0, the same current will flow out of the source. Direction of arrows used to identify semiconductor types in a transistor may appear confusing. The arrows do NOT represent the direction of current flow in the deice. Rather, they denote the type of the underlying pn junction: arrow pointing inward for p-type, arrow pointing outward for n-type. For a NMOS, the arrow is placed on the body and pointing inward as the body is made of p-type material. (Arrow is not on source or drain as they are interchangeable.) In the simplified symbol for the case when body and source is connected, arrow is on the source (deice is not symmetric now) and is pointing outward as the source is made of n-type materials.. C65 Lecture Notes (F. Najmabadi), Fall G G D S D S i D B G D S i D

24 3.6 NMOS Large Signal Model Like BJT, a NMOS (with source connected to body) has six parameters (three oltages and three currents), two of which (i S and GD ) can be found in terms of the other four by KVL and KCL. NMOS is simpler than BJT because i G = 0 (and i S = i D ). Therefore, three parameters describe behaior of a NMOS ( GS, i D, and DS ). NMOS has one characteristics equation that relates these three parameters. Again, situation is simpler than BJT as simple but accurate characteristics equations exist. Cut-off: GS < V t, i D = 0 for any DS Triode: GS > V t, i D = K[2 DS ( GS V t ) 2 DS ] for DS < GS V t Saturation: GS > V t, i D = K( GS V t ) 2 for DS > GS V t In the aboe, K and V t are constants that depend on manufacturing of the NMOS (gien in manufacturer spec sheets). As mentioned aboe, for small alues of DS ( DS GS V t ), NMOS behaes as resistor, r DS, and the alue of r DS is controlled by GS V t. This can be seen by dropping 2 DS in i D equation of triode region: r DS = DS i D 1 2K( GS V t ) p-channel nhancement-type MOSFT (PMOS) The physical structure of a PMOS is identical to a NMOS except that the semiconductor types are interchanged, i.e., body and gate are made of n-type material and source and drain are made of p-type material and a p-type channel is formed. As the sign of the charge carriers are reersed, all oltages and currents in a PMOS are reersed. By conention, the drain current is flowing out of the drain as is shown. With this, all of the NMOS discussion aboe applies to PMOS as long as we multiply all oltages by a minus sign: G G D S D S i D B G D S i D Cut-off: GS > V t, i D = 0 for any DS Triode: GS < V t, i D = K[2 DS ( GS V t ) 2 DS ] for DS > GS V t Saturation: GS < V t, i D = K( GS V t ) 2 for DS < GS V t Note that V t is negatie for a PMOS. C65 Lecture Notes (F. Najmabadi), Fall

25 Seeral important point should be noted: 1) No current flows into the gate, i G = 0 (note the insulator between gate and the body). 2) When FT is in cut-off, i D = 0. Howeer, i D = 0, does not mean that FT is in cut-off. FT is in cut-off only when no channel exists ( GS < V t ) and i D = 0 for any applied DS. Howeer, FT can be in triode region, i.e., a channel is formed, but i D = 0 because DS = 0. 3) The FT saturation region is called saturation because i D is saturated in this region and does not increase further. Some of the modern books call this actie region as it is equialent to actie-linear region of a BJT (and not the BJT saturation). 4) The i D DS characteristic cures of a FT look similar to C cures of a BJT. In fact, as there is a unique relationship between i B and B, the C cures of a BJT can be labeled with different alues of B instead of i B, making the characteristic cures of the two deices een more similar: In FT GS control deice behaior and in BJT B. Both deices are in cut-off when the input oltage is below a threshold alue: B < γ for NPN BJT and GS < V t for NMOS. They exhibit a linear region in which the output current ( or i D ) is roughly constant as the output oltage ( C or DS ) is changed. There are, howeer, major differences. Most importantly, a BJT requires i B to operate but in a FT i G = 0 (actually ery small). These differences become clearer as we explore FTs. Recipe for soling NMOS & PMOS Circuits: Solution method is ery similar to BJT circuit. For a NMOS circuit (PMOS in parenthesis): 1) Write down a KVL including GS terminals (call it GS-KVL) and a KVL including DS terminals (call it DS-KVL). 3) From GS-KVL, compute GS (using i G = 0) 3a) If GS < V t, NMOS is in cut-off (PMOS: GS < V t ). Let i D = 0, sole for DS from DS-KVL. We are done. 3b) If GS > V t, NMOS is not in cut-off (PMOS: GS > V t ). Go to step 4. 4) Assume NMOS is in saturation region. Compute i D from i D = K( GS V t ) 2. Then, use DS-KVL to compute DS. If DS > GS V t (PMOS: DS > GS V t ), we are done. Otherwise go to step 5. 5) NMOS has to be in triode region. Substitute for i D from i D = K[2 DS ( GS V t ) 2 DS] in DS-KV to get a quadratic equation in DS. Find DS (one of the two roots would be unphysical). Check that DS < GS V t (PMOS: DS < GS V t ). Substitute DS in DS-KVL to find i D. (In sum, for PMOS recipe, replace GS, DS, and V t with GS, DS, and V t in the NMOS recipe.) C65 Lecture Notes (F. Najmabadi), Fall

26 xample: Consider NMOS circuit below with K = 0.25 ma/v 2 and V t = 2 V. Find o when i = 0, 6, and 12 V for R D = 1 KΩ and V DD = 12 V. GS-KVL: GS = i V DD DS-KVL: V DD = R D i D DS R D o A) i = 0 V. From GS-KVL, we get GS = i = 0. As GS < V t = 2 V, NMOS is in cut-off, i D = 0, and DS is found from DS-KVL: i G D S i D DS-KVL: o = DS = V DD R D i D = 12 V B) i = 6 V. From GS-KVL, we get GS = i = 6 V. Since GS = 6 > V t = 2, NMOS is not in cut-off. Assume NMOS in saturation region. Then: i D = K( GS V t ) 2 = (6 2) 2 = 4 ma DS-KVL: DS = V DD R D i D = = 8 V Since DS = 8 > GS V t = 4, NMOS is indeed in saturation region and i D = 4 ma and o = DS = 8 V. C) i = 12 V. From GS-KVL, we get GS = 12 V. Since GS > V t, NMOS is not in cut-off. Assume NMOS in saturation region. Then: i D = K( GS V t ) 2 = (12 2) 2 = 25 ma DS-KVL: DS = V DD R D i D = = 13 V Since DS = 13 < GS V t = 12 2 = 10, NMOS is NOT in saturation region. Assume NMOS in triode region. Then: i D = K[2 DS ( GS V t ) 2 DS ] = [2 DS (12 2) 2 DS ] i D = [20 DS 2 DS ] Substituting for i D in DS-KVL, we get: DS-KVL: V DD = R D i D DS 12 = [20 DS 2 DS ] DS 2 DS 24 DS 48 = 0 C65 Lecture Notes (F. Najmabadi), Fall

27 This is a quadratic equation in DS. The two roots are: DS = 2.2 V and DS = 21.8 V. The second root is not physical as the circuit is powered by a 12 V supply. Therefore, DS = 2.2 V. As DS = 2.2 < GS V t = 10, NMOS is indeed in triode region with o = DS = 2.2 V and DS-KVL: DS = V DD R D i D i D = , 000 = 9.8 ma Load Line: Operation of NMOS circuits can be better understood using the concept of load line. Similar to BJT, load line is basically the line representing DS-KVL in i D ersus DS space. Load line of the example circuit is shown here. xercise: Mark the Q-points of the preious example for i = 0, 6, and 12 V on the load line figure below. Body ffect In deriing NMOS (and other MOS) i D ersus DS characteristics, we had assumed that the body and source are connected. This is not possible in an integrated chip which has a common body and a large number of MOS deices (connection of body to source for all deices means that all sources are connected). The common practice is to attach the body of the chip to the smallest oltage aailable from the power supply (zero or negatie). In this case, the pn junction between the body and source of all deices will be reersed biased. The impact of this to lower threshold oltage for the MOS deices slightly and its called the body effect. Body effect can degrade deice performance. For analysis here, we will assume that body effect is negligible. C65 Lecture Notes (F. Najmabadi), Fall

28 3.7 MOSFT Inerters and Switches NMOS Inerters and Switches The basic NMOS inerter circuit is shown; the circuit is ery similar to a BJT inerter. This circuit was soled in page 88 for V DD = 12 and R D = 1 kω. We found that if i = 0 (in fact i < V t ), NMOS will be in cut-off with i D = 0 and o = V DD. When i = 12 V, NMOS will be in triode region with i D = 10 ma and DS = 2.2 V. Therefore, the circuit is an inerter gate. It can also be used as switch. There are some important difference between NMOS and BJT inerter gates. First, BJT needs a resistor R B. This resistor conerts the input oltage into an i B and keep B γ. NMOS does not need a resistor between the source and the input oltage as i G = 0 and i = GS can be directly applied to the gate. Second, if the input oltage is high, the BJT will go into saturation with o = C = sat = 0.2 V. In the NMOS gate, if the input oltage is high, NMOS is in the triode region. In this case, DS can hae any alue between 0 and GS V t ; the alue of o = DS is set by the alue of the resistor R D. This effect is shown in the figure. xercise: Compute o for the aboe circuit with V DD = 12 and R D = 10 kω when i = 12 V. i G R D D S V DD i D o Complementary MOS (CMOS) Complementary MOS technology employs MOS transistors of both polarities as is shown below. CMOS deices are more difficult to fabricate than NMOS, but many more powerful circuits are possible with CMOS configuration. As such, most of MOS circuits today employ CMOS configuration and CMOS technology is rapidly taking oer many applications that were possible only with bipolar deices a few years ago. V DD G 2 S 2 i D 2 i D2 o G 1 D 1 i D1 S 1 C65 Lecture Notes (F. Najmabadi), Fall

29 CMOS Inerter The CMOS inerter, the building block of CMOS logic gates, is shown below. The low and high states for this circuit correspond to 0 and V DD, respectiely. CMOS gates are built on the same chip such that both NMOS and PMOS hae the same threshold oltage V tn = V t, V tp = V t and same K (one needs different channel length and width to get the same K for PMOS and NMOS). In this case, the CMOS will hae a symmetric transfer characteristics, i.e., o = 0.5V DD when i = 0.5V DD as is shown below. This circuit works only if V DD > 2V t by a comfortable margin. i = 0 Since GS1 = i = 0 < V t, NMOS will be in cut-off. Therefore, i D1 = 0. Since GS2 = i V DD = V DD < V t, PMOS will be ON while i D2 = i D1 = 0. Recall i D ersus DS characteristic cures of a NMOS (page 85), each labeled with a alues of V GS. As GS2 = V DD < V t (PMOS ON), operating point of PMOS will be on one of the cures and not on the horizontal axis. But i D2 = 0 and the only point that satisfies this condition is DS2 = 0. Note that PMOS is NOT in cut-off, it is in triode region and acts like a resistor. DS2 = 0 because i D2 = 0. Output oltage can now be found by KVL: o = V DD DS2 = V DD. So, when i = 0, o = V DD. i = V DD Since GS1 = i = V DD > V t, NMOS will be ON. Since GS2 = i V DD = 0 > V t, PMOS will be in cut-off and i D2 = 0. Since i D1 = i D2 = 0 and NMOS is ON, NMOS should be in triode region with DS1 = 0. Then o = DS1 = 0. So, when i = V DD, o = 0 i = 0.5V DD In this case, GS1 = i = 0.5V DD and GS2 = i V DD = 0.5V DD. Since, GS1 > V t and GS2 < V t, both transistors will be ON. Furthermore, as transistors hae same threshold oltage, same K, i D1 = i D2, and GS1 = GS2, both transistor will be in the same state (either triode or saturation) and will hae identical DS : DS1 = DS2. Since DS1 DS2 = V DD, then DS1 = 0.5V DD, DS2 = 0.5V DD, and o = 0.5V DD. Note that since V DD > 2V t, both transistors are in the saturation region. The transfer function of the CMOS inerter is shown below. V o NMOS Off PMOS Ohmic NMOS Actie PMOS Ohmic NMOS Actie PMOS Actie NMOS Ohmic PMOS Actie NMOS Ohmic PMOS Off V i C65 Lecture Notes (F. Najmabadi), Fall