Review: Performance and Technology Trends. CS152 Computer Architecture and Engineering Lecture 4. Cost and Design

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1 Review: Performance and Technology Trends 000 C52 Computer rchitecture and Engineering Lecture 4 Cost and Design eptember 8, 999 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: Lec4. Performance 00 0 upercomputers Minicomputers Microprocessors Mainframes Year Technology Power:.2 x.2 x.2 =.7 x / year Feature ize: shrinks 0% / yr. => witching speed improves.2 / yr. Density: improves.2x / yr. Die rea:.2x / yr. RIC lesson is to keep the I as simple as possible: horter design cycle => fully exploit the advancing technology (~3yr) dvanced branch prediction and pipeline techniques Bigger and more sophisticated on-chip caches Lec4.2 B X Review: General C/L Cell Delay Model... Combinational Logic Cell Vout Cout Combinational Cell (symbol) is fully specified by: functional (input -> output) behavior - truth-table, logic equation, VHDL load factor of each input critical propagation delay from each input to each output for each transition - T HL (, o) = Fixed Internal Delay + Load-dependent-delay x load Linear model composes Internal Delay Delay Va -> Vout X X X X X X delay per unit load Ccritical Cout Lec4.3 Review: Characterize a Gate Input capacitance for each input For each input-to-output path: For each output transition type (H->L, L->H, H->Z, L->Z... etc.) - Internal delay (ns) - Load dependent delay (ns / ff) Example: 2-input NND Gate B Out For and B: Input Load (I.L.) = 6 ff For either -> Out or B -> Out: Tlh = 0.5ns Tlhf = 0.002ns / ff Thl = 0.ns Thlf = ns / ff 0.5ns Delay -> Out Out: Low -> High lope = 0.002ns / ff Cout Lec4.4

2 Review: Technology, Logic Design and Delay Overview: Cost and Design CMO Technology Trends Complementary: PMO and NMO transistors CMO inverter and CMO logic gates Delay Modeling and Gate Characterization Delay = Internal Delay + (Load Dependent Delay x Output Load) Clocking Methodology and Timing Considerations implest clocking methodology - ll storage elements use the ME clock edge Cycle Time = CLK-to-Q + Longest Delay Path + etup + Clock kew (CLK-to-Q + hortest Delay Path - Clock kew) > Hold Time Review from Last Lecture (2 minutes) Cost and Price (8) dministrative Matters (3 minutes) Design process (27 minutes) Break (5 minutes) More Design process (5 minutes) Online notebook (0 minutes) Lec4.5 Lec4.6 Integrated Circuit Costs Die Yield Die cost = Wafer cost Dies per Wafer * Die yield Dies per wafer = π * ( Wafer_diam / 2) 2 π * Wafer_diam Test dies Wafer rea Die rea 2 * Die rea Die rea Raw Dice Per Wafer wafer diameter die area (mm 2 ) /5cm /20cm /25cm die yield 23% 9% 6% 2% % 0% typical CMO process: α =2, wafer yield=90%, defect density=2/cm2, 4 test sites/wafer Die Yield = Wafer yield α Defects_per_unit_area * Die_rea { + } α Die Cost is goes roughly with the cube of the area. Lec4.7 Good Dice Per Wafer (Before Testing!) 6 /5cm /20cm /25cm typical cost of an 8, 4 metal layers, 0.5um CMO wafer: ~$2000 Lec4.8

3 Real World Examples Other Costs Chip Metal Line Wafer Defect rea Dies/ Yield Die Cost layers width cost /cm 2 mm 2 wafer 386DX $ % $4 486DX $ % $2 PowerPC $ % $53 HP P $ % $73 DEC lpha $ % $49 uperprc $ % $272 Pentium $ % $47 From "Estimating IC Manufacturing Costs, by Linley Gwennap, Microprocessor Report, ugust 2, 993, p. 5 IC cost = Die cost + Testing cost + Packaging cost Final test yield Packaging Cost: depends on pins, heat dissipation Chip Die Package Test & Total cost pins type cost ssembly 386DX $4 32 QFP $ $4 $9 486DX2 $2 68 PG $ $2 $35 PowerPC 60 $ QFP $3 $2 $77 HP P 700 $ PG $35 $6 $24 DEC lpha $49 43 PG $30 $23 $202 uperprc $ PG $20 $34 $326 Pentium $ PG $9 $37 $473 Lec4.9 Lec4.0 ystem Cost: Workstation Cost vs. Price ystem ubsystem % of total cost Cabinet heet metal, plastic % Power supply, fans 2% Cables, nuts, bolts % (ubtotal) (4%) Motherboard Processor 6% DRM (64MB) 36% Video system 4% I/O system 3% Printed Circuit board % (ubtotal) (60%) I/O Devices Keyboard, mouse % Monitor 22% Hard disk ( GB) 7% Tape drive (DT) 6% (ubtotal) (36%) Lec4. Q: What % of company income on Research and Development (R&D)? Component Cost Input: chips, displays,... avg. selling price % Gross Margin +33% Direct Costs component cost Making it: labor, scrap, returns,... list price direct costs component cost Overhead: R&D, rent, marketing, profits, % verage Discount gross margin direct costs component cost Commision: channel profit, volume discounts, (W PC) (33 45%) (33 4%) (8 0%) (25 3%) Lec4.2

4 Cost ummary dministrative Matters Integrated circuits driving computer industry Die costs goes up with the cube of die area Economics ($$$) is the ultimate driver for performance! Review complete: did ok on prob 2 & 3 Problems and 4 more challenging Make sure you look at solutions! (out soon) Read Chapter 4: LU, Multiply, Divide, FP Mult Dollars for bugs! First to report bug gets $ check end bug/ to mkp@mkp.com Include page number, orginal text, why bug, fixed text Lec4.3 Lec4.4 The Design Process Design Process (cont.) "To Design Is To Represent" Design activity yields description/representation of an object -- Traditional craftsman does not distinguish between the conceptualization and the artifact -- eparation comes about because of complexity -- The concept is captured in one or more representation languages -- This process I design Design Begins With Requirements -- Functional Capabilities: what it will do Design Finishes s ssembly -- Design understood in terms of components and how they have been assembled -- Top Down decomposition of complex functions (behaviors) into more primitive functions Datapath -- bottom-up composition of primitive building blocks into more complex assemblies CPU LU Regs hifter Nand Gate Control Design is a "creative process," not a simple method -- Performance Characteristics: peed, Power, rea, Cost,... Lec4.5 Lec4.6

5 Design Refinement Informal ystem Requirement Initial pecification Intermediate pecification Final rchitectural Description Intermediate pecification of Implementation Final Internal pecification refinement increasing level of detail Design as earch Problem trategy trategy 2 ubprob ubprob2 ubprob3 BB BB2 BB3 BBn Design involves educated guesses and verification -- Given the goals, how should these be prioritized? -- Given alternative design pieces, which should be selected? -- Given design space of components & assemblies, which part will yield the best solution? Physical Implementation Lec4.7 Feasible (good) choices vs. Optimal choices Lec4.8 Problem: Design a fast LU for the MIP I MIP LU requirements Requirements? Must support the rithmetic / Logic operations Tradeoffs of cost and speed based on frequency of occurrence, hardware budget dd, ddu, ub, ubu, ddi, ddiu => 2 s complement adder/sub with overflow detection nd, Or, ndi, OrI, Xor, Xori, Nor => Logical ND, logical OR, XOR, nor LTI, LTIU (set less than) => 2 s complement adder with inverter, check sign bit of result LU from from C 50 / P&H book chapter 4 supports these ops Lec4.9 Lec4.20

6 MIP arithmetic instruction format R-type: I-Type: Type op funct DDI 0 xx DDIU xx LTI 2 xx LTIU 3 xx NDI 4 xx ORI 5 xx XORI 6 xx LUI 7 xx op Rs Rt Rd funct op Rs Rt Immed 6 Type op funct DD DDU 00 4 UB UBU ND OR XOR NOR igned arith generate overflow, no carry Type op funct LT LTU Lec4.2 Design Trick: divide & conquer Break the problem into simpler problems, solve them and glue together the solution Example: assume the immediates have been taken care of before the LU 0 operations (4 bits) 00 add 0 addu 02 sub 03 subu 04 and 05 or 06 xor 07 nor 2 slt 3 sltu Lec4.22 Refined Requirements () Functional pecification inputs: 2 x 32-bit operands, B, 4-bit mode outputs: 32-bit result, -bit carry, bit overflow operations: add, addu, sub, subu, and, or, xor, nor, slt, sltu (2) Block Diagram (powerview symbol, VHDL entity) c ovf LU 32 B m 4 Behavioral Representation: VHDL Entity LU is generic (c_delay: integer := 20 ns; _delay: integer := 20 ns); port ( signal, B: in vlbit_vector (0 to 3); signal m: in vlbit_vector (0 to 3); signal : out vlbit_vector (0 to 3); signal c: out vlbit; signal ovf: out vlbit) end LU;... <= + B; Lec4.23 Lec4.24

7 Design Decisions Refined Diagram: bit-slice LU LU 32 B 32 bit slice imple bit-slice 7-to-2 C/L big combinational problem many little combinational problems partition into 2-step problem 7 3-to-2 C/L PLD Gates CL0 CL6 mux a3 b3 LU3 m co cin s3 Ovflw 32 a0 LU0 co s0 b0 m cin 4 M Bit slice with carry look-ahead... Lec4.25 Lec to-2 Combinational Logic start turning the crank... Function Inputs Outputs K-Map M0 M M2 M3 B Cin Cout 0 add even plus a MUX? Design trick 2: take pieces you know (or can imagine) and try to put them together Design trick 3: solve part of the problem and extend CarryIn and -select or Mux Result B -bit Full dder add 27 Lec4.27 CarryOut Lec4.28

8 dditional operations - B = + ( B) = + B + form two complement by invert and add one -select invert CarryIn and Revised Diagram LB and MB need to do a little extra 32 B 32 B -bit Full dder or add CarryOut Mux Result? a3 b3 LU0 co cin s3 Ovflw 32 a0 LU0 co s0 b0 cin 4 M C/L to produce select, comp, c-in et-less-than? left as an exercise Lec4.29 Lec4.30 Overflow Overflow Detection Decimal Binary Examples: = 0 but = - 9 but... Decimal s Complement Overflow: the result is too large (or too small) to represent properly Example: bit binary number 7 When adding operands with different signs, overflow cannot occur! Overflow occurs when adding: 2 positive numbers and the sum is negative 2 negative numbers and the sum is positive On your own: Prove you can detect overflow by: Carry into MB Carry out of MB Lec4.3 Lec4.32

9 Overflow Detection Logic Carry into MB Carry out of MB For a N-bit LU: Overflow = CarryIn[N - ] XOR CarryOut[N - ] More Revised Diagram LB and MB need to do a little extra 0 B0 B 2 B2 3 B3 CarryIn0 -bit Result0 LU CarryIn CarryOut0 -bit Result LU CarryIn2 CarryOut -bit Result2 LU CarryIn3 -bit Result3 LU CarryOut3 X Y X XOR Y Overflow signed-arith and cin xor co Ovflw a3 b3 LU0 co cin s3 32 B 32 a0 b0 LU0 co cin s M C/L to produce select, comp, c-in Lec4.33 Lec4.34 But What about Performance? Critical Path of n-bit Rippled-carry adder is n*cp CarryIn0 0 -bit Result0 B0 LU CarryIn CarryOut0 -bit Result B LU CarryIn2 CarryOut 2 -bit Result2 B2 LU CarryIn3 CarryOut2 3 -bit Result3 B3 LU CarryOut3 Design Trick: Throw hardware at it 0 B0 B 2 B2 3 B3 Carry Look head (Design trick: peek) G P G P G P G P C0 = Cin C = G0 + C0 P0 C2 = G + G0 P + C0 P0 P B C-out kill 0 C-in propagate 0 C-in propagate generate P = and B G = xor B C3 = G2 + G P2 + G0 P P2 + C0 P0 P P2 G P Lec4.35 C4 =... Lec4.36

10 Plumbing as Carry Lookahead nalogy Cascaded Carry Look-ahead (6-bit): bstraction g0 c g p0 g0 c0 p p0 c0 g0 p0 c0 C L 4-bit dder C0 G0 P0 C = G0 + C0 P0 C2 = G + G0 P + C0 P0 P c2 g p 4-bit dder g2 p2 g3 p3 c4 Lec bit dder C3 = G2 + G P2 + G0 P P2 + C0 P0 P P2 G P C4 =... Lec4.38 2nd level Carry, Propagate as Plumbing Design Trick: Guess (or Precompute ) p0 g0 CP(2n) = 2*CP(n) n-bit adder n-bit adder p2 p g p CP(2n) = CP(n) + CP(mux) P0 p3 g3 G0 g2 p3 p2 Cout n-bit adder n-bit adder 0 n-bit adder Carry-select adder Lec4.39 Lec4.40

11 Carry kip dder: reduce worst case delay dditional MIP LU requirements B 4 4-bit Ripple dder P3 P2 P P0 Just speed up the slowest case for each block B 0 4-bit Ripple dder P3 P2 P P0 Mult, MultU, Div, DivU (next lecture) => Need 32-bit multiply and divide, signed and unsigned ll, rl, ra (next lecture) => Need left shift, right shift, right shift arithmetic by 0 to 3 bits Nor (leave as exercise to reader) => logical NOR or use 2 steps: ( OR B) XOR... Exercise: optimal design uses variable block sizes Lec4.4 Lec4.42 Elements of the Design Process Divide and Conquer (e.g., LU) Formulate a solution in terms of simpler components. Design each of the components (subproblems) Generate and Test (e.g., LU) Given a collection of building blocks, look for ways of putting them together that meets requirement uccessive Refinement (e.g., carry lookahead) olve "most" of the problem (i.e., ignore some constraints or special cases), examine and correct shortcomings. Formulate High-Level lternatives (e.g., carry select) rticulate many strategies to "keep in mind" while pursuing any one approach. Work on the Things you Know How to Do The unknown will become obvious as you make progress. Lec4.43 ummary of the Design Process Hierarchical Design to manage complexity Top Down vs. Bottom Up vs. uccessive Refinement Importance of Design Representations: Block Diagrams Decomposition into Bit lices top bottom down up Truth Tables, K-Maps mux design Circuit Diagrams meets at TT Other Descriptions: state diagrams, timing diagrams, reg xfer,... Optimization Criteria: Gate Count rea [Package Count] Pin Out Logic Levels Fan-in/Fan-out Cost Delay Design time Power Lec4.44

12 Why should you keep an design notebook? Keep track of the design decisions and the reasons behind them Otherwise, it will be hard to debug and/or refine the design Write it down so that can remember in long project: 2 weeks ->2 yrs Others can review notebook to see what happened Record insights you have on certain aspect of the design as they come up Record of the different design & debug experiments Memory can fail when very tired Industry practice: learn from others mistakes Why do we keep it on-line? You need to force yourself to take notes Open a window and leave an editor running while you work ) cts as reminder to take notes 2) Makes it easy to take notes ) + 2) => will actually do it Take advantage of the window system s cut and paste features It is much easier to read your typing than your writing lso, paper log books have problems Limited capacity => end up with many books May not have right book with you at time vs. networked screens Can use computer to search files/index files to find what looking for Lec4.45 Lec4.46 How should you do it? On-line Notebook Example Keep it simple DON T make it so elaborate that you won t use (fonts, layout,...) eparate the entries by dates type date command in another window and cut&paste Refer to the handout Example of On-Line Log Book on cs 52 home page tart day with problems going to work on today Record output of simulation into log with cut&paste; add date May help sort out which version of simulation did what Record key with cut&paste Record of what works & doesn t helps team decide what went wrong after you left Index: write a one-line summary of what you did at end of each day Lec4.47 Lec4.48

13 st page of On-line notebook (Index + Wed. 9/6/95) * Index ============================================================== Wed ep 6 00:47:28 PDT Created the 32-bit comparator component Thu ep 7 4:02:2 PDT Tested the comparator Mon ep 2:0:45 PDT Investigated bug found by Bart in comp32 and fixed it + ==================================================================== Wed ep 6 00:47:28 PDT 995 Goal: Layout the schematic for a 32-bit comparator I ve layed out the schemtatics and made a symbol for the comparator. I named it comp32. The files are ~/wv/proj/sch/comp32.sch ~/wv/proj/sch/comp32.sym Wed ep 6 02:29:22 PDT ==================================================================== 2nd page of On-line notebook (Thursday 9/7/95) + ==================================================================== Thu ep 7 4:02:2 PDT 995 Goal: Test the comparator component I ve written a command file to test comp32. I ve placed it in ~/wv/proj/diagnostics/comp32.cmd. I ran the command file in viewsim and it looks like the comparator is working fine. I saved the output into a log file called ~/wv/proj/diagnostics/comp32.log Notified the rest of the group that the comparator is done. Thu ep 7 6:5:32 PDT ==================================================================== dd line index at front of log file at end of each session: date+summary tart with date, time of day + goal Make comments during day, summary of work End with date, time of day (and add line summary at front of file) Lec4.49 Lec4.50 3rd page of On-line notebook (Monday 9//95) + =================================================================== Mon ep 2:0:45 PDT 995 Goal: Investigate bug discovered in comp32 and hopefully fix it Bart found a bug in my comparator component. He left the following From bart@simpsons.residence un ep 0 0:47: Received: by wayne.manor (NX5.67e/NX3.0) id 00334; un, 0 ep 95 0:47: Date: Wed, 0 ep 95 0:47: From: Bart impson <bart@simpsons.residence> To: bruce@wanye.manor, old_man@gokuraku, hojo@sanctuary ubject: [cs52] bug in comp32 tatus: R Hey Bruce, I think there s a bug in your comparator. The comparator seems to think that ffffffff and fffffff7 are equal. Can you take a look at this? Bart th page of On-line notebook (9//95 contd) I verified the bug. here s a viewsim of the bug as it appeared.. (equal should be 0 instead of ) IM>stepsize 0ns IM>v a_in [3:0] IM>v b_in B[3:0] IM>w a_in b_in equal IM>a a_in ffffffff\h IM>a b_in fffffff7\h IM>sim time = 0.0ns _IN=FFFFFFFF\H B_IN=FFFFFFF7\H EQUL= imulation stopped at 0.0ns h. I ve discovered the bug. I mislabeled the 4th net in the comp32 schematic. I corrected the mistake and re-checked all the other labels, just in case. I re-ran the old diagnostic test file and tested it against the bug Bart found. It seems to be working fine. hopefully there aren t any more bugs:) Lec4.5 Lec4.52

14 5th page of On-line notebook (9//95 contd) On second inspectation of the whole layout, I think I can remove one level of gates in the design and make it go faster. But who cares! the comparator is not in the critical path right now. the delay through the LU is dominating the critical path. so unless the LU gets a lot faster, we can live with a less than optimal comparator. dded benefit: cool post-design statistics ample graph from the lewife project: I ed the group that the bug has been fixed Mon ep 4:03:4 PDT ================================================================ For the Communications and Memory Management Unit (CMMU) These statistics came from on-line record of bugs Perhaps later critical path changes; what was idea to make compartor faster? Check log book! Lec4.53 Lec4.54 Lecture ummary Cost and Price Die size determines chip cost: cost - die size (α +) Cost v. Price: business model of company, pay for engineers R&D must return $8 to $4 for every $ invester n Overview of the Design Process Design is an iterative process, multiple approaches to get started Do NOT wait until you know everything before you start Example: Instruction et drives the LU design On-line Design Notebook Open a window and keep an editor running while you work;cut&paste Refer to the handout as an example Former C 52 students (and Ts) say they use on-line notebook for programming as well as hardware design; one of most valuable skills Lec4.55