07/11/08. Avnet, Inc. Engineering Services Copyright Avnet Engineering Services

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1 Spartan- SP Starter oard vnet ngineering Services Function over Sheet lock iagram FPG ank 0 FPG ank FPG ank FPG ank FPG Power R Memory R Termination onfig/flash Memory 0/00/000 PHY PHY Power Out XP onnector (JX) XP onnector (JX) oard Power Revision History Sheet Number 0 Xilinx ocument ontrol Number 0 Xilinx is disclosing this ocument and Intellectual Property (hereinafter the esign ) to you for use in the development designs to operate on, or interface with Xilinx FPGs. xcept as stated herein, none the esign may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent Xilinx. ny unauthorized use the esign may violate copyright laws, trademark laws, the laws privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out the application or use the esign; nor does Xilinx convey any license under its patents, copyrights, or any rights others. You are responsible for obtaining any rights you may require for your use or implementation the esign. Xilinx reserves the right to make changes, at any time, to the esign as deemed desirable in the sole discretion Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness any engineering or technical support or assistance provided to you in connection with the esign. TH SIGN IS PROVI S IS WITH LL FULTS, N TH NTIR RISK S TO ITS FUNTION N IMPLMNTTION IS WITH YOU. YOU KNOWLG N GR THT YOU HV NOT RLI ON NY ORL OR WRITTN INFORMTION OR VI, WHTHR GIVN Y XILINX, OR ITS GNTS OR MPLOYS. XILINX MKS NO OTHR WRRNTIS, WHTHR XPRSS, IMPLI, OR STTUTORY, RGRING TH SIGN, INLUING NY WRRNTIS OF MRHNTILITY, FITNSS FOR PRTIULR PURPOS, TITL, N NONINFRINGMNT OF THIR-PRTY RIGHTS. IN NO VNT WILL XILINX LIL FOR NY ONSQUNTIL, INIRT, XMPLRY, SPIL, OR ININTL MGS, INLUING NY LOST T N LOST PROFITS, RISING FROM OR RLTING TO YOUR US OF TH SIGN, VN IF YOU HV N VIS OF TH POSSIILITY OF SUH MGS. TH TOTL UMULTIV LIILITY OF XILINX IN ONNTION WITH YOUR US OF TH SIGN, WHTHR IN ONTRT OR TORT OR OTHRWIS, WILL IN NO VNT X TH MOUNT OF FS PI Y YOU TO XILINX HRUNR FOR US OF TH SIGN. YOU KNOWLG THT TH FS, IF NY, RFLT TH LLOTION OF RISK ST FORTH IN THIS GRMNT N THT XILINX WOUL NOT MK VILL TH SIGN TO YOU WITHOUT THS LIMITTIONS OF LIILITY. 0//0 The esign is not designed or intended for use in the development on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems ( High-Risk pplications ). Xilinx specifically disclaims any express or implied warranties fitness for such High-Risk pplications. You represent that use the esign in such High-Risk pplications is fully at your risk Xilinx, Inc. ll rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks Xilinx, Inc. ll other trademarks are the property their respective owners. vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - Lead Sheet Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

2 vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - lock iagram Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

3 ,, XP_S_IO_[0:] XP_S_IO_[0:] XP_IFF_p[0:] XP_IFF_n[0:] 0 0.uF.V U V / OUT OS_Hx_mhZ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_IFF_p0 XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p0 XP_IFF_p XP_IFF_n0 XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n0 XP_IFF_n R R0 LK_MHz NK 0 U _VRF_0 _VRF_0 _VRF_0 G G H H J0 J J _VRF_0 J IO_L0p_0 G0 IO_L0n_0 F0 IO_L0p_0_VRF_0 G IO_L0n_0 F IO_L0p_0 IO_L0n_0 IO_L0p_0 IO_L0n_0 IO_L0p_0 IO_L0n_0 IO_L0p_0 H IO_L0n_0 G IO_L0p_0 IO_L0n_0 IO_L0p_0 IO_L0n_0 IO_Lp_0 0 IO_Ln_0 0 IO_Lp_0 J IO_Ln_0 K IO_Lp_0 F IO_Ln_0 IO_Lp_0_VRF_0 0 IO_Ln_0 0 IO_Lp_0 IO_Ln_0 IO_Lp_0 G IO_Ln_0 H IO_Lp_0 IO_Ln_0 IO_Lp_0 IO_Ln_0 IO_Lp_0 IO_Ln_0 IO_L0p_0 F IO_L0n_0_VRF_0 IO_Lp_0 IO_Ln_O IO_Lp_0 IO_Ln_0 IO_Lp_0 IO_Ln_0 IO_Lp_0 IO_Ln_0 F IO_Lp_0_GLK K IO_Ln_0_GLK J IO_Lp_0_GLK IO_Ln_0_GLK IO_Lp_0_GLK F IO_Ln_0_GLK G IO_Lp_0_GLK0 IO_Ln_0_GLK IO_Lp_0 IO_Ln_0 IO_L0p_0 IO_L0n_0 IO_Lp_0 IO_Ln_0 F IO_Lp_0 IO_Ln_0_VRF_0 IO_Lp_0 0 IO_Ln_0 0 IO_Lp_0 0 IO_Ln_0 0 IO_Lp_0 G IO_Ln_0 H IO_Lp_0 IO_Ln_0 IO_Lp_0 0 IO_Ln_0 IO_Lp_0 IO_Ln_0 IO_Lp_0 J IO_Ln_0 K IO_L0p_0 IO_L0n_0 IO_Lp_0 IO_Ln_0 IO_Lp_0 IO_Ln_0 IO_Lp_0 J IO_Ln_0 K IO_Lp_0 IO_Ln_0 IO_Lp_0 IO_Ln_0 IO_Lp_0 G0 IO_Ln_0 H0 IO_Lp_0 G IO_Ln_0 H IO_Lp_0 F IO_Ln_0 IO_Lp_0 IO_Ln_0 IO_Lp_0_VRF_0 F IO_Ln_0_PU_ G G F 0 G F0 F XS00FG_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_IFF_p XP_IFF_n XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_IFF_p XP_IFF_n XP_S_IO_0 XP_S_IO_ XP_IFF_p0 XP_IFF_n0 XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n LK_MHz XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p0 XP_IFF_n0 XP_S_LK_IN XP_IFF_LK_IN_p XP_IFF_LK_IN_n XP_IFF_p0 XP_IFF_n0 XP_IFF_LK_OUT_p XP_IFF_LK_OUT_n XP_S_LK_OUT RP0 K FPG_PU RP K SW SW IP- Vcco_0 R. 0 R. Vcco_0 0.uF R K R0 0 K R J SM onnector NP K R K R SWITH_P SWITH_P SWITH_P SWITH_P SW SPST SW SPST SW SPST SW SPST Vcco_0 vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - FPG ank 0 Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

4 NK U IP_Lp VRF_ IP_Ln VRF_ IP_Ln_ IP_Lp VRF_ IP_Ln VRF_ IP_L0n VRF_ IP_Lp VRF_ IP_Ln_ IP_Lp_ IP_Ln_ IP_Lp VRF_ IP_Ln_ IP_L0p_ IP_L0n_ IO_L0p H IO_L0n L IO_L0p L IO_L0n L0 IO_L0p 0 IO_L0n IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n VRF_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln VRF_ IO_Lp IO_Ln IO_Lp IO_Ln IO_Lp IO_Ln IO_Lp IO_Ln IO_L0p RHLK0 IO_L0n RHLK IO_Lp RHLK IO_Ln TRY_RHLK IO_Lp RHLK IO_Ln RHLK IO_Lp RY_RHLK IO_Ln RHLK IO_Lp 0 IO_Ln IO_Lp_ IO_Ln_ IO_Lp IO_Ln IO_Lp IO_Ln IO_Lp_ IO_Ln_ IO_Lp IO_Ln IO_Lp IO_Ln IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp VRF_ IO_Ln_ IO_Lp_ IO_Ln_ IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp 0 IO_Ln IO_Lp IO_Ln IO_Lp IO_Ln IP_Ln_ IP_Ln_ IP_Lp_ IP_Lp_ IP_Ln_ IP_L0p_ IP_Lp_ IP_Lp_ G H H U V R R N N M N K L Y0 Y W0 W V V V U0 U U Y Y U T0 Y Y T T W V V V V U R R0 U U R R T T R R R R P P0 P P P N P N M M P N L M N N K K N0 M0 J J M M K K M M J J L K G G L0 K0 F F L L F K K F G J J0 J H H0 G Y H W U W H G FLSH_0 FLSH_ XP_S XP_S XP_S XP_S XP_S FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ LK_.MHz L L L FLSH_0 FLSH_ FPG_RS_Tx FPG_RS_Rx FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ XP_S0 XP_S XP_S L _G0 _G _G _G _0 R0 _R _R _R IGI_ IGI_ IGI_ IGI_ IGI_ IGI_ IGI_ IGI_ L L FLSH_0 FLSH_ FLSH_ FLSH_ L L SM_IRQ 0 FLSH_W# 0 FLSH_O# 0 FLSH_# 0 SPISL_ SPISL_ SPISL_ SPISL_ SM_0 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_0 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_0 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_ 0 SM_On 0 SM_Wn 0 SM_n 0 SM_RSTn 0 SM_RY 0 SUSPN _VSYN _HSYN FLSH_Reset# 0 _G[0:] _[0:] _R[0:] G_Rx_p G_Rx_n G_Tx_p G_Tx_n R R R R R R R R.V R.K R0 00 Place resistors as close as possible to the FPG R.K J ST onnector L L L L L L L L R0 R0 R0 R0 R0 R0 R0 R0 0 L_GRN L_GRN L_GRN L_GRN L_GRN L_GRN L_GRN L_GRN.V 0.uF 0.uF 0 0.uF 0.uF XP_S XP_S XP_S XP_S XP_S XP_S0 XP_S XP_S U0 N V - - V- RIN MX R LK_.MHz F_OFF V OUT F_ON IN INVLI 0 ROUT IGI_ IGI_ IGI_ IGI_ IGI_ IGI_ IGI_ IGI_ FPG_RS_Tx U O 0 FPG_RS_Rx.V R0 FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_0 FLSH_ FLSH_ FLSH_ 0.uF V 0 SNTGVR.V.V 0.uF U Vcco_ J J V OUT / OS_Hx_.mhZ.V FLSH_[0:] 0 P XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ ONNTOR R 0 0.uF 0 XS00FG_ vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - FPG ank Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

5 , XP_S_IO_[0:] XP_IFF_p[0:] XP_IFF_n[0:] XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_IFF_p0 XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p0 XP_IFF_p XP_IFF_n0 XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n0 XP_IFF_n NK U IP VRF_ IP VRF_ IP VRF_ IP_ IP VRF_ IP_ IP_ IP_ IP_ IP_ IP VRF_ IP_ IP VRF_ IP VRF_ IP VRF_ IP VRF_ IO_L0p M IO_L0n M0 IO_L0p M IO_L0n SO_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp RWR_ IO_Ln VS IO_Lp_ IO_Ln_ IO_Lp VS IO_Ln VS0 IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp IO_Ln IO_Lp_ IO_Ln_ IO_Lp IO_Ln IO_Lp GLK IO_Ln GLK IO_Lp GLK IO_Ln GLK IO_Lp GLK0 IO_Ln GLK IO_Lp GLK IO_Ln GLK IO_Lp_ IO_Ln_ IO_L0p_ IO_L0n MOSI_SI_ IO_Lp_ IO_Ln_ IO_Lp WK IO_Ln OUT IO_Lp_ IO_Ln_ IO_Lp INIT_ IO_Ln IO_Lp_ IO_Ln_ IO_Lp IO_Ln IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IOIO_Lp_ IO_Ln_ IO_Lp 0_IN_MISO IO_Ln LK IO_ IP_ IP_ IP_ IP_ IP_ IP_ IP VRF_ IP_ IP_ IP_ IP_ IP_ IP_ IP_ IP VRF IP_ XS00FG_ F F F Y Y W Y F F V0 W0 F Y0 0 V U V W Y F F V W 0 F0 F Y F Y F V W Y V U F F F V U Y W V F F F F 0 0 F Y Y Y Y W XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p0 XP_IFF_n0 XP_IFF_p0 XP_IFF_n0 XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n XP_IFF_p XP_IFF_n FLSH_ FLSH_ XP_IFF_p XP_IFF_n FLSH_ FLSH_ LK_Socket XP_IFF_p XP_IFF_n XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_IFF_p XP_IFF_n FLSH_ XP_S_IO_ XP_S_IO_ FLSH_ FLSH_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_IFF_p XP_IFF_n XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ PO_RST# SPI_SL# 0 XP_S_LK_OUT SM_LK 0 XP_IFF_p0 XP_IFF_n0 FLSH_0 FPG_M FPG_M FPG_M0 XP_IFF_LK_IN_p XP_IFF_LK_IN_n XP_S_LK_IN R R0 RP K SPI_MOSI R0 Vcco_ JP efault: JP :, : (Master SPI) K R L_GRN K Vcco_ XP_IFF_LK_OUT_p XP_IFF_LK_OUT_n FLSH_0 0 SPI_MISO 0 SPI_LK 0 FPG_LK 0 FPG_PU JP SPI_MOSI 0 FPG_INIT# 0 LK_Socket R0 R M M onfiguration Mode P Pull-up JP : JP : Master Serial Master Serial Slave Serial Slave Serial Master SPI Master SPI PI Up PI Up Slave Parallel Slave Parallel JTG JTG OUT OS No No Resistors R - R and R-R are for variant select (VS) to support SPI configuration the FPG. VS[:0] = b results in a SPI read command Fast Read (0x0) which is compatible with Intel S Flash. U V NL Fox H- compatible.v Yes Yes Yes No Yes No Yes No Yes No 0.uF losed losed Open losed losed losed Open losed Open Open Open losed losed Open Open losed Open Open losed Open losed SPISL_ SPISL_ SPISL_ SPISL_ losed.v XP_IFF_n XP_IFF_p XP_IFF_n NP M0 JP : Vcco_ FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_.V FLSH_[0:] 0 SPI_SL# SPI_MOSI SPI_MISO SPI_LK.V vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard PU_ JP : losed losed losed Open Open Open losed Open Open Open Open losed losed Open losed losed Open losed losed losed Open Open Open losed Open Open RP.K R K R K 0 J0 R K R K R K R K R.K R0.K Sheet - FPG ank Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

6 .V NK U IP_Ln_ IP_Lp_ IP_Ln VRF_ IP_L0n VRF_ IP_L0n_ IP_Ln VRF_ IP_L0p_ IP_L0n VRF_ IP_Lp_ IP_Ln_ IP_Lp_ IP_Ln_ IP_L0p_ IP_L0n VRF_ IP_Lp_ IP_Ln VRF_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln VRF_ IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp LHLK0 IO_Ln LHLK IO_Lp LHLK IO_Ln IRY_LHLK IO_Lp LHLK IO_Ln LHLK IO_Lp TRY_LHLK IO_Ln LHLK IO_Lp VRF_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp VRF_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_L0p_ IO_L0n_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IO_Lp_ IO_Ln_ IP_L0p_ IP_Lp_ IP_Lp_ IP_L0p_ IP_Lp_ IP_Lp_ IP_Ln_ IP_Ln_ FPG_R_VRF G Y H J J J K U V W W J J G H K K F F G J H F K J G F L0 L H H K L J J M0 M K K K K L L M M M M M M M M N N N N N N P P P P N P0 R R R R T T P P R R P P T U R0 R U U R R V V T0 T U V T U W W Y Y U U Y Y V V U V W W G G Y TH_RS TH_OL TH_Rx_V TH_Rx_R TH_INT# TH_Tx_0 TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_N TH_Tx_R TH_GTX_LK TH_M TH_MIO TH_RST# R_OT R_S# R_W# R_S# R_RS# R_S0 R_K R_0 R_S R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ LK_F_M FPG_R_LK_p FPG_R_LK_n FPG_R_LK0_p FPG_R_LK0_n TH_MLK M_F_LK TH_Rx_LK TH_Tx_LK FPG_R_0 FPG_R_ FPG_R_ FPG_R_ R_LM_ R_UQS_ R_UQS#_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ R_UQS_0 R_UQS#_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ R_UM_0 R_LM_0 RST_QS_IV FPG_R_ FPG_R_ FPG_R_ FPG_R_ R_LQS_ R_LQS#_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ R_LQS_0 R_LQS#_0 FPG_R_ FPG_R_ FPG_R_0 FPG_R_ TH_Rx_0 TH_Rx_ TH_Rx_ TH_Rx_ TH_Rx_ TH_Rx_ TH_Rx_ TH_Rx_ R R0 R0 R R FPG_R_S0, FPG_R_ R R0 Place R close to pin N FPG_0.V_TT FPG_R_VRF FPG_R_UM_, M_F_LK - This trace should have length equal to R_LK trace length QStrace length RST_QS_IV - The trace from T0 to T should have length equal to R_LK trace length QStrace length R R0 R Place R close to pin T 0.0uF FPG_0.V_TT 0.0uF 0.0uF 0.0uF 0.0uF.0uF.0uF.0uF.0uF R_0 R_S# R_W# R_ R_K R_ R_ R_0 R_OT R_S R_ R_RS# R_S# R_ R_ R_ R_ R_ R_ FPG_R_LK_n FPG_R_LK_p FPG_R_LK0_n FPG_R_LK0_p LK_F_M R_LM_ R_UQS_ R_UQS#_ R_UQS_0 R_UQS#_0 R_LM_0 R_UM_0 R_LQS#_ R_LQS_ R_LQS#_0 R_LQS_0 TH_MIO TH_M.V R K.V U RP R0 RP R0 RP R0 RP R0 RP R0 RP R0 RP R0 RP R0 RP R0 RP R0.V 0.uF V N G0.V FPG_R_0 FPG_R_ R FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ M_F_LK 0.uF VY Y Y Y Y 0.V 0K FPG_R_S#, FPG_R_W#, FPG_R_K R_OT_ontrol FPG_R_S, FPG_R_RS#, FPG_R_S#, FPG_R_LK_# FPG_R_LK_ FPG_R_LK_0# FPG_R_LK_0 FPG_R_LM_, FPG_R_UQS_, FPG_R_UQS#_, FPG_R_UQS_0, FPG_R_UQS#_0, FPG_R_LM_0, FPG_R_UM_0, FPG_R_LQS#_, FPG_R_LQS_, FPG_R_LQS#_0, FPG_R_LQS_0, GMII_MIO GMII_M 0 0.uF.V 0 0.uF 0 0.uF TH_RS TH_OL TH_Rx_V TH_Rx_R TH_INT# TH_MLK TH_Rx_LK TH_Tx_LK TH_Rx_0 TH_Rx_ TH_Rx_ TH_Rx_ TH_Rx_ TH_Rx_ TH_Rx_ TH_Rx_ 00 0.uF TH_Tx_0 TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_ TH_Tx_N TH_Tx_R TH_GTX_LK TH_RST#.V.V.V FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ U V V H V V H 0 F F G G H H J J K K 0 IR O SNV0TZQL U V V H V V H 0 F F G G H H J J K K 0 IR O 0 F F G G H H J J K 0 K IR K O K G G J J 0 F F G G H H J J K 0 K IR K O K G G J J SNV0TZQL FPG_R_[0:],.V.V.V FPG_R_[0:], GMII_RS GMII_OL GMII_RX_V GMII_RX_R GINT# G_MLK GMII_RX_LK GMII_TX_LK GMII_RX0 GMII_RX GMII_RX GMII_RX GMII_RX GMII_RX GMII_RX GMII_RX 0 0.uF.V 0 0.uF GMII_TX0 GMII_TX GMII_TX GMII_TX GMII_TX GMII_TX GMII_TX GMII_TX GMII_TX_N GMII_TX_R GMII_GTX_LK G_RST# 0 0.uF 0 0.uF XS00FG_ vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - FPG ank Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

7 .V XP VOLTG SLT XP VOLTG SLT 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0 0.0uF 0.0uF 0.0uF.0uF.0uF.0uF.0uF.uF.uF 0uF.V Vcco_0.V efault: JP : (VO_0 =.V).V Vcco_.V efault: JP : (VO_ =.V) ap Size 00 ap Size 00 ap Size 00 ap Size TN.V JP JP 0.0uF 0.0uF 0.0uF 0 0.0uF 0.0uF.0uF.0uF.0uF.uF.uF 0uF JTG_TK JTG_TMS FPG_TO FPG_TI JTG_TK JTG_TMS JTG_TO JTG_TI.V V_INT.V FPG_PROG# 0.V R L_LU SW SPST 0.uF.V R.0K JP default setting : Q N00 R.K 0 FPG_ON efault: JP Unpopulated JP R 0K JP SUSPN.V R.K JTG_TK JTG_TMS FPG_TO FPG_TI G V0 W W W W V U0 U U T T T T T T T R R R P P P P N N N M M M L L L U TK TMS TO TI PR0G_ SUSPN ON U T T T R R R P P P P N N N N M M M M L L L K V U T P N0 L K J VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX XS00FG_ VO_0 VO_0 VO_0 VO_0 VO_0 VO_0 VO_0 VO_0 VO_0 VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ H H W T T N L L H W W W T T P L L H Vcco_0.V Vcco_.V L L L L K0 K J H H H H F F F F F F F F F F F F V_INT 0.0uF 0 0.0uF 0.0uF 0.0uF 0.0uF 0 0.0uF 0.0uF 0.0uF 0 0.0uF 0.0uF 0.0uF 0 0.0uF 0 0.0uF.0uF.0uF 0.0uF.0uF.0uF.0uF.0uF.uF.uF.uF.uF 0uF Vcco_0 0.0uF 0.0uF 0 0.0uF 0.0uF 0 0.0uF.0uF 0.0uF.0uF.uF.uF 0uF ap Size 00 ap Size 00 ap Size 00 ap Size TN Vcco_ 0 0.0uF 0.0uF 0.0uF 0.0uF 0 0.0uF.0uF.0uF.0uF.uF.uF 0 0uF.V 0.0uF 0.0uF 0 0.0uF 0.0uF 0 0.0uF.0uF.0uF.0uF.uF.uF 0uF vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - FPG Power Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

8 .V.V.uF 0.uF 0.uF 0.uF 0 0.uF 0.uF 0.uF 0.uF 0.uF.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0 0.uF 0.uF 0.uF 0.uF 0 0.uF 0.uF 0.uF 0.0uF 0.0uF 0.0uF 0.0uF 0.uF 0.uF 0.uF 0.uF 0 0.uF 0.0uF 0.0uF 0.0uF FPG_R_VRF.V R NP FPG_R_VRF 0.0uF R_OT_ontrol 0.0uF FPG_R_VRF.V FPG_R_VRF.V, FPG_R_[0:], FPG_R_S0, FPG_R_S FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ U M 0 M M N N N N P P P M 0 P R L 0 L V V V M V J V R VQ VQ VQ VQ VQ VQ VQ G VQ G VQ G VQ G MTHMN FPG_MM_0 FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_0 FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_0 FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_0 FPG_MM_ G G H H H H F F Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q MTHMN V R V J V M V V U FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_[0:], FPG_R_S0, FPG_R_S,, FPG_R_RS#, FPG_R_S# FPG_R_RS#, FPG_R_S#,, FPG_R_W#, FPG_R_S# UQS UQS#/NU FPG_R_W#, FPG_R_S#, FPG_R_LK_0 FPG_R_LK_0# R 00 FPG_R_K F FPG_R_K FPG_R_LK_ FPG_R_LK_# H H F F P N J VL J VQ G VQ G VQ G VQ G VQ VQ VQ VQ VQ VQ L L F LM UM RS# S# K L LQS LQS#/NU R R R L RFU RFU RFU RFU OT K W# S# K L L K K# K J K K J VRF J VRF J VL J M M M N N N N P P P M P R UQS UQS#/NU F J N P RFU RFU RFU RFU F F H H Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q G G H H H H F F K L RS# S# LM UM F LQS LQS#/NU L R R R OT K K L W# S# J K K K K# K L J R 00, FPG_R_LQS#_0, FPG_R_LQS_0, FPG_R_LQS#_, FPG_R_LQS_, FPG_R_UM_0, FPG_R_LM_0, FPG_R_LM_, FPG_R_UM_, FPG_R_UQS_, FPG_R_UQS#_, FPG_R_UQS_0, FPG_R_UQS#_0 Place series terminations close to FPG, FPG_R_[0:] FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ RP R0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 RP0 R0 FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_0 FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ RP R0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ RP R0 FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_0 RP R0 FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_0 FPG_R_ RP R0 FPG_MM_ FPG_MM_ FPG_MM_0 FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_ RP R0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 RP R0 FPG_MM_ FPG_MM_ FPG_MM_ FPG_MM_0 vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - R Memory Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

9 FPG_0.V_TT RP 0 RP0 0 RP 0 RP 0 FPG_0.V_TT 0.0uF 0.0uF 0 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.uF 0.uF NP, FPG_R_[0:] FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_, FPG_R_S#, FPG_R_RS# FPG_0.V_TT NP RP 0, FPG_R_S#, FPG_R_W#, FPG_R_S0, FPG_R_S FPG_0.V_TT FPG_0.V_TT RP 0 RP 0 RP 0 RP 0 RP0 0 RP 0 RP 0 RP 0 RP 0 RP 0 RP 0 Layout Note: Install terminators as close as possible to the FPG (U), FPG_R_[0:] FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_0 FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_ FPG_R_, FPG_R_UQS_0, FPG_R_UQS#_0, FPG_R_UQS_, FPG_R_UQS#_, FPG_R_LM_0, FPG_R_UM_0, FPG_R_LM_, FPG_R_UM_, FPG_R_LQS_0, FPG_R_LQS#_0, FPG_R_LQS_, FPG_R_LQS#_ vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - R Termination Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

10 .V FLSH_# FLSH_O# FLSH_W# FLSH_[0:] Flash_Reset# R 0K.V JP FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_0 FLSH_ FLSH_ FLSH_.V U 0# #/RFU #/RFU O# W# YT#/RFU VPN RP# FJ TSSOP- V V VQ STS Q0 Q Q Q 0 Q Q Q Q Q Q Q0 Q Q Q Q 0 Q RFU 0.uF.V R K 0.uF.V U V IR 0 SNVTPW FLSH_W# FLSH_[0:] V V 0 O Vcco_ FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_# JTG_TK JTG_TMS FPG_TO FPG_TI JTG_TK JTG_TMS JTG_TO JTG_TI SPI_SL# SPI_LK SPI_MOSI SPI_MISO JP R 0K.V efault: JP No Jumper U S# V Q Hold# W# 0 QHF0S.V 0.uF R R JTG_TMS efault: JP :.V J R R R R R R JTG_TI JTG_TO JTG_TK.V 0 Layout Note: Place J and J close together 0.uF 0.uF 0uF JTG Parallel IV onnector.v.v J N N TI 0 TO TK TMS VRF -0 R R R R R R R R JTG_TI JTG_TO JTG_TK JTG_TMS SM_LK FPG_INIT# SM_Wn SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_ SM_n SM_RY FLSH_0 JTG_TK.V.V J.V.V TO LOK TMS TI TK PROGRMn INITn On Wn V.V IRQ n RSTn RY ON ITSTRM LK SM Header.V.V R R JTG_TO JTG_TMS JTG_TI FPG_PROG# SM_On SM_0 SM_ SM_0 SM_ SM_ SM_ SM_ SM_0 SM_ SM_ SM_ SM_ SM_IRQ SM_RSTn FPG_ON FPG_LK 0.uF 0.uF.V RP.K JTG_TMS JTG_TK JTG_TI UT PIN 0 vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet 0 - onfiguration/flash Memory Size ocument Number Rev 0 ate: Friday, July, 00 Sheet 0

11 GMII_TX0 R GMII_TX R GMII_TX R GMII_TX R GMII_TX R GMII_TX GMII_TX R R GMII_TX R GMII_TX_N GMII_TX_R R R0.V.V.V.V GMII_GTX_LK GMII_TX_LK GMII_RX0 GMII_RX GMII_RX GMII_RX GMII_RX GMII_RX GMII_RX GMII_RX GMII_RX_V GMII_RX_R GMII_RX_LK GMII_RS GMII_OL GMII_M GMII_MIO GINT#.V.V R0 K R K Place close to FPG Place close to PHY Place close to PHY R 00K NP R R R0 R R R R R R R R0 R R R R U TX0/TX0 TX/TX TX/TX TX/TX TX TX TX TX TX_N/TXN_R TX_LK/RGMII_SL GTX_LK/TK TX_R RX0/RX0 RX/RX RX/RX RX/RX RX RX RX RX RX_V/RK RX_RRXV_R RX_LK OL/LK_M_FRQ RS/RGMII_SL0 M MIO INTRRUPT LK_IN LK_OUT LK_TO_M RST MIX_N MN_MIX/TX_TLK MULTI_N/TX_TRIG NON_I M_LK_N/TX_SYN_LK PVH MI_N 0 MI_P 0 MI_N MI_P MI_N MI_P 0 MI_N MI_P PHY_R PHY_R PHY_R PHY_R L_UP/PHY_R0 L_T/SP0 L_LNK_0/SP L_LNK_00/UPLX L_LNK_000/N_N 0 TK TMS TI TO TRST R K R. % R. % R. % RP.K R. % R. % R. % LNK0 LNK00 LNK000.V.V.V Speed0 G_MLK.V R Place close to PHY G_RST# R. % R. % U VG0 U R 0 VG0 J T SHIL V_T MX0_N MX0_P MX_N MX_P MX_N MX_P MX_N MX_P 0 H_ SHIL -0- LINK U VG0 JT om.v R K JT om NP R R K R0 0M Y XTL-MHz pf pf JT om JT0 om JT om LNK000 L_GRN R K LNK00 L_GRN R K LNK0 L_GRN R K R 0 R 0 R 0.V.V.V JT om JT om JT om uto-neg uplex Speed.V JT om K JT om K NON-I MN-MIX.V JT om K JT om K JT om K M LK-N MULTI-N MIX-N JT om UPLX L_GRN R K R 0.V JT om PHY R0 efault position is - for all JTx jumpers vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - 0/00/000 PHY Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

12 .V uf 0.0uF 0.0uF.V uf 0.0uF 0.0uF 0.0uF U.V.V R R uf 0.0uF V_V V_V V_V V_V V_V V_V V_V OR_V OR_V OR_V OR_V OR_V OR_V OR_V OR_V 0.0uF 0 0.uF 0.0uF 0.uF 0.0uF 0 0.uF 0.0uF 0.uF 0.0uF uf.v 0.0uF 0.uF 0.0uF 0.uF 0.0uF.V 0.uF R 0 0.0uF uf 0 0.uF R.K % V_V V_V V_SL IO_V IO_V IO_V IO_V IO_V IO_V IO_V IO_V IO_V IO_V IO_V IO_V G_RF RSV RSV RSV PVH vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - PHY Power Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

13 _[0:] _G[0:] _R[0:] _0 G0 _G _G _G _R0 _R _R _R R.0K R K R K R 0 R0.0K R K R K R 0 R.0K R K R K R 0 LU GRN R _VSYN _HSYN R R R 0 P ONNTOR NP R R0 R R0 R0 R0 vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - Out Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

14 XP_S_IO_[0:].V JX.V XP_IFF_LK_IN_p XP_IFF_LK_IN_n XP_IFF_LK_OUT_p XP_IFF_LK_OUT_n XP_IFF_p0 XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p0 XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p0 XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_IFF_n0 XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n0 XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_IFF_n XP_S_IO_ XP_S_IO_ XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_S_LK_IN XP_S_LK_OUT.V 0.uF 0.uF.V 0.uF 0.uF 0.uF 0 0.uF 0.uF 00 0.uF 0uF 0uF.V 0 0.V QT-00 XP_IFF_p[0:] XP_IFF_n[0:] vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - XP onnector (JX) Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

15 , XP_S_IO_[0:].V JX.V XP_IFF_LK_IN_p XP_IFF_LK_IN_n XP_IFF_LK_OUT_p XP_IFF_LK_OUT_n XP_IFF_p0 XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p0 XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p0 XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_0 XP_S_IO_ XP_IFF_n0 XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n0 XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_S_IO_ XP_IFF_n XP_S_IO_ XP_S_IO_ XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_n XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_IFF_p XP_S_LK_IN XP_S_LK_OUT.V 0.uF.V 0.uF 0.uF 0.uF 0 0.uF 0.uF 0.uF 0.uF 0uF 0uF.V 0 0.V QT-00 XP_IFF_p[0:] XP_IFF_n[0:] vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - XP onnextor (JX) Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

16 V POWR (V) INPUT J V arrel Socket R SMT- NP 0uF Main Power Switch NP R K SW PWR_ON PTH_INH# R 0 PWR_OFF SPT Slide HG V 0 00uF U0 PTH_Track PTH_INH# V RST WI MR TPS U Vin Track INH PTH_Track PTH_INH# PTH000WZ Vout J R uf F Fair-Rite 0 murata GRMRK0 uf HG.V VX TPSK000 JP0.V JP0 efault jumper :, : R.V Vsense = (.K/0K)0.0 Vsense =.V V_INT R00.K R0 0K SW GLOL RST 0.uF V R 0K U SNS V MR RST T TPS0 Power-On Reset.V.V U.V Sns V Sns MR Sns RST RST R0 0K.V 0.uF R.V R 0K PO_RST# HG0.V V R K R K TPS0- RST HG HG HG HG V 00uF PTH_Track PTH_INH# U PTH0000WZ Vin Track INH Vout J R.K uf F Fair-Rite 0 murata GRMRK0 uf VX TPSK000 JP V_INT JP efault jumper :, : R R.V Q MMTLT HG.V HG HG HG HG V 00uF PTH_Track PTH_INH# U Vin Track INH PTH000WZ Vout J R.K uf murata GRMRK0 F Fair-Rite 0 00uF VX TPS0K000 JP.V JP efault jumper :, : R 0.V HG HG HG HG V 0uF 0uF FPG_0.V_TT FPG_R_VRF 0 0uF 0uF 0 0.0uF 0uF U VLOIN VST 0 VTT RVH VTT LL VTTSNS RVL P MO S VTTRF VIN OMP PGOO VQSNS S 0 VQST S TPSPWP PTH_Track 0.uF R0.K V.uF Q STSNF0L L.uH Q STSNF0L 0uF HG.V JP.V JP efault jumper :, : R 00K PGOO vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - oard Power Size ocument Number Rev 0 ate: Friday, July, 00 Sheet

17 RV RV POWR LS TO V_INT,.V N.V RILS ONNT U0. TO PTH_INH# NT PKG LO RSISTOR TO V RIL T PWR JK PRLLL TRMINTION TO SM LOK INPUT RMOV LVL SHIFTR U & IRTLY ONNT SPI NTS TO U GROUN UNUS I/O PINS ON TRNSIVRS U, U & U HNG NM OF PIN "V" ON FPG SYMOL FROM "IP" TO "IO" 0//0: Updated ank FPG package by adding pin (IP_) and changing pin from IP_ (input only) to IO_ (bidirectional) //0: hanged U device type from FJ/P0 G to FJ TSSOP- 0//0: orrected typo on pin U FPG (U) vnet, Inc. ngineering Services opyright 00 Spartan- SP Starter oard Sheet - Revision History Size ocument Number Rev 0 ate: Friday, July, 00 Sheet