DB46 Top Level U_PSU PSU.SCHDOC. U_DB_Common DB_Common. U_Bypass_Board DB_Bypass. U_DB46_Hardware_Kit DB46_Hardware_Kit.SchDoc.

Transcription

1 U ommon _ommon U_PSU PSU.SHO U_ypass_oard _ypass U_6_Hardware_Kit 6_Hardware_Kit.Schoc Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: 6_Top.Schoc 6 Top Level ltium Limited L, Rodborough Road NSW 086 ustralia

2 TP0 U_PSU_MX8_V_LT PSU_MX8_V_LT V PWRNET PWRNET i i V V0 TP TP V V0 U_PSU_MX8860_J PSU_MX8860_J VIN nfult VSET VOUT V V V PWRNET PWRNET PWRNET i i i V NT7 TP V0 TP V RT 00K % nalog power for the FPG VUX is set to a nominal.v by the 00K feedback resistor. Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: PSU.SHO Power Supply Top Level ltium Limited L, Rodborough Road NSW 086 ustralia

3 V0 _PS 0uF 0V _PS.uF 0V 6_PS uf 0V R_PS 0R % Vfilt _PS 70pF 0V OMP 6 U_PS MX8EEE IN IN V SHN OMP LX LX LX LX F P P 6 8 LX L_PS u,, R, SM F R_PS K7 % R_PS 7K % R_PS K7 % 9 8_PS R_PS TOFF 7 0uF 0V TOFF 00K % FSEL 7_PS 0 REF_V uf V REF _PS uf 0V V _PS 0uF 0V Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: File: 7//008 Time: ::0 PM Sheet of PSU_MX8_V_LT.Schoc Power Supply MX8 (V) ltium Limited L, Rodborough Road NSW 086 ustralia

4 VIN _L.uF 0V _L 0.0uF 0V U MX8860EU8+ IN OUT 7 6 nshn OUT nfult SET 8 R_L 00K % nfult VSET R_L 00K % Higher level has resistor (R) between VSET and VOUT. _L.uF 0V VOUT The voltage provided by the MX8860 linear regulator is determined by the addition of a resistor between VOUT and VSET. This additional resistor (R) is located on the higher-level schematic. The voltage produced by the MX8860 is calculated as follows: VOUT =. * ( + R / 00k) If R = 0k, If R = 00k, If R = 6k, VOUT =. * ( + 0k/00k) =.0 Volts VOUT =. * ( + 00k/00k) =.0 Volts VOUT =. * ( + 6k/00k) =.0 Volts Note that if VSET is grounded (on the higher-level schematic), VOUT=.8 Volts Note also that VIN must be a minimum of 0.8 Volts above VOUT. Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: PSU_MX8860_J.Schoc Power Supply MX8860 (V) ltium Limited L, Rodborough Road NSW 086 ustralia

5 _M 0uF 0V _M 0uF 0V These decoupling capacitors are intended to assist the voltage rails on the P - where the decoupling capacitors for the FPG are not close. Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: _ypass.schoc oard ypass apacitors ltium Limited L, Rodborough Road NSW 086 ustralia

6 Top Level Schematic For aughter oard esign oth FPG-Only and FPG + MU This evice Sheet is the same for all designs. It relies on being instantiated in a project that contains a device-specific sheet named EVIES.Schoc. U_Memory_ommonus_aughteroard N_ommonMemory U_EVIES EVIES.Schoc U_Motheroardonnectors _Motheroardonnectors MEM US U_RESET_SW SLEEP_N SW U_RESET_SW SLEEP_N SW UZZER UZZER U_ommonMemory_Termination N_ommonMemory_Termination MEM N IP USER_LE USERIO N IP USER_LE USERIO JTG JTG I I U_SRM_K6R06V-T0T_6Kx6 SRM_6Kx6_TSOP KEYOR MOUSE KEYOR MOUSE SRM SRM RS RS SPI SPI U_SRM_K6R06V-T0T_6Kx6 SRM_6Kx6_TSOP LOKS PROGRM LOKS PROGRM SRM SRM TFT TFT EXT_ EXT_ EXT_ EXT_ EXT_ EXT_ U_aughteroard_LES _LES STTUS_LE STTUS_LE STTUS_LE ONE_WIRE P ONE_WIRE_I ONE_WIRE_PIO ONE_WIRE P ONE_WIRE_I ONE_WIRE_PIO Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet 6 of File: _ommon.schoc aughter oard Top Level ltium Limited L, Rodborough Road NSW 086 ustralia

7 U_FPG FPG.SHO US SRM SRM MEM_OMMON SRM SRM U_RESET_SW SLEEP_N SW UZZER N U_RESET_SW SLEEP_N SW UZZER N IP USER_LE IP USER_LE USERIO USERIO STTUS_LE STTUS_LE I KEYOR MOUSE I KEYOR MOUSE RS TFT RS TFT EXT_ EXT_ EXT_ EXT_ EXT_ EXT_ ONE_WIRE P ONE_WIRE_I ONE_WIRE_PIO ONE_WIRE P ONE_WIRE_I ONE_WIRE_PIO SPI LOKS PROGRM JTG SPI LOKS PROGRM JTG evice Specific Section of aughter oard esign This schematic sheet (plus any child sheets) will contain the device specific parts of any daughter board designs. This will include any FPG or MU devices as well as dedicated power supplies, connectors etc. Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet 7 of File: EVIES.Schoc FPG, LEs and SRM Memory ltium Limited L, Rodborough Road NSW 086 ustralia

8 //008 ::0 PM FPG.SHO Project Title Size: ate: File: Revision: Sheet of Time: FPG onnections ssy: 6 - Virtex SX ltium Limited L, Rodborough Road NSW 086 ustralia FPG_TK FPG_TI FPG_TMS FPG_TO FPG_PROGRM FPG_M0 FPG_M FPG_M FPG_LK FPG_ONE FPG_PROGRM FPG_TO FPG_INIT FPG_PROG_PWR_ON FPG_ONE FPG_I FPG_I0 FPG_I FPG_I STTUS_LE FPG_I = 0x0 (Xilinx) TMS ONE M LK M0 M TK HSWP_EN TI PROG_ TO IN INIT U_FPG_Power FPG_NonIO.Schoc U_ypass_ ypass_fpg_.schoc U_ypass_V ypass_fpg_v.sho U_ypass_V ypass_fpg_v.sho FPG_ONE R K7 % R K7 % R K7 % R K7 % R7 00R % R8 00R % R9 00R % R0 00R % R 00R % R 00R % R8 00R % R 00R % R 00R % R 00R % R0 00R % VRN_7 VRP_7 NT NT NT NT NT6 FPG_LK IO FPG_LK EXTEN_ US_9 US_SRM_KE US_SRM_NS US_SRM_NRS EXTEN_9 EXTEN_ EXTEN_ EXTEN_ US_SRM_NS ONE_WIRE P EXTEN_ U_TFT_LUE U_TFT_LUE EXTEN_ REF_LK US_FLSH_NS SL U_TFT_IRQ U_TFT_POL U_TFT_MUX U_TFT_M U_TFT_ISP_ON U_TFT_LIGHT SRM_0 SRM_9 SRM_8 SRM_8 SRM_ SRM_ SRM_ SRM_ EXTEN_6 EXTEN_7 IO8 IO9 SRM_ SRM_ EXTEN_8 EXTEN_9 IP LE LE LE LE6 LE7 IP IP SRM_NLE SRM_NOE SRM_7 SRM_ SRM_NS SRM_ SRM_ EXTEN_0 EXTEN_ LE0 LE LE IP0 IP SRM_NHE SRM_6 SRM_ SRM_0 FPG_INIT IO0 IO IO8 SW IO IO IO9 IO0 RS_RTS EXTEN_0 EXTEN_ EXTEN_ EXTEN_ EXTEN_0 EXTEN_ EXTEN_ US_6 US_7 EXTEN_ EXTEN_ EXTEN_ US_ US_ EXTEN_ EXTEN_6 US_9 US_8 US_8 US_7 US_0 US_ EXTEN_6 EXTEN_ EXTEN_8 EXTEN_7 US_ US_ EXTEN_8 EXTEN_7 EXTEN_0 US_0 US_NWE EXTEN_0 EXTEN_9 US_FLSH_NUSY US_8 EXTEN_ EXTEN_ EXTEN_ US_ US_ US_ EXTEN_ US_ EXTEN_ EXTEN_ EXTEN_ EXTEN_6 EXTEN_7 EXTEN_8 EXTEN_7 EXTEN_0 EXTEN_9 U_TFT_GREEN SRM_9 SRM_0 EXTEN_8 EXTEN_9 EXTEN_ U_TFT_GREEN SRM_8 SRM_7 SRM_ SRM_ EXTEN_0 EXTEN_ EXTEN_ U_TFT_GREEN0 NEXUS_TK SRM_6 NEXUS_TMS SRM_ EXTEN_ EXTEN_9 EXTEN_ EXTEN_ EXTEN_6 NEXUS_TI SRM_ SRM_NWE EXTEN_ EXTEN_0 EXTEN_6 EXTEN_7 SRM_0 SRM_7 EXTEN_ EXTEN_ EXTEN_7 EXTEN_8 EXTEN_8 U_TFT_LUE SRM_ SRM_ SRM_6 EXTEN_ EXTEN_ EXTEN_9 U_TFT_RE0 U_TFT_RE U_TFT_RE U_TFT_RE SRM_ SRM_ SRM_ US_ EXTEN_8 EXTEN_6 EXTEN_ N_RX RS_TX RS_RX KLOK MOUSELOK US_NOE US_ US_6 US_ US_ SRM_ EXTEN_ EXTEN_ EXTEN_ IO6 IO7 IO IO IO IO SRM_NLE SRM_ SRM_NOE SRM_NHE SRM_ SRM_6 SRM_7 EXTEN_ US_NE EXTEN_9 EXTEN_ EXTEN_0 N_TX US_SRM_FEEK RS_TS KT MOUSET US_ US_ EXTEN_ NEXUS_TO EXTEN_ US_0 US_ US_6 US_ US_ US_ US_7 US_SRM_LK EXTEN_6 EXTEN_ EXTEN_9 EXTEN_7 EXTEN_0 EXTEN_8 EXTEN_8 EXTEN_ EXTEN_7 EXTEN_9 EXTEN_ EXTEN_6 SRM_ EXTEN_6 EXTEN_ EXTEN_ EXTEN_ SRM_ SRM_ EXTEN_0 EXTEN_ SRM_0 EXTEN_ SRM_9 EXTEN_ SRM_8 SRM_7 EXTEN_7 SRM_6 SRM_8 SRM_ EXTEN_8 SRM_ SRM_9 SRM_8 EXTEN_9 IO SRM_NWE SRM_ SRM_0 EXTEN_0 SRM_ SRM_ SRM_NS SRM_0 SRM_ SRM_ IO IO IO IO IO IO7 IO IO IO IO6 IP IO IO SRM_ SRM_ US_6 US_ EXTEN_6 S IO IO6 IO7 IO8 IO9 IP6 U_RESET_SW SRM_ IO0 IO0 IP7 EXTEN_ EXTEN_ EXTEN_ US_8 US_9 US_0 US_ US_ US_ US_7 US_ US_0 US_ US_9 US_FLSH_NRESET EXTEN_ EXTEN_ EXTEN_8 EXTEN_6 EXTEN_ EXTEN_ EXTEN_9 EXTEN_6 EXTEN_ EXTEN_ EXTEN_9 EXTEN_7 EXTEN_6 EXTEN_7 EXTEN_ EXTEN_9 EXTEN_7 EXTEN_ EXTEN_ EXTEN_ EXTEN_0 EXTEN_8 EXTEN_7 EXTEN_ EXTEN_ EXTEN_ EXTEN_0 EXTEN_8 EXTEN_ EXTEN_ EXTEN_6 EXTEN_7 U_TFT_L EXTEN_8 U_TFT_STH EXTEN_9 U_TFT_STV EXTEN_0 U_TFT_GREEN EXTEN_ U_TFT_GREEN EXTEN_ EXTEN_ EXTEN_ EXTEN_ U_TFT_GREEN U_TFT_L U_TFT_L SPI_IN US_NE SPI_LK UNUSE US_NE0 SPI_SEL SPI_MOE US_NE US_ US_0 US_6 US_ US_SRM_NS SPI_OUT US_9 US_ US_8 US_7 US_ US_ SRM_6 SRM_7 SRM_ SRM_ SRM_ SRM_ SRM_ SRM_0 UNUSE SW0 U_TFT_LUE UZZER SW SW SW U_TFT_RE U_TFT_LUE0 UNUSE UNUSE UNUSE6 UNUSE FPG_IN SRM_NS SRM_[8..0] SRM_[..0] SRM_NHE SRM_NWE SRM_NOE UZZER UZZER N_RX N_TX IP[7..0] SL S SPI_LK SPI_IN SPI_OUT SPI_MOE SPI_SEL IO[..0] FPG_LK REF_LK FPG_LK FPG_IN FPG_ONE FPG_I[..0] FPG_INIT FPG_M[..0] FPG_PROG_LK FPG_PROG_PWR_ON FPG_PROGRM FPG_TK FPG_TI FPG_TO FPG_TMS FPG_LK ONE_WIRE_I ONE_WIRE_I SW[..0] ONE_WIRE P ONE_WIRE P SRM_NS SRM_[8..0] SRM_[..0] SRM_NHE SRM_NWE SRM_NOE SRM_NLE SRM_NLE US_SRM_LK US_SRM_FEEK NT8 ONE_WIRE_PIO ONE_WIRE_PIO ONE_WIRE U_W_S06_EPROM W_S06_EPROM I PIO PIO ONE_WIRE [8..0] [..0] NS NWE NOE NHE NLE SRM [8..0] [..0] NS NWE NOE NHE NLE SRM US_[..] US_[..0] US_NOE US_NWE US_NE[..0] US_SRM_NS US_FLSH_NS US_SRM_NS US_SRM_KE US_SRM_LK US_SRM_NS US_SRM_NRS US_FLSH_NRESET US_FLSH_NUSY US_[..] US_[..0] US_NE[..0] US_NWE US_NOE US_FLSH_NS US_FLSH_NRESET US_FLSH_NUSY US_SRM_NS US_SRM_KE US_SRM_LK US_SRM_NS US_SRM_NRS US_SRM_NS HOST MEMORY RESOURES MEM_OMMON UGHTER OR MEMORY RESOURES REF_LK FPG_LK FPG_LK MOE SEL LK IN OUT IN ONE INSTLLE I[..0] LK PROGRM M[..0] INIT PROG_PWR_ON PROG_LK TMS TO TI TK TMS TO TI TK HR SOFT UGHTER OR I/O JTG PROGRM SPI US LOKS JTG PROGRM SPI LOKS NEXUS_TK NEXUS_TI NEXUS_TO NEXUS_TMS U_RESET_SW HOST PERIPHERLS Host Reset Status LEs L[7..0] USER_LE SW [..0] RE[..0] GREEN[..0] LUE[..0] M POL L[..] STV STH ISP_ON LIGHT IRQ MUX U_TFT_MUX U_TFT_RE[..0] U_TFT_GREEN[..0] U_TFT_LUE[..0] U_TFT_M U_TFT_POL U_TFT_L[..] U_TFT_STV U_TFT_STH U_TFT_ISP_ON U_TFT_LIGHT U_TFT_IRQ TFT TFT L ISPLY INTERFE T LOK KLOK KT MOUSELOK MOUSET RS_TS RS_RTS RS_RX RS_TX RS KEYOR MOUSE RX TX RTS TS T LOK LE[7..0] U_RESET_SW IP USERIO IO[..0] [7..0] TX RX N SL S I EXT_ EXT_ EXT_ EXTEN_[9..0] EXTEN_[9..0] EXTEN_[9..0] [9..0] [9..0] [9..0] ONE-WIRE ONNETIONS SLEEP_N Shared ypass aps _M 0uF 0V _M 0uF 0V NK IO_LP L_ F IO_LN_0_L_ F IO_LP_9_L_ F IO_LN_8_L_ F IO_LP_7_L_ F6 IO_LN_6_L_ F IO_LP L_ IO_LN VREF_L_ IO_LP L_ IO_LN L_ E IO_L6P L_ IO_L6N_0_L_ IO_L7P_9_L_ 6 IO_L7N_8_L_ 6 IO_L8P_7 L_ E IO_L8N_6 L_ U XVSX-0FFG668 NK IO_LP L_ IO_LN L_ IO_LP L_ IO_LN L_ IO_LP L_ 6 IO_LN_0_L_ IO_LP_9_L_ IO_LN_8_VREF_L_ IO_LP_7_L_ IO_LN_6_L_ IO_L6P L_ IO_L6N L_ IO_L7P L_ 6 IO_L7N L_ IO_L8P L_ IO_L8N_0_L_ U XVSX-0FFG668 NK IO_LP_G L_ IO_LN_G L_ IO_LP_G_VRN_L_ IO_LN_G_VRP_L_ IO_LP_G_L_ IO_LN_G_L_ IO_LP_G_L_ IO_LN_G_VREF_L_ IO_LP_G_L_ 6 IO_LN_G_L_ IO_L6P_G_L_ 0 IO_L6N_G_L_ 0 IO_L7P_G_L_ 7 IO_L7N_G_L_ 7 IO_L8P_G_L_ IO_L8N_G_L_ U XVSX-0FFG668 NK IO_LP_G_L_ F IO_LN_G_L_ E IO_LP_G_L_ 0 IO_LN_G_L_ 0 IO_LP_G_L_ 7 IO_LN_G_L_ 7 IO_LP_G_L_ F IO_LN_G_VREF_L_ F0 IO_LP_G_L_ E IO_LN_G_L_ E IO_L6P_G_L_ E0 IO_L6N_G_L_ 0 IO_L7P_G_VRN_L_ 7 IO_L7N_G_VRP_L_ 6 IO_L8P_G L_ IO_L8N_G L_ U XVSX-0FFG668 NK IO_LP_ 7 IO_LN_ 7 IO_LP_ 0 IO_LN_ 0 IO_LP_ 8 IO_LN_ 8 IO_LP_ 0 IO_LN_VREF_ 9 IO_LP_ E7 IO_LN_ F7 IO_L6P_ IO_L6N_ IO_L7P_ 9 IO_L7N_ 8 IO_L8P L_ IO_L8N L_ IO_L7P_ G9 IO_L7N_ F9 IO_L8P_ E IO_L8N_ E IO_L9P_ F0 IO_L9N_ E0 IO_L0P_ 6 IO_L0N_VREF_ IO_LP_ IO_LN_ IO_LP_ H0 IO_LN_ G0 IO_LP_VRN_ G IO_LN_VRP_ G IO_LP L_ F IO_LN L_ F IO_L9P L_ G8 IO_L9N L_ G7 IO_L0P_ IO_L0N_ IO_LP_ F8 IO_LN_ E8 IO_LP_ E IO_LN_VREF_ IO_LP_ 0 IO_LN_ 9 IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_L6P_ IO_L6N_ IO_LP L_ 6 IO_LN L_ IO_L6P_ H IO_L6N_ H IO_L7P_ E IO_L7N_ E IO_L8P_ G IO_L8N_VREF_ G IO_L9P_ F6 IO_L9N_ E6 IO_L0P_ H IO_L0N_ H IO_LP_ G6 IO_LN_ G IO_LP_ H6 IO_LN_ H UE XVSX-0FFG668 NK 6 IO_LP_6 0 IO_LN_6 0 IO_LP_6 9 IO_LN_6 8 IO_LP_6 8 IO_LN_6 7 IO_LP_6 8 IO_LN_VREF_6 7 IO_LP_6 F0 IO_LN_6 E0 IO_L6P_6 6 IO_L6N_6 IO_L7P_6 E9 IO_L7N_6 F9 IO_L8P L_6 6 IO_L8N L_6 6 IO_L7P_6 E7 IO_L7N_6 6 IO_L8P_6 E6 IO_L8N_6 E IO_L9P_6 F7 IO_L9N_6 G7 IO_L0P_6 IO_L0N_VREF_6 IO_LP_6 H8 IO_LN_6 H7 IO_LP_6 IO_LN_6 E IO_LP_VRN_6 G6 IO_LN_VRP_6 G IO_LP L_6 E IO_LN L_6 E IO_L9P L_6 G0 IO_L9N L_6 G9 IO_L0P_6 F8 IO_L0N_6 G8 IO_LP_6 7 IO_LN_6 7 IO_LP_6 IO_LN_VREF_6 IO_LP_6 9 IO_LN_6 9 IO_LP_6 IO_LN_6 IO_LP_6 IO_LN_6 IO_L6P_6 IO_L6N_6 IO_LP L_6 IO_LN L_6 IO_L6P_6 E IO_L6N_6 F IO_L7P_6 F IO_L7N_6 F IO_L8P_6 G IO_L8N_VREF_6 G IO_L9P_6 H6 IO_L9N_6 H IO_L0P_6 G IO_L0N_6 G IO_LP_6 H IO_LN_6 H IO_LP_6 H IO_LN_6 H UF XVSX-0FFG668 NK 7 IO_LP SM7_L_7 9 IO_LN SM7_L_7 9 IO_L6P_SM6_7 9 IO_L6N_SM6_7 0 IO_L7P_SM_7 Y7 IO_L7N_SM_7 7 IO_L8P_7 0 IO_L8N_VREF_7 0 IO_L9P_SM_7 8 IO_L9N_SM_7 8 IO_L0P_SM_7 F IO_L0N_SM_7 F IO_LP_SM_7 F8 IO_LN_SM_7 E8 IO_LP_SM_7 E IO_LN_SM_7 IO_L7P_7 F9 IO_L7N_7 F0 IO_L8P_7 Y9 IO_L8N_7 W9 IO_L9P_7 F IO_L9N_7 E IO_L0P_7 Y0 IO_L0N_VREF_7 Y IO_LP_7 8 IO_LN_7 Y8 IO_LP_7 F IO_LN_7 E IO_LP_VRN_7 E0 IO_LN_VRP_7 0 IO_LP L_7 IO_LN L_7 IO_LP_7 V IO_LN_7 V IO_LP_7 W IO_LN_7 W6 IO_LP_7 W IO_LN_7 W IO_LP_7 W IO_LN_VREF_7 W IO_LP_7 W0 IO_LN_7 V0 IO_L6P_7 Y IO_L6N_7 Y6 IO_L7P_7 IO_L7N_7 IO_L8P L_7 IO_L8N L_7 Y IO_L9P L_7 IO_L9N L_7 6 IO_L0P_7 6 IO_L0N_7 6 IO_LP_7 IO_LN_7 6 IO_LP_7 Y IO_LN_VREF_7 Y IO_LP_7 IO_LN_7 IO_LP_7 IO_LN_7 IO_LP_7 IO_LN_7 IO_L6P_7 IO_L6N_7 UG XVSX-0FFG668 NK 8 IO_LP L_8 F8 IO_LN L_8 F7 IO_L6P_8 8 IO_L6N_8 Y8 IO_L7P_8 Y0 IO_L7N_8 0 IO_L8P_8 7 IO_L8N_VREF_8 7 IO_L9P_8 9 IO_L9N_8 9 IO_L0P_8 E6 IO_L0N_8 6 IO_LP_8 F9 IO_LN_8 E9 IO_LP_8 8 IO_LN_8 8 IO_L7P_8 F IO_L7N_8 E IO_L8P_8 IO_L8N_8 IO_L9P_8 F6 IO_L9N_8 F IO_L0P_8 7 IO_L0N_VREF_8 Y7 IO_LP_8 9 IO_LN_8 Y9 IO_LP_8 IO_LN_8 IO_LP_VRN_8 E7 IO_LN_VRP_8 7 IO_LP L_8 6 IO_LN L_8 6 IO_LP_8 W IO_LN_8 W IO_LP_8 V6 IO_LN_8 V IO_LP_8 W7 IO_LN_8 V7 IO_LP_8 W IO_LN_VREF_8 W IO_LP_8 W6 IO_LN_8 W IO_L6P_8 Y IO_L6N_8 Y IO_L7P_8 IO_L7N_8 IO_L8P L_8 Y IO_L8N L_8 Y IO_L9P L_8 Y6 IO_L9N L_8 Y IO_L0P_8 IO_L0N_8 IO_LP_8 IO_LN_8 IO_LP_8 IO_LN_VREF_8 IO_LP_8 IO_LN_8 IO_LP_8 IO_LN_8 IO_LP_8 F IO_LN_8 E IO_L6P_8 IO_L6N_8 UH XVSX-0FFG668 NK 9 IO_L7P_9 N IO_L7N_9 N0 IO_L8P_9 P IO_L8N_9 P IO_L9P_9 P IO_L9N_9 P IO_L0P_9 R6 IO_L0N_VREF_9 R IO_LP_9 P0 IO_LN_9 P9 IO_LP_9 R IO_LN_9 R IO_LP_VRN_9 R IO_LN_VRP_9 R IO_LP L_9 T IO_LN L_9 T IO_LP_9 J IO_LN_9 J0 IO_LP_9 J IO_LN_9 J IO_LP_9 K IO_LN_9 K IO_LP_9 J6 IO_LN_VREF_9 J IO_LP_9 L9 IO_LN_9 K0 IO_L6P_9 L IO_L6N_9 L0 IO_L7P_9 K IO_L7N_9 K IO_L8P L_9 K6 IO_L8N L_9 K IO_L9P L_9 M9 IO_L9N L_9 N9 IO_L0P_9 L IO_L0N_9 L IO_LP_9 M IO_LN_9 M IO_LP_9 L6 IO_LN_VREF_9 M6 IO_LP_9 M IO_LN_9 M0 IO_LP_9 M IO_LN_9 M IO_LP_9 N IO_LN_9 N IO_L6P_9 N IO_L6N_9 N IO_LP L_9 R0 IO_LN L_9 R9 IO_L6P_9 T6 IO_L6N_9 U6 IO_L7P_9 U IO_L7N_9 V IO_L8P_9 U IO_L8N_VREF_9 U IO_L9P_9 U IO_L9N_9 U IO_L0P_9 T IO_L0N_9 T0 IO_LP_9 U0 IO_LN_9 T9 IO_LP_9 V6 IO_LN_9 V UI XVSX-0FFG668 NK 0 IO_L7P_0 N7 IO_L7N_0 M7 IO_L8P_0 P IO_L8N_0 P IO_L9P_0 P8 IO_L9N_0 N8 IO_L0P_0 R IO_L0N_VREF_0 R IO_LP_0 P7 IO_LN_0 P6 IO_LP_0 R IO_LN_0 R IO_LP_VRN_0 R6 IO_LN_VRP_0 R IO_LP L_0 U IO_LN L_0 T IO_LP_0 J7 IO_LN_0 J6 IO_LP_0 J IO_LN_0 J IO_LP_0 K7 IO_LN_0 K6 IO_LP_0 J IO_LN_VREF_0 J IO_LP_0 L7 IO_LN_0 L6 IO_L6P_0 K IO_L6N_0 K IO_L7P_0 K IO_L7N_0 K IO_L8P L_0 L IO_L8N L_0 L IO_L9P L_0 M8 IO_L9N L_0 L8 IO_L0P_0 L IO_L0N_0 K IO_LP_0 M IO_LN_0 M IO_LP_0 M IO_LN_VREF_0 M IO_LP_0 M6 IO_LN_0 M IO_LP_0 N IO_LN_0 N IO_LP_0 N IO_LN_0 N IO_L6P_0 P IO_L6N_0 P IO_LP L_0 R8 IO_LN L_0 R7 IO_L6P_0 T IO_L6N_0 T IO_L7P_0 T7 IO_L7N_0 T6 IO_L8P_0 U IO_L8N_VREF_0 U IO_L9P_0 V IO_L9N_0 U IO_L0P_0 V IO_L0N_0 V IO_LP_0 T8 IO_LN_0 U7 IO_LP_0 U6 IO_LN_0 U UJ XVSX-0FFG668 To permit I (terminated) inputs, the following must be done on each ank: Tie the VRN pin (in each bank) through 0R to. Tie the VRP pin (in each bank) through 0R to. Pin Nets labeled "UNUSExx" are not used for any function, they are labeled for the purposes of FPG pin swapping only.

9 9 6 - Virtex SX 0 7//008 ::0 PM FPG_NonIO.Schoc Project Title Size: ate: File: Revision: Sheet of Time: FPG Power & Programming ssy: ltium Limited L, Rodborough Road NSW 086 ustralia TMS ONE M LK M0 M TK HSWP_EN TI PROG_ TO V V IN INIT V HSWPEN_0 G6 LK_0 G _IN_0 G PROG 0 H INIT 0 G S 0 G ONE_0 H RWR 0 H VTT_0 Y6 M_0 W PWRWN 0 W TMS_0 Y M0_0 W TO_0 Y TK_0 W M_0 Y OUT_USY_0 Y TI_0 Y TN_0 G TP_0 H UK XVSX-0FFG668 VUX M9 VUX N9 VUX P9 VUX W0 VUX H VUX W VUX J VUX V VUX H6 VUX W6 VUX H7 VUX N8 VUX P8 VUX R8 VINT K9 VINT L9 VINT T9 VINT U9 VINT J0 VINT K0 VINT L0 VINT T0 VINT U0 VINT V0 VINT J VINT L VINT T VINT V VINT M VINT R VINT M VINT R VINT J6 VINT L6 VINT T6 VINT V6 VINT J7 VINT K7 VINT L7 VINT T7 VINT U7 VINT V7 VINT K8 VINT L8 VINT T8 VINT U8 VO_ E VO_ E6 VO_ VO_ 6 VO_ VO_ 6 VO_ E VO_ VO_ H8 VO_ 9 VO_ E9 VO_ H9 VO_ J9 VO_ VO_ F VO_ F VO_6 F VO_6 VO_6 F VO_6 8 VO_6 E8 VO_6 J8 VO_6 H9 VO_6 H0 VO_7 W7 VO_7 W8 VO_7 V9 VO_7 9 VO_7 E9 VO_7 VO_7 E VO_7 VO_8 VO_8 VO_8 E VO_8 V8 VO_8 W8 VO_8 8 VO_8 E8 VO_8 W9 VO_9 M8 VO_9 K9 VO_9 U9 VO_9 L VO_9 T VO_9 L VO_9 T VO_9 P6 VO_0 N VO_0 L VO_0 T VO_0 L VO_0 T VO_0 K8 VO_0 U8 VO_0 R9 VO_0 V VO_0 J UL XVSX-0FFG668 P E E F J V F6 N M0 N0 P0 R0 K M N P R U E K L N P T U J K L M N P R T U V F J K L M N P R T U V F E K L N P T U K6 M6 N6 P6 R6 U6 M7 N7 P7 R7 8 8 F P J V E F 6 N6 E6 UM XVSX-0FFG668 VREFN_SM E VREFP_SM E6 V_SM F7 VN_SM F VP_SM F6 _SM E7 UN XVSX-0FFG668

10 V _M 0uF 0V V _FP 0uF 0V _FP 0uF 0V _FP 0uF 0V V _FP _FP 6_FP 7_FP 8_FP 9_FP 0_FP _FP V _FP _FP _FP _FP 6_FP 7_FP 8_FP 9_FP Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet 0 of File: ypass_fpg_v.sho FPG ypass apacitors for V ltium Limited L, Rodborough Road NSW 086 ustralia

11 V _M 0uF 0V V _FP 0uF 0V V _FP _FP 6_FP V 8_FP 9_FP _FP 6_FP Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: ypass_fpg_v.sho FPG ypass apacitors for V ltium Limited L, Rodborough Road NSW 086 ustralia

12 8_FP 0uF 0V 9_FP 0uF 0V 0_FP 0uF 0V _FP 0uF 0V _FP 0uF 0V _FP 0uF 0V _FP 0uF 0V _FP 0uF 0V 0_FP _FP _FP _FP 7_FP 6_FP 6_FP 6_FP 66_FP 67_FP 68_FP 70_FP 7_FP 7_FP 76_FP 77_FP 78_FP 80_FP 8_FP 8_FP 8_FP 86_FP 87_FP 89_FP 9_FP 9_FP 96_FP 99_FP 00_FP Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: ypass_fpg_.schoc FPG ypass apacitors for ltium Limited L, Rodborough Road NSW 086 ustralia

13 U S06 Vcc T N PIO PIO 6 I PIO PIO ONE_WIRE Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: W_S06_EPROM.Schoc -Wire us I ltium Limited L, Rodborough Road NSW 086 ustralia

14 STTUS LE POWER LE _SL R_SL 70R % R_SL 70R % LE_PWR STTUS_LE U_SL SN7LVG0V N V Y LE_PGM LE_SL GREEN LE_SL RE Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: _LES.Schoc aughter oard LEs ltium Limited L, Rodborough Road NSW 086 ustralia

15 HOSTMEMORY US_[..] US_[..0] US_SRM_NS US_SRM_NS US_SRM_NRS US_SRM_KE US_SRM_LK US_[..] US_[..0] US_[6..] US_[..0] SRM [6..] [..0] SRM_NS SRM_NS SRM_NRS SRM_KE SRM_LK NE[..0] NWE M_SRM OM_SRM SRM_MT8L6M6TG_6Mx SRM MEM US_FLSH_NS US_FLSH_NRESET US_FLSH_NUSY US_[..] US_[..0] FLSH [..] [..0] FLSH_NS FLSH_NRESET FLSH_NUSY NOE NWE M_FLSH OM_FLSH FLSH_S9GL6NFFIV0_6Mx6 FLSH SRM US_SRM_NS US_NE[..0] US_NOE US_NWE US_[0..] US_[..0] [0..] [..0] NS NE[..0] NOE NWE M_SRM OM_SRM SRM_6Kx_TSOP_ SRM ommon-us Memory lock 6K x -bit SRM ( Myte) 6M x -it SRM (6 Myte) 6M x 6-it Flash ( Myte) Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: N_ommonMemory.Schoc ommon-us Memory lock ltium Limited L, Rodborough Road NSW 086 ustralia

16 FLSH FLSH [..0] [..] FLSH_NS NOE NWE FLSH_NRESET US_[..0] US_[..] US_ US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_ US_ E E7 8 8 F G F7 U S9GL6NFFIV E# OE# WE# WP#/ RESET# YTE# Q0 Q Q Q Q Q Q6 Q7 Q8 Q9 Q0 Q Q Q Q Q/- V VIO VIO RY/Y# E H E H H E H6 E6 F G F G F G6 F6 G7 G 8 F E8 H7 H US_0 US_ US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_ US_ US_ N N N N N N N N N N N 8 F8 G8 H8 E G H FLSH_NUSY 6 Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: File: 7//008 Time: ::0 PM Sheet 6 of FLSH_S9GL6NFFIV0_6Mx6.Schoc 6M x 6 Flash Memory (G) ltium Limited L, Rodborough Road NSW 086 ustralia

17 7 6 - Virtex SX 0 7//008 ::0 PM SRM_MT8L6M6TG_6Mx.Schoc Project Title Size: ate: File: Revision: Sheet of Time: 6M x SRM TSOP x ssy: ltium Limited L, Rodborough Road NSW 086 ustralia [6..] [..0] NE[..0] NWE SRM_NS SRM_NRS SRM_KE SRM_LK SRM_NS SRM US_SRM_LK US_SRM_KE US_SRM_LK US_SRM_KE US_[6..] US_[..0] US_NE[..0] US_SRM_NS US_SRM_NRS V Q0 VQ Q Q Q 6 Q 7 Q 8 VQ 9 Q 0 Q6 Q Q7 V QML WE 6 S 7 RS 8 S V KE 7 LK 8 QMH 9 N 0 Q8 VQ Q9 Q0 Q 6 Q 7 Q 8 VQ 9 Q 0 Q Q Q U SRM-6Mx6 V Q0 VQ Q Q Q 6 Q 7 Q 8 VQ 9 Q 0 Q6 Q Q7 V QML WE 6 S 7 RS 8 S V KE 7 LK 8 QMH 9 N 0 Q8 VQ Q9 Q0 Q 6 Q 7 Q 8 VQ 9 Q 0 Q Q Q U SRM-6Mx6 US_SRM_LK US_SRM_KE US_NWE US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_0 US_ US_ US_ US_ US_6 US_ US_7 US_8 US_9 US_0 US_ US_ US_ US_ US_ US_ US_6 US_ US_ US_ US_ US_6 US_7 US_8 US_9 US_0 US_ US_ US_SRM_NS US_NWE US_SRM_NS US_SRM_NRS US_NE0 US_NE US_NE US_NE US_SRM_NS US_NWE US_SRM_NS US_SRM_NRS US_ US_ US_ US_ US_SRM_NS US_6 US_8 US_7 US_0 US_9 US_ US_ US_ US_ US_ US_6 US_8 US_7 US_ US_0 US_9 US_ US_6 SRM

18 8 is connected so that Kx6 device can be fitted U SRM-6Kx6 U SRM-6Kx6 SRM SRM [0..] [..0] NS NWE NOE NE[..0] SRM_[0..] SRM_[..0] SRM_NS SRM_NWE SRM_NOE SRM_NE[..0] SRM_ SRM_ SRM_ SRM_ SRM_6 SRM_NS 6 SRM_0 7 SRM_ 8 SRM_ 9 SRM_ 0 SRM_ SRM_ SRM_6 SRM_7 6 SRM_NWE 7 SRM_7 8 SRM_8 9 SRM_9 0 SRM_0 SRM_ 0 S 0 V 6 7 WE OE HE LE V N SRM_9 SRM_8 SRM_7 SRM_NOE SRM_NE SRM_NE0 SRM_ SRM_ SRM_ SRM_ SRM_ SRM_0 SRM_9 SRM_8 SRM_0 SRM_6 SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_6 SRM_NS 6 SRM_6 7 SRM_7 8 SRM_8 9 SRM_9 0 SRM_0 SRM_ SRM_ SRM_ 6 SRM_NWE 7 SRM_7 8 SRM_8 9 SRM_9 0 SRM_0 SRM_ 0 S 0 V 6 7 WE OE HE LE V N SRM_9 SRM_8 SRM_7 SRM_NOE SRM_NE SRM_NE SRM_ SRM_0 SRM_9 SRM_8 SRM_7 SRM_6 SRM_ SRM_ SRM_0 SRM_6 SRM_ SRM_ SRM_ SRM_ K x SRM - TSOP x Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: File: 7//008 Time: ::0 PM Sheet 8 of SRM_6Kx_TSOP_.Schoc ltium Limited L, Rodborough Road NSW 086 ustralia

19 6 7 8 MEM HOSTMEMORY US_[..] US_[..0] US_NE[..0] US_NOE US_NWE US_SRM_NS US_SRM_NS US_SRM_NRS US_SRM_KE US_SRM_LK US_FLSH_NS US_FLSH_NRESET US_SRM_NS US_[..] US_[..0] US_NE[..0] US_NOE US_NWE US_SRM_NS US_SRM_NS US_SRM_NRS US_SRM_KE US_SRM_LK US_FLSH_NS US_FLSH_NRESET US_SRM_NS THESE SIGNLS TERMINTE T THE SRM EVIE US_FLSH_NUSY RN RESNET x 00R RN RESNET x 00R RN7 RESNET x 00R US_NE US_NE0 US_NWE US_SRM_NS US_SRM_NRS US_SRM_NS US_NE US_NE US_SRM_KE US_SRM_LK RN RESNET x 00R RN6 RESNET x 00R RN8 RESNET x 00R ll devices using controlled impedance outputs from the source (ie. FPG) should use 0 ohm ( parallel 00 ohm resistors) termination. The Flash should be located closest to the source (FPG). The SRM should be located next furthest from the source (FPG). The SRM should be located next furthest from the source (FPG). Terminations are to be located at the furthest distance from the source (FPG). Note that pins,6,7 and 8 of the following resnet "groups" are pin-swappable within that "group": - all "power" resnets that terminate the FLSH-only signals (ie. RN and RN). - all "ground" resnets that terminate the FLSH-only signals (ie. RN and RN). - all "power" resnets that terminate the FLSH-SRM-only signals (ie. RN and RN7). - all "ground" resnets that terminate the FLSH-SRM-only signals (ie. RN6 and RN8). - all "power" resnets that terminate the FLSH-SRM-SRM signals (ie. RN9, RN, RN, RN, RN7, RN9, RN, RN, RN, RN7, RN9, RN, RN, RN). - all "ground" resnets that terminate the FLSH-SRM-SRM signals (ie. RN0, RN, RN, RN6, RN8, RN0, RN, RN, RN6, RN8, RN0, RN, RN, RN6). To remove any confusion by the P assembler, the following devices have been deleted entirely from the design: RN to RN6, and RN7 to RN. Note that high current (up to. mps) is drawn from the rail when all 9 pairs of resnets are loaded. The addition of up to. watts of heat was significantly warming the P. Testing has confirmed that the loading of only pairs of resnets (RN/, RN/6 and RN7/8) provides good operation at speeds up to 96MHz. This consumes up to 0.0 amps, ie. up to 0.6 watts of heat. The loading of the pairs of resnets terminates only the output control signals from the FPG to the SRM. The bidirectional data bus and address bus is not terminated. Signals that do not connect to the SRM (ie. signals to the slower flash and SRM devices only) are also not terminated. 6 Project Title Size: ate: File: Memory ommonus Terminations 6 - Virtex SX ssy: Revision: 0 7//008 Time: ::0 PM Sheet 9 of N_ommonMemory_Termination.Schoc 7 ltium Limited L, Rodborough Road NSW 086 ustralia 8

20 U_SM SRM-6Kx6 SRM SRM-6Kx6 [8..0] [..0] NS NWE NOE NHE NLE SRM_[8..0] SRM_[..0] SRM_NS SRM_NWE SRM_NOE SRM_NHE SRM_NLE SRM_0 SRM_ SRM_ SRM_ SRM_ SRM_NS 6 SRM_0 7 SRM_ 8 SRM_ 9 SRM_ 0 SRM_ SRM_ SRM_6 SRM_7 6 SRM_NWE 7 SRM_ 8 SRM_6 9 SRM_7 0 SRM_8 SRM_9 0 S 0 V 6 7 WE OE HE LE V N SRM_7 SRM_6 SRM_ SRM_NOE SRM_NHE SRM_NLE SRM_ SRM_ SRM_ SRM_ SRM_ SRM_0 SRM_9 SRM_8 SRM_8 SRM_ SRM_ SRM_ SRM_ SRM_0 8 is connected so that Kx6 device can be fitted _SM _SM _SM _SM Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet 0 of File: SRM_6Kx6_TSOP.Schoc 6K x 6-it SRM ltium Limited L, Rodborough Road NSW 086 ustralia

21 6 7 8 FPG_TK TK ONE_WIRE P FPG_TI ONE_WIRE P TI HR FPG_TO ONE_WIRE_PIO NT TO ONE_WIRE_PIO FPG_TMS TMS ONE_WIRE_I ONE_WIRE_I JTG NEXUS_TK TK UZZER NEXUS_TI UZZER TI SOFT NEXUS_TO U_RESET_SW TO U_RESET_SW NEXUS_TMS TMS SLEEP_N SLEEP_N LE8 V0 WS VX (NOW PHSE OUT) HR_ MOLEX EXTEN_0 EXTEN_0 USER_LE L[7..0] USER_LE[7..0] EXTEN_ EXTEN_ EXTEN_ 6 EXTEN_ EXTEN_ 7 8 EXTEN_ PIO EXTEN_ 9 0 EXTEN_ EXT_ [9..0] EXTEN_[9..0] EXTEN_ EXTEN_ EXTEN_6 EXTEN_6 EXTEN_7 6 EXTEN_7 PIO EXTEN_8 7 8 EXTEN_8 EXTEN_[9..0] EXT_ [9..0] EXTEN_9 9 0 EXTEN_9 EXTEN_0 EXTEN_0 PIO EXTEN_ EXTEN_ EXT_ [9..0] EXTEN_[9..0] EXTEN_ 6 EXTEN_ EXTEN_ 7 8 EXTEN_ EXTEN_ 9 0 EXTEN_ EXTEN_ EXTEN_ Note that the signal ONE_WIRE_I was SPI_LK LK EXTEN_6 EXTEN_6 previously called FPG_LK. SPI_IN IN EXTEN_7 6 EXTEN_7 SPI_OUT SPI OUT EXTEN_8 7 8 EXTEN_8 SPI_MOE This signal was included in N design, but MOE EXTEN_9 9 0 EXTEN_9 SPI_SEL never used. Hence it has now been reallocated. SEL EXTEN_0 EXTEN_0 EXTEN_ EXTEN_ TFT EXTEN_ 6 EXTEN_ U_TFT_RE[..0] RE[..0] EXTEN_ 7 8 EXTEN_ U_TFT_GREEN[..0] GREEN[..0] EXTEN_ 9 0 EXTEN_ U_TFT_LUE[..0] LUE[..0] EXTEN_ EXTEN_ U_TFT_M M EXTEN_6 EXTEN_6 U_TFT_POL POL EXTEN_7 6 EXTEN_7 U_TFT_L[..] L[..] EXTEN_8 7 8 EXTEN_8 U_TFT_STV STV EXTEN_ EXTEN_9 U_TFT_STH STH EXTEN_0 6 6 EXTEN_0 U_TFT_ISP_ON ISP_ON EXTEN_ 6 6 EXTEN_ U_TFT_LIGHT LIGHT EXTEN_ 6 66 EXTEN_ U_TFT_IRQ IRQ EXTEN_ EXTEN_ U_TFT_MUX MUX EXTEN_ EXTEN_ EXTEN_ 7 7 EXTEN_ EXTEN_6 7 7 EXTEN_6 INSTLLE FPG_LK EXTEN_ EXTEN_7 LK FPG_IN EXTEN_ EXTEN_8 IN FPG_ONE EXTEN_ EXTEN_9 ONE FPG_I[..0] EXTEN_0 8 8 EXTEN_0 I[..0] PROGRM FPG_INIT EXTEN_ 8 8 EXTEN_ INIT FPG_M[..0] EXTEN_ 8 86 EXTEN_ M[..0] FPG_PROG_LK EXTEN_ EXTEN_ PROG_LK FPG_PROG_PWR_ON EXTEN_ EXTEN_ PROG_PWR_ON FPG_PROGRM EXTEN_ 9 9 EXTEN_ PROGRM EXTEN_6 9 9 EXTEN_6 LOKS FPG_LK EXTEN_ EXTEN_7 FPG_LK REF_LK EXTEN_ EXTEN_8 REF_LK FPG_LK EXTEN_ EXTEN_9 FPG_LK N MH MH N_TX TX N_RX RX MOLEX KEYOR Green connections are I/O pins connected to N compatible P resources on the mother board. These can be changed. 6 N to aughter oard onnectors Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: File: 7//008 Time: ::0 PM _Motheroardonnectors.Schoc Sheet of 7 ltium Limited L, Rodborough Road NSW 086 ustralia 8 SL S IO0 IO IO IO IO IO IO6 IO7 IO8 IO9 IO0 IO IO IO IO IO IO6 IO7 IO8 IO9 IO0 IO IO IO IO IO IO6 IO7 IO8 IO9 IO0 IO IO IO IO IO ONE_WIRE P U_TFT_IRQ U_TFT_POL U_TFT_MUX U_TFT_M U_TFT_ISP_ON U_TFT_LIGHT MH MH MH MH FPG_LK REF_LK USER_LE0 USER_LE USER_LE USER_LE USER_LE USER_LE USER_LE6 USER_LE7 IP0 IP IP IP IP IP IP6 IP7 U_RESET_SW UZZER SW0 SW SW SW SW U_TFT_RE0 U_TFT_RE U_TFT_RE U_TFT_RE U_TFT_RE U_TFT_LUE0 U_TFT_LUE U_TFT_LUE U_TFT_LUE U_TFT_LUE U_TFT_GREEN0 U_TFT_GREEN U_TFT_GREEN U_TFT_GREEN U_TFT_GREEN U_TFT_GREEN U_TFT_STV U_TFT_STH U_TFT_L U_TFT_L U_TFT_L MH MH EXTEN_9 EXTEN_7 EXTEN_8 EXTEN_ 6 EXTEN_6 EXTEN_ 7 8 EXTEN_ EXTEN_ 9 0 EXTEN_ EXTEN_9 EXTEN_0 EXTEN_8 N_RX EXTEN_7 6 N_TX EXTEN_6 7 8 RS_RTS EXTEN_ 9 0 RS_TX EXTEN_ RS_TS EXTEN_ RS_RX EXTEN_ 6 EXTEN_ 7 8 EXTEN_0 9 0 EXTEN_9 EXTEN_8 EXTEN_7 6 EXTEN_6 7 8 EXTEN_ 9 0 EXTEN_ EXTEN_ EXTEN_ EXTEN_ 7 8 EXTEN_0 9 0 EXTEN_9 EXTEN_8 EXTEN_7 6 EXTEN_6 7 8 EXTEN_ 9 60 EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_0 EXTEN_9 EXTEN_8 EXTEN_7 EXTEN_6 EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_ EXTEN_0 ONE_WIRE_PIO MH MH KLOK KT MOUSELOK MOUSET FPG_INSTLLE FPG_I FPG_I FPG_I FPG_I0 SPI_IN SPI_LK SPI_SEL SPI_OUT SPI_MOE FPG_TO FPG_M FPG_M FPG_M0 FPG_PROGRM FPG_IN FPG_LK FPG_INIT FPG_TMS FPG_TK FPG_ONE NEXUS_TO FPG_TI NEXUS_TMS NEXUS_TK NEXUS_TI FPG_PROG_PWR_ON FPG_PROG_LK FPG_LK ONE_WIRE_I SW IP USERIO I RS MOUSE SW SW8 IO6 [..0] [7..0] IO[..0] SL S TX RTS RX TS T LOK T LOK SW[..0] IP[7..0] IO[..0] SL S RS_TX RS_RTS RS_RX RS_TS KT KLOK MOUSET MOUSELOK HR_L MH MH HR_T MOLEX SLEEP_N Red onnections are locked for N compatibility. They are hardwired on the N and therefore can NOT be changed. lue connections are connected to the New N compatible resources on the motherboard. These can be changed. V0 WS VX (NOW PHSE OUT)

22 U_MOUNTS _MOUNTS P 6 lank P Printed ircuit oard (are) Fiducial lignment omponents F Fiducial - Round F Fiducial - Round Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: 6_Hardware_Kit.Schoc 6 Hardware Kit ltium Limited L, Rodborough Road NSW 086 ustralia

23 MH MOUNTING HOLE MM ltium Logo Top MH MOUNTING HOLE MM MH MOUNTING HOLE MM ltium Logo ot Project Title 6 - Virtex SX Size: ssy: Revision: 0 ate: 7//008 Time: ::0 PM Sheet of File: _MOUNTS.Schoc Mounts, Logo & Label ltium Limited L, Rodborough Road NSW 086 ustralia