Optional IOB31 Board. x1 PCIe Link* (Expansion) x8 PCIe Connector. (PCIe1) x4 PCIe Link (B0) x8 PCIe Connector. (PCIe2)

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1 Technical Information Jumpers and s BPG () Small Form Factor PCI Express Backplane Block Diagram x PCIe (PCIe) x PCIe Link (A0) PICMG. System Host Board Optional IOB Board x PCIe Link* (Expansion) s (P & P) Ethernet s (P & P) I/0 Power (P0) BPG Backplane System Host Board Slot (Edge connectors A, B & C) x PCIe Link (B0) x PCIe (PCIe) x PCIe (PCIe) +V Power P ATX or EPS Power P *Assumes Trenton TL or TML system host board Layout Diagram.0.0* P P x PCIe Link (B0).* * = *.*. x PCIe Link PCIeS P P Ethernet Ports x mech. x elect. x PCIe Link (A0) x mech. x elect. JU x mech. x elect. P Notes: SHB Slot P0 P P P P P P.0 Copyright c00 Trenton Technology Inc *IOB Required to provide PCI Express link to PCIE slot **Optional and Ethernet connectivity provided by PICMG. SHB. Not all SHBs support this capability. spacing: 0.00 Nominal PCB thickness:.0 Mounting holes:. diameter All dimensions are inches. Trenton Support Center BPG () Technical Information -- s

2 BPG () Configuration Jumper The setup of the configuration jumper on the backplane is described below. * indicates the default value of the jumper. NOTE: For the two-position jumper (-post), RIGHT and LEFT refer to positioning when the backplane is viewed with the slots at the top end of the backplane. Jumper JU Description +V Auxiliary Voltage Install on the LEFT if +V auxiliary voltage is provided by the standard +V supply. This option is used for systems which do not have either an ATX or EPS standard power input. This mode provides the necessary +V for the SHB s +VAUX signal lines. Sleep mode recovery is not supported using non- ATX/EPS power supplies. Install on the RIGHT if +V auxiliary voltage is provided by a separate +VAUX signal input pin. This enables the necessary SHB power signaling and allows recovery from sleep mode. This option is used for ATX or EPS standard power supplies. * BPG () s The connectors available on the BPG vary depending on the version of the backplane you have. s for the -00 (right angle connectors) and -00 (straight- in/vertical connectors) are defined below. BPG (-00) s NOTE: on the connectors is indicated by the square pad on the PCB. P - ATX/EPS Power pin right angle dual row header, Amp #- 0 +.V +.V +V +V +VAUX +V +V +.V 0 +.V -V -V +V +V +V Trenton Support Center BPG () Technical Information -- s

3 BPG (-00) s (continued) P - +V Power pin right angle mini fit JR, Molex # V +V +V +V P - Power-On pin single row header, Amp #0- P - Power Button pin single row header, Amp #0- P - Reset pin single row header, Amp #0- P - Power Good pin single row header, Amp #0- P0 - I/O Power 0 pin right angle dual row header, Molex #-00 IPMB_DA IPMB_CL SMDAT SMCLK 0 +V +V +VAUX +.V 0 +VAUX +VAUX -V Trenton Support Center BPG () Technical Information -- s

4 BPG (-00) s (continued) P - Universal Serial Bus () pin dual row header, Molex #0--00 (+V fused with self-resetting fuses) +V V P - Universal Serial Bus () pin dual row header, Molex #0--00 (+V fused with self-resetting fuses) +V V P - 0/00/000Base-T Ethernet - LAN 0 pin shielded RA RJ- connector, Molex #0- TRP+ TRP- TRP+ TRP+ TRP- TRP- TRP+ TRP- P - 0/00/000Base-T Ethernet - LAN pin shielded RA RJ- connector, Molex #0- TRP+ TRP- TRP+ TRP+ TRP- TRP- TRP+ TRP- P - System Management Bus pin single row header, Amp #0- SMB Clock SMB Data Trenton Support Center BPG () Technical Information -- s

5 BPG (-00) s P - ATX/EPS Power pin dual row mini fit JR, Molex # V +.V +V +V +VAUX +V +V +.V 0 +.V -V -V +V +V +V P - +V Power pin mini fit JR, Molex #--0 +V +V +V +V P - Power-On pin single row header, Amp #0- P - Power Button pin single row header, Amp #0- P - Reset pin single row header, Amp #0- P - Power Good pin single row header, Amp #0- Trenton Support Center BPG () Technical Information -- s

6 BPG (-00) s (continued) P0 - I/O Power 0 pin right angle dual row header, Molex #-00 IPMB_DA IPMB_CL SMDAT SMCLK 0 0 +V +V +VAUX +.V +VAUX +VAUX -V P - P - Universal Serial Bus () pin dual row header, Molex #0--00 (+V fused with self-resetting fuses) +V V Universal Serial Bus () pin dual row header, Molex #0--00 (+V fused with self-resetting fuses) +V V P - 0/00/000Base-T Ethernet - LAN 0 pin shielded RA RJ- connector, Molex #0- TRP+ TRP- TRP+ TRP+ TRP- TRP- TRP+ TRP- Trenton Support Center BPG () Technical Information -- s

7 BPG (-00) s (continued) P - 0/00/000Base-T Ethernet - LAN pin shielded RA RJ- connector, Molex #0- TRP+ TRP- TRP+ TRP+ TRP- TRP- TRP+ TRP- P - System Management Bus pin single row header, Amp #0- SMB Clock SMB Data Trenton SHB Optional Backplane I/O Support For the BPG TRENTON ETHERNET SHB LAN 0 LAN LAN 0 TQ, - - X X X X X TL, - - X X X X X TML, - - X X X X X MCG-series - - X X X X X LAN is a 0/00BASE-T Ethernet interface when using the TQ, TL or TML Backplane routings of interfaces & are factory build options on the TL and TML LAN is a 0/00/000BASE-T Ethernet interface when using a MCG-series SHB interfaces,, and are logical interfaces,, 0 and on the TQ system host board Note: The letter X indicates an interface connection routed to SHB edge connector C for use on the backplane. Configuration Illustrated For The BPG MODEL# MODEL NAME DESCRIPTION -00 BPG-CRA ATX/EPS right-angle connectors -00 BPG-CST ATX/EPS vertical connectors Trenton Support Center BPG () Technical Information -- s

x16 PCIe Link* (A0) x16 PCIe Connector (PCIe2) 64-bit/133MHz PCI-X PCI-X Connector (SLTA1) PCI-X Connector (SLTB1) 64-bit/133MHz PCI-X

x16 PCIe Link* (A0) x16 PCIe Connector (PCIe2) 64-bit/133MHz PCI-X PCI-X Connector (SLTA1) PCI-X Connector (SLTB1) 64-bit/133MHz PCI-X Technical Information Jumpers and s BPG/ () Small Form Factor PCI Express Backplane Block Diagram PICMG. System Host Board s (P & P) BPG/ Backplane System Host Board Slot (Edge connectors A, B & C) x PCIe

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