sop8 dip8 HIGH SPEED CAN TRANSCEIVER 100%

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1 STC00 sop dip _ 0// _ 0// 0: 0:0 sop dip HIGH SPEED CAN TRANSCEIVER DESCRIPTION The STCompoet STC00 is the iterface betwee the Cotroller Area Network (CAN) protocol cotroller ad the physical bus. The STC00 provides differetial trasmit capability to the bus ad differetial receive capability to the DIP SOP CAN cotroller. It is primarily iteded for high speed applicatios, up to MBaud, i passeger cars. RE The STC00 is pi compatible with STC00 high speed CAN trasceiver ad offers the excellet EMC performace. The features iclude a ideal passive behavior whe supply voltage is off, ad a very lowcurret stadby mode with remote wakeup capability via the bus. 00% 00% Fwfg_z%eBvAzdHFfAzdHFtrb&gsm=c&rpstart=0&rpum=0 RE jofazdhfdacbadm9lc0_z%ebips&gsm=be&rpstart=0&rpum=0 FEATURES Fully Compatible with ISO 9 Stadard High Speed (Up to MBaud) Very Low ElectroMagetic Emissio (EME) Differetial Receiver with High CommoMode Rage for ElectroMagetic Immuity (EMI) Trasceiver i Upowered State Disegages from the Bus (Zero Load) Iput Levels Compatible with.v ad.0v Devices Source for Stabilizig the Recessive Bus Level If Split Termiatio is Used (Further Improvemet of EME) At Least 0 Nodes ca be Coected Trasmit Data (TXD) Domiat TimeOut Fuctio Bus Pis Protected Agaist Trasiets i Automotive Eviromets Bus Pis ad Pi SPLIT ShortCircuit Proof to Battery ad Groud Thermally Protected sop dip _ 0// _ 0// 0: 0:0 sop dip DEVICE SUMMARY DIP SOP 00% 00% Orderig Code STC00B Package Material Lead Free SOP Fwfg_z%eBvAzdHFfAzdHFtrb&gsm=c&rpstart=0&rpum=0 STC00BG Haloge Free Package Type () ShippigRE Markig Tapig reel 00 YM jofazdhfdacbadm9lc0_z%ebips&gsm=be&rpstart=0&rpum=0 RE Note : Y: Year code. M: Moth code. V.0 of ST XX YM

2 STC00 INTERNAL SCHEMATIC DIAGRAM V CC TXD V CC TimeOut & Slpoe Thermal Protectio V SPLIT SPLIT CANH STB WakeUp Mode Cotrol Driver CANL R R RXD MUX WakeUp Filter R R GND STC00 Curret Curret Badgap Referece Badgap Referece PIN DESCRIPTION PIN SYMBOL FUNCTION DESCRIPTION TXD Trasmit data iput. GND Groud. V CC Supply voltage. RXD Receive data output; Reads out data from the bus lies. SPLIT Commomode stabilizatio output. CANL Lowlevel CAN bus lie. CANH Highlevel CAN bus lie. STB Stadby mode cotrol iput. V.0 of

3 STC00 ABSOLUTE MAXIMUM RATINGS () T A = C, uless otherwise specified. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT Supply V CC No time limit 0..0 V Operatig rage.. V TXD Pi DC V TXD 0. V CC 0. V RXD Pi DC V RXD 0. V CC 0. V STB Pi DC V STB 0. V CC 0. V CANH Pi DC V CANH 0V < V CC <.V, o time limit 0 V CANL Pi DC V CANH 0V < V CC <.V, o time limit 0 V SPLIT Pi DC V SPLIT 0V < V CC <.V, o time limit 0 V CANH, CANL ad SPLIT Pis Trasiet V TRT Accordig to ISO V ESD Huma Body Model HBM CANH, CANL & SPLIT pis () V Other pis V Machie Model () MM V Virtual Juctio Temperature () T VJ 0 0 C Storage Temperature T st g 0 C Note : Absolute Maximum Ratigs are stress ratigs oly ad fuctioal device operatio is ot implied. The device could be permaetly damaged beyod absolute maximum ratigs. Note : Equivalet to dischargig a 00pF capacitor via a.kω series resistor. Note : Equivalet to dischargig a 00pF capacitor via a 0.µH series iductor ad a 0Ω series resistor. Note : Juctio temperature i accordace with IEC 0. A alterative defiitio of T VJ is: T VJ = T amb P R th(vjamb), where R th(vjamb) is a fixed value to be used for the calculatig of T VJ. The ratig for T VJ limits the allowable combiatios of power dissipatio (P) ad ambiet temperature (T amb). V.0 of

4 STC00 ELECTRICAL CHARACTERISTICS () V CC =.V ~.V, T VJ = 0 C ~ 0 C, ad R L = 0Ω uless otherwise oted. All voltages are defied with respect to GND; positive currets flow ito the IC. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT V CC Supply Pi Supply Curret Stadby mode I CC 0 µa Trasmit Data Iput (TXD) Pi Normal mode Recessive; V TXD = V CC. 0 ma Domiat; V TXD = 0V ma High Level Iput V IH V CC 0. V Low Level Iput V IL V High Level Iput Curret I IH V TXD = V CC 0 µa Low Level Iput Curret I IL Normal mode, V TXD = 0V µa Iput Capacitace C i Not tested 0 pf Stadby Mode Cotrol Iput (STB) Pi High Level Iput V IH V CC 0. V Low Level Iput V IL V High Level Iput Curret I IH V STB = V CC 0 µa Low Level Iput Curret I IL V STB = 0V 0 µa Receive Data Output (RXD) Pi High Level Output V OH Stadby mode, I RXD = 00µA V CC. V CC 0. V CC 0. V High Level Output Curret I OH Normal mode, V RXD = V CC 0.V ma Low Level Output Curret I OL V RXD = 0.V 0 ma CommoMode Stabilizatio Output (SPLIT) Pi Output V O Leakage Curret I L Bus Lies (CANH & CANL) Pis Normal mode, 00µA < I O < 00µA Stadby mode, V < V SPLIT < V 0.V CC 0.V CC 0.V CC V 0 µa Domiat Output V O(dom) V TXD = 0V CANH pi.. V CANL pi 0... V Matchig of Domiat Output V O(dom)(m) V CC V CANH V CANL mv V.0 of

5 STC00 V CC =.V ~.V, T VJ = 0 C ~ 0 C, ad R L = 0Ω uless otherwise oted. All voltages are defied with respect to GND; positive currets flow ito the IC. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Bus Lies (CANH & CANL) Pis Differetial Bus Output (V CANH V CANL ) V O(dif)(bus) V TXD = 0V, domiat, Ω < R L < Ω..0 V V TXD = V CC, recessive, o load 0 0 mv Recessive Output V O(reces) Normal mode, V TXD = V CC, o load 0.V CC V ShortCircuit Output Curret I O(SC) V TXD = 0V Stadby mode, o load V V CANH = 0V, measure CANH ma V CANL = 0V, measure CANL ma Recessive Output Curret I O(reces) V < V CAN < V.. ma Differetial Recessive Threshold V dif(th) V < V CANL & V CANH < V Normal mode () V Stadby mode V Differetial Receiver Hysteresis V hys(dif) V < V CANL & V CANH < V, ormal mode mv Iput Leakage Curret I LI V CC = 0V, V CANH = V CANL = V 0 µa CommoMode Iput Resistace R i(cm) Stadby or ormal mode kω CommoMode Iput Resistace Matchig R i(cm)(m) V CANH = V CANL 0 % Differetial Iput Resistace R i(dif) Stadby or ormal mode 0 kω CommoMode Iput Capacitace C i(cm) V TXD = V CC, ot tested 0 pf Differetial Iput Capacitace C i(dif) V TXD = V CC, ot tested 0 pf Timig Characteristics () Delay TXD to Bus Active t d(txdbuso) Normal mode 0 0 s Delay TXD to Bus Iactive t d(txdbusoff) s Delay Bus Active to RXD t d(busorxd) s Delay Bus Iactive to RXD t d(busoffrxd) 00 0 s Propagatio Delay TXD to RXD t PD(TXDRXD) V STB = 0V 0 s TXD Domiat TimeOut t dom(txd) V TXD = 0V µs V.0 of

6 STC00 VCC =.V ~.V, TVJ = 0 C ~ 0 C, ad RL = 0Ω uless otherwise oted. All voltages are defied with respect to GND; positive currets flow ito the IC. PARAMETER Timig Characteristics SYMBOL TEST CONDITIONS MIN TYP MAX UNIT () Domiat Time for WakeUp via Bus tbus Stadby mode 0.. µs Delay Stadby Mode to Normal Mode td(stborm) Normal mode. 0 µs 0 C Thermal Shutdow Shutdow Juctio Temperature TJ(sd) Note : All parameters are guarateed i the virtual juctio temperature rage by desig, but oly 00% tested at C ambiet temperature for fial tested. Note : See the Figure. Note : See the Figure ad Figure. sop dip _ 0// _ 0// 0: 0:0 sop dip ST XX YM TEST INFORMATION AND CIRCUIT DIP SOP 00% 00% V RE 00kHz µf Fwfg_z%eBvAzdHFfAzdHFtrb&gsm=c&rpstart=0&rpum=0 00F TXD jofazdhfdacbadm9lc0_z%ebips&gsm=be&rpstart=0&rpum=0 pf GND STB CANH RE F STC00 VCC CANL RXD SPLIT 00 YM Trasiet Geerator F Figure : Automotive Trasiets Test Circuit VRXD R R R HIGH R LOW hysteresiscurret 0. Curret Badgap Referece Badgap Referece 0.9 R R Vi(dif)(bus) (V) Figure : Hysteresis of the Receiver V.0 Curret Badgap Referece of R R

7 STC00 V µf 00F TXD STB GND V CC CANH STC00 CANL R L 0Ω C L 00pF pf RXD SPLIT Figure : Test Circuit for Timig Characteristics TXD HIGH LOW CANH CANL RXD 0.V CC 0.V CC HIGH LOW Domiat (BUS o) V i(dif)(bus) * 0.9V 0.V t d(txdbuso) t d(txdbusoff) t d(busorxd) t PD(TXDRXD) t d(busoffrxd) t PD(TXDRXD) *: V i(dif)(bus) = V CANH V CANL Figure : Timig Diagram V.0 of

8 STC00 FUNCTIONAL DESCRIPTION Operatig Modes The STC00 provides modes of operatio which are selectable via pi STB. See Table for a descriptio of the modes of operatio. Table : Operatig Modes Mode STB Pi LOW RXD Pi HIGH Normal mode LOW Bus domiat Bus recessive Stadby mode HIGH Wakeup request detected No wakeup request detected Normal mode I this mode the trasceiver is able to trasmit ad receive data via the bus lie CANH ad CANL. See the Iteral Schematic Diagram. The differetial receiver coverts the aalog data o the bus lies ito digital data which is output to RXD pi via the multiplexer (MUX). The slope of the output sigals o the bus lies is fixed ad optimized i a way that lowest ElectroMagetic Emissio (EME) is guarateed. Stadby mode I this mode the trasmitter ad receiver are switched off, ad the lowpower differetial receiver will moitor the bus lies. The supply curret o V CC is reduced to a miimum i such a way that ElectroMagetic Immuity (EMI) is guarateed ad a wakeup evet o the bus lies will be recogized. I this mode the bus lies are termiated to groud to reduce the supply curret (I CC ) to a miimum. A diode is added i series with the highside driver of RXD to prevet a reverse curret from RXD to V CC i the upowered state. I ormal mode this diode is bypassed. This diode is ot bypassed i staby mode to reduce curret cosumptio. V CC Split Circuit Pi SPLIT provides a DC stabilized voltage 0f 0.V CC. It is tured o oly i ormal mode. I stadby mode pi SPLIT is floatig. The V SPLIT circuit ca be coectig pi SPLIT to the ceter tap of the split termiatio (See Figure ). I case of a recessive bus voltage < 0.V CC due to the presece of a usupplied trasceiver i the etwork with a sigificat leakage curret from the bus lies to groud, the split circuit will stabilize this recessive voltage to 0.V CC. So a start of trasmissio does ot cause a step i the commomode sigal which would lead to poor ElectroMagetic Emissio (EME) behavior. I ormal mode, V SPLIT = 0.V CC R R GND CANH SPLIT CANL 0Ω 0Ω Figure : Stabilizatio Circuitry ad Applicatio V.0 of

9 STC00 WakeUp I the stadby mode the bus lies are moitored via a lowpower differetial comparator. Oce the lowpower differetial comparator has detected a domiat bus level for more tha t BUS, pi RXD will become LOW. OverTemperature Detectio The output drivers are protected agaist overtemperature coditios. If the virtual juctio temperature exceeds the shutdow juctio temperature T J(sd), the output drivers will be disabled util the virtual juctio temperature becomes lower tha T J(sd) ad TXD becomes recessive agai. By icludig the TXD coditio, the occurrece of output driver oscillatio due to temperature drifts is avoided. TXD Domiat TimeOut Fuctio A TXD domiat timeout timer circuit prevets the bus lies from beig drive to a permaet domiat state (blockig all etwork commuicatio) if pi TXD is forced permaetly LOW by a hardware ad/or software applicatio failure. The timer is triggered by a egative edge o TXD pi. If the duratio of the LOW level o TXD pi exceeds the iteral timer value (t dom ), the trasmitter is disabled, drivig the bus lies ito a recessive state. The timer is reset by a positive edge o TXD pi. The TXD domiat timeout time t dom defies the miimum possible bit rate of 0kBaud. FailSafe Features Pi TXD provides a pullup towards V CC i order to force a recessive level i case TXD pi is usupplied. Pi STB provides a pullup towards V CC i order to force the trasceiver ito stadby mode i case STB pi is usupplied. I the evet that the V CC is lost, pis TXD, STB ad RXD will become floatig to prevet reverse supplyig coditios via these pis. V.0 9 of

10 R STC00 TYPICAL APPLICATION CIRCUIT BAT V V CC CANH SPLIT CANL GND STB STC00 RXD TXD V CC Port x Microcotroller RXD TXD GND Figure : Typical Applicatio for V Microcotroller R R R R R R R R Curret Curret Badgap Referece Badgap Referece Curret Curret Badgap R Referece R Badgap Referece Curret Badgap Referece V.0 0 of

11 STC00 PACKAGE DIMENSION SOP D A A E E L L b e c A SYMBOL Dimesios i Millimeters Dimesios i Iches MIN MAX MIN MAX A A A b c D E E e.0 (BSC) 0.00 (BSC) L V.0 of

12 STC00 NOTICE Iformatio furished by STCompoet is believed to be accurate ad reliable. However, o resposibility is assumed for its use. Customers are resposible for their products ad applicatios usig STCompoet compoets. To miimize the risks associated with customer products ad applicatios, customers should provide adequate desig ad operatig safeguards. STCompoet reserves the right to make chages to their products or specificatio without otice. Customers are advised to obtai the latest versio of relevat iformatio to verify, before placig orders, that iformatio beig relied o is curret ad complete. V.0 of