Documentation Standards

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1 Documentation Standards Circuit specification. Description of what the system is supposed to do, including a description of all inputs and outputs and the functions that are to be performed (page ). Block diagram. Informal pictorial description of the system s major functional modules. Schematic or logic diagram. Formal specification of the electrical components of the system, their interconnections, and all details needed to construct it (IC type, pin numbers, etc.).

2 Documentation Standards Timing diagram. Shows the values of various logic signals as a function of time, including cause and effect delays between critical signals. Structured logic device description. Describes the internal function of a programmable logic device (PLD), a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

3 Block Diagrams SHIFT-AND-ADD MULTIPLIER RESET LOAD RUN CONTROL R/W ADDR IN -word x -bit RAM DISPLAY BYTE EN OUT INBUS direct left right LDA LDB SEL MULTIPLEXER to A REGISTER B REGISTER CARRY LOOKAHEAD ADDER Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e OUTBUS

4 Block Diagrams (a) (b) -BIT REGISTER -BIT REGISTER x LS Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e (c) LS LS LS LS

5 Gate Symbols Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e AND NAND OR NOR BUFFER INVERTER (a) (b) (c) Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e (a) (b) (c) (d) Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e (a) (b) (c) (d) Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e (a) (b) (c) (d)

6 Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e SSI x00 x0 x0 x0 x x0 x x x0 x x x0 x x x

7 Active Levels For Pins Each signal should have an active level associated with it. A signal is active high if it performs the named action or denotes the named condition when it is HIGH or. A signal is active low if it performs the named action or denotes the named condition when it is LOW or 0. A signal is said to be asserted when it is at its active level.

8 Active Levels For Pins ENABLE DO MY THING ENABLE DO MY THING (a) Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e (b)

9 Buses Collection of two or more related signal lines. Microprocessor A A A A A A0 A A A A A A A A A A0 ADDR ADDR ADDR ADDR ADDR ADDR0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR0 ADDR ADDR ADDR ADDR ADDR ADDR0 ADDR ADDR ADDR[:0] LA LA LA LA LA LA0 LA LA LA[:0] ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR0 LA LA LA LA LA LA LA LA0 RDY READY ALE D D D D D D D D0 MEMIO READ WRITE ALE DATA DATA DATA DATA DATA DATA DATA DATA0 MIO RD_L WR_L ALE DATA[:0] DATA DATA DATA DATA DATA DATA DATA DATA0 RD_L WR_L DB DB DB DB DB DB DB DB0 Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e DB[:0] CONTROL,

10 Timing Diagrams Illustrate the logical behavior of the signals in a digital circuit as a function of time. Causality: which input transition causes which output transition. Propagation delay: the time it takes for a change at the input to produce a change at the output. Note that propagation delays when outputs change from LOW to HIGH may differ from when they change from HIGH to LOW.

11 Timing Diagrams (b) GO READY trdy trdy DAT tdat tdat (a) (c) GO GO READY READY ENB DAT trdymin trdymax DAT Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e tdatmin tdatmax

12 Decoders A decoder is a multiple-input multiple-output logic circuit that converts coded inputs into coded outputs, where the inputs and outputs codes are different. Decoder input code word enable inputs map output code word Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

13 Decoders Generally the input code has fewer bits than the output codes. In a one-to-one mapping each input code word produces a different output code word. Most commonly used codes: For input: The n-bit binary code. For output: The -out-of-m code.

14 Binary Decoder Binary decoder: The most common decoder. n-to- n. The input code is the n-bit binary code. The output code is the -out-ofm code.

15 Binary Decoder Table - Truth table for a -to- binary decoder. Inputs Outputs EN I I0 Y Y Y Y0 0 x x I0 I0 I I EN I0 Y0 I0 I -to- decoder EN (a) Y0 Y Y Y I EN (b) Y Y Y

16 Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e Binary Decoder Table - Truth table for onehalf of a x dual -to- decoder. Inputs Outputs G_L B A Y_L Y_L Y_L Y0_L x x G_L A B () () () () () () () Y0_L Y_L Y_L Y_L x G Y0 Y A B Y Y G A B Y0 Y Y Y 0 (a) G_L A B () () () () () (0) () Y0_L Y_L Y_L Y_L (b) Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e / x G A B (c) Y0 Y Y Y / x / x (a) G A B Y0 Y Y Y (b) G A B Y0 Y Y Y

17 Binary Decoder Table - Truth table for a x -to- decoder. Inputs Outputs G GA_L GB_L C B A Y_L Y_L Y_L Y_L Y_L Y_L Y_L Y0_L 0 x x x x x x x x x x x x x x x (a) G () GA_L () GB_L () () () () () Y0_L Y_L Y_L Y_L (b) x Y0 G Y GA Y GB Y Y A Y B Y C Y 0 () Y_L A () (0) Y_L B () C () () () Y_L Y_L Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

18 Cascading Binary Decoders N0 N N N +V R x Y0 G Y GA Y GB Y Y A Y B Y C Y 0 DEC0_L DEC_L DEC_L DEC_L DEC_L DEC_L DEC_L DEC_L EN_L U x G GA GB A B C Y0 Y Y Y Y Y Y Y 0 DEC_L DEC_L DEC0_L DEC_L DEC_L DEC_L DEC_L DEC_L Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e U

19 Cascading Binary Decoders x GA G GB Y0 Y Y Y B A C Y Y Y Y x GA G GB Y0 Y Y Y B A C Y Y Y Y DEC0_L DEC_L DEC_L DEC_L DEC_L DEC_L DEC0_L DEC_L DEC_L DEC_L DEC_L DEC_L DEC_L DEC_L DEC_L DEC_L N0 N N N EN_L N EN_L EN x GA G GB Y0 Y Y Y B A C Y Y Y Y DEC_L DEC_L DEC0_L DEC_L DEC_L DEC_L DEC_L DEC_L x GA G GB Y0 Y Y Y B A C Y Y Y Y DEC_L DEC_L DEC_L DEC_L DEC0_L DEC_L DEC_L DEC_L / x A G B Y0 Y Y Y EN0X_L ENX_L ENX_L ENX_L U U U U U Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

20 Seven Segment Decoders a Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e e f g c b d (a) (b) Table - Truth table for a x seven-segment decoder. Inputs Outputs BI_L D C B A a b c d e f g 0 x x x x

21 Seven Segment Decoders (a) () a Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e (b) x (0) b BI a b 0 A c B d C e D f g () c () d BI_L () () e A () B () () f C () () g D ()

22 Encoders Reverses what a decoder does. If a device s output code word has fewer bits than the input code word then the device is usually called an encoder. The simplest encoder is the binary encoder or the n -to-n encoder.

23 Encoders Inputs Outputs I0 I I I I I I I Y Y Y Binary encoder Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e Y0 I0 (a) n inputs I0 I I Y0 Y I n Y n n outputs (b) I I I I I I I Y Y

24 Priority Encoders Priority encoders assigns priority to the input lines, so that when multiple lines are asserted at the same time, the encoder will produce the highest priority requestor. Inputs Outputs I0 I I I I I I I Y Y Y X X X X X X X X X X X X X X X X X X X X X 0 0 X X X X X X X

25 Priority Encoders Table - Truth table for a x -input priority encoder. Inputs Outputs EI_L I0_L I_L I_L I_L I_L I_L I_L I_L A_L A_L A0_L GS_L EO_L x x x x x x x x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x I0_L (0) () EO_L I_L () () GS_L I_L () I_L () () A0_L I_L () Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e I_L () () A_L I_L () I_L () () A_L EI_L ()

26 Cascading Binary Encoders I I I I I I I I0 A A A0 GS EO EI 0 x I I I I I I I I0 A A A0 GS EO EI 0 x I I I I I I I I0 A A A0 GS EO EI 0 x x REQ_L REQ0_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ0_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ0_L REQ_L REQ_L REQ0_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L REQ_L I I I I I I I I0 A A A0 GS EO EI 0 RGS RA0 RA RA RA RA U U U U GA_L GA_L GA0_L GGS_L GEO_L GA_L GA_L GA0_L GGS_L GEO_L GA_L GA_L GA0_L GGS_L GEO_L G0A_L G0A_L G0A0_L G0GS_L x00 U x00 U x0 U 0 x0 U x0 U 0 x0 U Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

27 Tri-State Devices Devices whose outputs may be in one of three states, 0,, or Hi-Z (high impedance). These devices have an extra input which is used to control if the output is floating (Hi-Z) or if it is behaving normally (page ). (a) (b) (c) (d) Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e Inputs Output EN A Y X Hi-Z

28 Tri-State Devices -bit party line P Q x EN EN_L EN_L SSRC0 SSRC SSRC G GA GB A B C Y0 Y Y Y Y Y Y Y 0 SELP_L SELQ_L SELR_L SELS_L SELT_L SELU_L SELV_L SELW_L R S T SDATA U V W SSRC[0] 0 EN EN_L, EN_L SDATA W P Q R S max(t plzmax, t phzmax ) min(t pzlmin, t pzhmin ) dead time

29 Tri-State Devices G G x G_L G_L () () (b) A A A A A A A A Y Y Y Y Y Y Y Y A A A A () () () () () () () () Y Y Y Y A () () Y Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e A A () () () () Y Y (a) A () () Y

30 Tri-State Devices x DIR G B B B (b) (a) A A A A A A A A B B B B B () B G_L () DIR () A () () B A () () B A () () B A () () B A () () B A () () B A () () B A ()

31 Tri-State Devices Microprocessor x READ INSEL G G Input Port DB0 DB DB DB DB DB DB DB D0 D D D D D D D INSEL INSEL User Inputs A A A A A A A A Y Y Y Y Y Y Y Y DB0 DB DB DB DB DB DB DB x G G Input Port Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e User Inputs A A A A A A A A Y Y Y Y Y Y Y Y DB0 DB DB DB DB DB DB DB DB[0:]

32 Multiplexers (b) D0 D Y Dn (a) enable select s multiplexer EN SEL D0 D Dn Y n data sources b b b D0 D Dn Y b data output bd0 bd bdn by SEL EN Digital switch (page ). A multiplexer with n data sources requires s = log n select lines. Commercially available MUX have n=,,, or. EN enables the output.

33 Multiplexers Inputs Output EN S D0 D Y 0 X X X Inputs Output EN S Y 0 X 0 0 D0 D Y = EN S D0 + EN S D

34 Multiplexers iy = n j= 0 EN M j id j (b) D0 D Y Dn (a) enable select s multiplexer EN SEL D0 D Dn Y n data sources b b b D0 D Dn Y b data output bd0 bd bdn by SEL EN General logic equation for a multiplexer is show above.

35 Multiplexers Table - Truth table for a x -input, -bit multiplexer. Inputs Outputs EN_L C B A Y Y_L x x x D0 D D D D D 0 0 D D D D 0 0 D D 0 0 D D 0 D D EN_L () D0 () A A B B C C D () D () D () () Y D () () Y_L D () x D D A B () () () (0) 0 EN A B C D0 D D D D D D D Y Y C () (a) (b)

36 Multiplexers Inputs Outputs G_L S Y Y Y Y x A A A A 0 B B B B Table - Truth table for a x -input, -bit multiplexer. (a) G_L S A B () () () () () Y (b) 0 x G S A Y B A Y B A Y B A Y B A () B () () Y A B A () (0) () () Y Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e B () () Y

37 Multiplexers Inputs Outputs G_L G_L B A Y Y C0 C C C C C 0 0 C C C C C 0 0 C C C C 0 0 C x x 0 0 Table - Truth table for a x -input, -bit multiplexer. (a) A () B () G_L () Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e C0 () C () () Y C () C () G_L C0 C C C () (0) () () () () Y (b) 0 x A B G C0 C Y C C G C0 C Y C C

38 Multiplexers x D0 D D D D D D D EN Y Y A B C 0 / x A G B Y0 Y Y Y XEN_L XA XA XA0 XA XA X0 X X X X X X X EN_L EN_L EN_L EN0_L x D0 D D D D D D D EN Y Y A B C 0 X0 X X X X X X X x D0 D D D D D D D EN Y Y A B C 0 x D0 D D D D D D D EN Y Y A B C 0 X X X X X0 X X X X X X X X X X X0 / x0 XOUT XO0_L XO_L XO_L XO_L U U U U U U Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

39 Demultiplexers Digital switch (page 0). A demultiplexer with n data outputs requires s = log n select lines. (a) SRCA multiplexer demultiplexer DSTA SRCB SRCC BUS DSTB DSTC SRCZ DSTZ SRCSEL DSTSEL (b) SRCA Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e DSTA SRCB SRCC MUX BUS DMUX DSTB DSTC SRCZ DSTZ SRCSEL DSTSEL

40 Demultiplexers (a) -to- decoder (b) / x SRCDATA G Y0 DST0DATA SRCDATA_L G Y0 DST0DATA_L Y DSTDATA Y DSTDATA_L DSTSEL0 A Y DSTDATA DSTSEL0 A Y DSTDATA_L DSTSEL B Y DSTDATA DSTSEL B Y DSTDATA_L Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e Table - Truth table for onehalf of a x dual -to- decoder. Inputs Outputs G_L B A Y_L Y_L Y_L Y0_L x x

41 Exclusive-Or Gates An exclusive-or (XOR) gate is a input device whose output is if exactly one of its inputs is (page 0). An exclusive-nor (XNOR) or equivalence is just the opposite. (a) (b) Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

42 Exclusive-Or Gates X Y X Y (XOR) (X Y) (XNOR) Table - Truth table for XOR and XNOR functions. Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e (a) X F = X Y Y (b) X F = X Y Y

43 Parity Circuits Parity detectors are circuits that detects if the numbers of ones at its input is odd or even. Used to detect errors during the transmission of binary information, by using a parity bit. Parity bit is an extra bit included with the binary message to make the number of ones in the message either even or odd.

44 Parity Circuits (a) I I I I IN ODD (b) I I I I ODD IM IN Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

45 Parity Circuits x0 (a) A B C () () (0) Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e (b) 0 A B C D E F G H I EVEN ODD D E F () () () () EVEN G H I () () () () ODD

46 Parity Circuits x0 D E F G H I EVEN ODD A B C 0 D0 D D D D D D D U U U U D[0:] RP Memory Chips DIN DIN DIN DIN DIN PIN DIN0 READ WRITE DIN DIN DOUT DOUT DOUT DOUT DOUT POUT DOUT0 DOUT DOUT D0 D D D D D D D D D D0 D D D D D x G G Y Y Y A A A A A A A A Y Y Y Y Y DO0 DO DO DO DO DO DO DO LS0 U x0 x0 ERROR RD_L PI PO RD WR Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

47 Comparators Comparators are circuits that compare two binary words and indicates whether they are equal or not equal. (a) A0 B0 / x U DIFF (b) A0 B0 A B A B A B 0 x U U U U DIFF0 DIFF DIFF DIFF x0 U x0 U DF0_L DF_L x00 U DIFF Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

48 Comparators primary inputs PI 0 cascading input PI cascading output PI n PI PI PI C 0 C C C n C n CI module CO CI module CO CI module CO PO PO PO boundary inputs Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e boundary outputs PO 0 PO PO n primary outputs (b) X0 Y0 X Y X Y X(N ) Y(N ) X Y CMP EQI EQO EQ X Y CMP EQI EQO EQ X Y CMP EQI EQO EQ EQ(N ) X Y CMP EQI EQO EQN (a) X Y CMP EQO Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e EQI

49 Comparators Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e () PEQQ_L Q0 P0 () () Q P () () Q P () () Q P () () () PGTQ_L Q () P () Q () P () Q () P () Q () P ()

50 Comparators x 0 ALTBIN AEQBIN AGTBIN A0 B0 A B A B A B ALTBOUT AEQBOUT AGTBOUT Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e + V R x x x XD0 YD0 XD YD XD YD XD YD 0 ALTBIN AEQBIN AGTBIN A0 B0 A B A B A B ALTBOUT AEQBOUT AGTBOUT XLTY XLTY XLTY ALTBIN ALTBOUT ALTBIN ALTBOUT XEQY XEQY XEQY AEQBIN AEQBOUT AEQBIN AEQBOUT XGTY XGTY XGTY AGTBIN AGTBOUT AGTBIN AGTBOUT XD 0 XD 0 A0 A0 YD B0 YD B0 XD A XD A YD B YD B XD A XD0 A YD B YD0 B XD A XD A YD B YD B XD[0] YD[0] Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

51 Adders Half adder adds two one bit operands and produces a two bit sum (page ). HS = X Y CO = XY X Y CO HS

52 Adders Full adder adds three one bit operands and produces a two bit sum. S = X Y CIN COUT = XY + X CIN + Y CIN CIN X Y COUT S

53 Adders full adder X Y CIN S (b) X Y CIN S COUT COUT X Y (a) Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e (c) COUT S CIN x y x y x y x 0 y 0 X Y X Y X Y X Y c c c c COUT CIN COUT CIN COUT CIN COUT CIN c 0 S S S S s s s s 0 Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

54 PLDs I I I I Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e P P P P P P O O O I I I I P P P P P P O O O Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

55 PLDs Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e V CC floating gate nonfloating gate active-low input lines active-high AND lines

56 PLDs I I I I P P P P P P O O O Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

57 PALL I () () O I () I () 0 () IO I () 0 () IO I () 0 () IO I () () IO I () 0 () IO I () 0 () IO I () 0 () () O I0 Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

58 GALVC I () I () 0 () O I () 0 () IO I () 0 () IO I () 0 () IO I () () IO I () 0 () IO I () 0 () IO I () 0 () () O I0 Copyright 000 by Prentice Hall, Inc. Digital Design Principles and Practices, /e

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