An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm G. Mohan 1 K. Rambabu 2

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1 IJSRD - Intrntionl Journl or Sintii Rsrh & Dvlopmnt Vol., Issu, ISSN (onlin): - An Eiint FPGA Implmnttion o th Avn Enryption Stnr Algorithm G. Mohn K. Rmu M.Th Assistnt Prossor Dprtmnt o Eltronis n ommunition Enginring, Brillint Institut o Enginring n thnology Astrt A propos FPGA-s implmnttion o th Avn Enryption Stnr (AES) lgorithm is prsnt in this ppr. This implmnttion is ompr with othr works to show th iiny. Th sign uss n itrtiv looping pproh with lok n ky siz o its, lookup tl implmnttion o S -ox. This givs low omplxity rhittur n sily hivs low ltny s wll s high throughput. Simultion rsults, prormn rsults r prsnt n ompr with prvious rport signs. Ky wors: AES, FPGA, nryption, ryption, Rijnl, lok iphr I. INTRODUTION For long tim, th Dt Enryption Stnr (DES) ws onsir s stnr or th symmtri ky nryption. DES hs ky lngth o its. Howvr, this ky lngth is urrntly onsir smll n n sily rokn. For this rson, th Ntionl Institut o Stnrs n Thnology (NIST) opn orml ll or lgorithms in Sptmr. A group o itn AES nit lgorithms wr nnoun in August. Nxt, ll lgorithms wr sujt to ssssmnt pross prorm y vrious groups o ryptogrphi rsrhrs ll ovr th worl. In August, NIST slt iv lgorithms: Mrs, R, Rijnl, Srpnt n Twoish s th inl omptitors. Ths lgorithms wr sujt to urthr nlysis prior to th sltion o th st lgorithm or th AES. Finlly, on Otor,, NIST nnoun tht th Rijnl lgorithm ws th winnr. Rijnl n spii with ky n lok sizs in ny multipl o its, with minimum o its n mximum o its. Thror, th prolm o rking th ky oms mor iiult []. In ryptogrphy, th AES is lso known s Rijnl []. AES hs ix lok siz o its n ky siz o, or its. Th AES lgorithm n iintly implmnt y hrwr n sotwr. Sotwr implmnttions ost th smllst rsours, ut thy or limit physil surity n th slowst pross. Bsis, growing rquirmnts or high sp, high volum sur ommunitions omin with physil surity, hrwr implmnttion o ryptogrphy tks pl. An FPGA implmnttion is n intrmit solution twn gnrl purpos prossors (GPPs) n pplition spii intgrt iruits (ASIs). It hs vntgs ovr oth GPPs n ASIs. It provis str hrwr solution thn GPP. Also, it hs wir ppliility thn ASIs sin its oniguring sotwr mks us o th ro rng o untionlity support y th ronigurl vi []. This ppr ls with n FPGA implmnttion o n AES nryptor/ryptor using n itrtiv looping pproh with lok n ky siz o its. Bsis, our sign uss th lookup- tl implmnttion o S-ox. This mtho givs vry low omplxity rhittur n is sily oprt to hiv low ltny s wll s high throughput. Orgniztion o th rst o this ppr is s ollows. Stion provis ri ovrviw o AES lgorithm. Dsign o AES s on FPGA implmnttion is prsnt in stion. Stion givs simultion rsults ollow y th omprisons with othr works in stion. Finlly, stion givs th onlusion o this work. II. DESRIPTION OF AES ALGORITHM Th AES lgorithm is symmtri lok iphr tht n nrypt n rypt inormtion. Enryption onvrts t to n unintlligil orm ll iphr-txt. Dryption o th iphr-txt onvrts th t k into its originl orm, whih is ll plin-txt. A. AES nryption Th AES lgorithm oprts on -it lok o t n xut Nr - loop tims. A loop is ll roun n th numr o itrtions o loop, Nr, n,, or pning on th ky lngth. Th ky lngth is, or its in lngth rsptivly. Th irst n lst rouns ir rom othr rouns in tht thr is n itionl ARounKy trnsormtion t th ginning o th irst roun n no Mixoulmns trnsormtion is prorm in th lst roun. In this ppr, w us th ky lngth o its (AES-) s mol or gnrl xplntion. An outlin o AES nryption is givn in Fig.. B. SuByts Trnsormtion Th SuByts trnsormtion is non-linr yt sustitution, oprting on h o th stt yts inpnntly. Th SuByts trnsormtion is on using on-pr-lult sustitution tl ll S-ox. Tht S-ox tl ontins numrs (rom to ) n thir orrsponing rsulting vlus. Mor tils o th mtho o lulting th S-ox tl rrs to []. In this sign, w us look-up tl s shown in Tl I. This is mor iint mtho thn irtly implmnting th multiplitiv invrs oprtion ollow y in trnsormtion. This pproh vois omplxity o hrwr plmnttion n hs th signiint vntg o prorming th S-ox omputtion in singl lok yl, thus ruing th ltny. All rights rsrv y

2 An Eiint FPGA Implmnttion o th Avn Enryption Stnr Algorithm (IJSRD/Vol. /Issu //) All rights rsrv y Tl S-Box Tl Y B A X E. ShitRows Trnsormtion In ShitRows trnsormtion, th rows o th stt r ylilly lt shit ovr irnt osts. Row is not shit; row is shit on yt to th lt; row is shit two yts to th lt n row is shit thr yts to th lt. D. Mixolumns Trnsormtion In Mixolumns trnsormtion, th olumns o th stt r onsir s polynomils ovr GF ( ) n multipli y moulo x + with ix polynomil (x), givn y: (x)={}x + {}x + {}x + {}. E. ARounKy Trnsormtion In th ARounKy trnsormtion, Roun Ky is to th Stt - rsult rom th oprtion o th Mixolumns trnsormtion - y simpl itwis XOR oprtion. Th RounKy o h roun is riv rom th min ky using th KyExpnsion lgorithm []. Th nryption/ryption lgorithm ns lvn -it RounKy, whih r not RounKy[] RounKy[] (th irst RounKy [] is th min ky). B. AES ryption Dryption is rvrs o nryption whih invrs roun trnsormtions to omputs out th originl plintxt o n nrypt iphr-txt in rvrs orr. Th roun trnsormtion o ryption uss th untions ARounKy, InvMixolumns, InvShitRows, n InvSuByts sussivly. F. ARounKy ARounKy is its own invrs untion us th XOR untion is its own invrs. Th roun kys hv to slt in rvrs orr. Th sription o th othr trnsormtions will givn s ollows. G. InvShitRows Trnsormtion InvShitRows xtly untions th sm s ShitRows, only in th opposit irtion. Th irst row is not shit, whil th son, thir n ourth rows r shit right y on, two n thr yts rsptivly. H. InvSuByts trnsormtion Th InvSuByts trnsormtion is on using on-prlult sustitution tl ll InvS-ox. Tht InvS-ox tl ontins numrs (rom to ) n thir orrsponing vlus. InvS-ox is prsnt in Tl II. Tl Invs-Box Tl Y

3 An Eiint FPGA Implmnttion o th Avn Enryption Stnr Algorithm (IJSRD/Vol. /Issu //) All rights rsrv y X I. InvMixolumns Trnsormtion In th InvMixolumns trnsormtion, th polynomils o gr lss thn ovr GF( ), whih oiints r th lmnts in th olumns o th stt, r multipli moulo (x + ) y ix polynomil (x) = {B}x + {D}x + {}x + {E}, whr {B}, {D}; {}, {E} not hximl vlus. In th nxt stion, sription o th propos sign s on FPGA implmnttion o AES nryption/ryption untion is til. III. FPGA IMPLEMENTATION OF AES ALGORITHM Fig. shows th til sign o AES or s on FPGA implmnttion, whr th ontrol signls r sri in Tl III. Th totl sign hs pins. It rquirs th txt_in, txt_out n ky whih hv its lngth. An th ontrol signls using to ontrol th propr oprtions o th or r lk, rst_n, writ, irtion, on n nl pins Th Ky lok los kys n omins with Ky Roun lok to prorm Ky Expnsion trnsormtion, n gnrts propr Rounkys unr th ontrol signls rom th ontrollr lok. ontrollr lok tks writ signl, irtion signl, n nl signl rom outsi n gnrts ll th ontrol signls or th whol systm. TABL E III. ONTROL SIGNALS OF AES ORE I/O Pin Pin nm num r Pin sription port (it) lk I hip lok rst_n I lr ll signl n t writ I : Writ ky n txt_in irtio n I : Enryption : Dryption nl I : Enl AES or : Disl AES or ky I Ky t txt_in I Plintxt/iphrtxt t on O :Enryption/Dryptio n is omplt txt_out O iphrtxt/ Plintxt t Th plin txt (txt _in) n ky is lo only whn th writ signl mks low-high-low trnsition (silly puls). Th pross is going to omplt whn th on signl is puls tr som lok yls rom th writ signl gos low. Th on signl tivs only in on lok yl. Eh roun ky s wll s roun is omplt in on lok yl. Howvr, th roun ky is inish or th roun is lult y on lok yl. Hn, omining with on lok yl or rgistring th input, totl lok yl n or prossing -it t is

4 An Eiint FPGA Implmnttion o th Avn Enryption Stnr Algorithm (IJSRD/Vol. /Issu //) loks in nryption mo. In ryption, lvn roun kys must omplt or th irst roun is lult. Bus th lst roun ky is us in th irst roun pross, it tks lok yls to omplt. With using th ov itrtiv looping pproh, miniml numr o lok yls rquir prorming nryption/ryption or h t lok o -it IV. SIMULATION RESULTS Th sign hs n o y Vrilog HDL. All th rsults r synthsiz n simult sing on th Qutus., th Mol Sim Altr. n EPKB vi Th rsults o simulting th nryption/ryption lgorithm rom th MolSim simultor r shown in Fig. n Fig. throughput n r. Thror it llows us to pross t in ommunition pplitions rquiring high surity ommunition with low ltny, high throughput n smll r. Bsis, th sign is ompr with nothr implmnttion using Xilinx hip [] whih uss th similr rhittur with our sign, ut it rquirs highr ltny. Bus Altr n Xilinx hv th irnt hip rhitturs,omprison twn us n [] nnot on in th othr ritri o mmory, throughput n r. Tl Iv. omprison In Fpg Implmnttions O Th As ALGORITHM Dsigns Our sign [] [] [] FPGA Vnor FPGA hip Altr Altr Altr Xilinx APEXK APEXK APEXK (Mix Vrsion) (Mix Vrsion) XV Fig. : Timing simultion o AES nryption lgorithm Mmory Enryption - Dryption - Fig. : Timing simultion o AES ryption lgorithm Thy r showing low ltny. Hn, th prtil rsults r in orn to thortil pritions n stisy th nryption n ryption mthoology. To tst th systm, tst nh is us. Th tst nh pplis nryption/ryption input puls to triggr th systm. Th output rsult o th nryption ws oun urtly tr lok yls rom th strting o nryption pross. So th ltny o nryption is only lok yls. Similrly, th ltny o ryption is lok yls. V. OMPARISONS In this stion, th rsults otin y our sign, n omprison twn our rsults n othr quivlnt implmnttions is givn n isuss. Our sign or AES -it nryption/ryption lgorithm ws synthsiz, implmnt y Altr tools. Tl IV summrizs th hrwr rsours rquir y min uiling loks n givs til omprisons with th othr signs [], []. onsiring th omprison in tl IV, our sign is oun to mor iint in trms o ltny, Ltny Enryption (lok yls) Dryption Throughput Enryption - (Mps) Dryption - Ar Enryption - (Ls) Dryption - Th sign is tst with th smpl vtors provi y FIPS []. Th lgorithm hivs low ltny n th throughput rhs th vlu o Mit/s or nryption n Mit/s or ryption. VI. ONLUSIONS Th Avn Enryption Stnr lgorithm is symmtri lok iphr tht n pross t loks o its through th us o iphr kys with lngths o,, n its. An iint FPGA implmnttion o it lok n it ky AES lgorithm hs n prsnt in this ppr. Th sign is implmnt on Altr using APEXK FPGA whih is s on high prormn rhittur. Th propos sign is implmnt s on th itrtiv pproh or ryptogrphi lgorithms. Our rhittur is oun to ttr in trms o ltny, throughput s wll s r. Th sign is tst with th smpl vtors provi y FIPS []. Th lgorithm hivs low ltny n th throughput rhs th vlu o Mit/s or nryption n Mit/s or ryption. All rights rsrv y

5 An Eiint FPGA Implmnttion o th Avn Enryption Stnr Algorithm (IJSRD/Vol. /Issu //) REFERENE [] Dmn J., n Rijmn V, "Th Dsign o Rijnl: AES-th Avn Enryption Stnr", Springr- Vrlg, [] FIPS, Avn Enryption Stnr (AES), Novmr,. [] Tssir, R., n Burlson, W., Ronigurl omputing or igitl signl prossing: survy, J.VLSI Signl Pross.,,, (-), pp.-. [] Ahm, N.; Hsn, R.; Jui, W.M; Dsign o AES S-Box using omintionl logi optimiztion, IEEE Symposium on Inustril Eltronis & Applitions (ISIEA), pp. -,. [] Alx Pnto, Mrlo Brlos, Riro Ris, An IP o n Avn Enryption Stnr or Altr Dvis, SBI, pp. -, Porto Algr, Brzil, n Sptmr. [] Mr. Atul M. Borkr, Dr. R. V. Kshirsgr n Mrs. M. V. Vywhr, FPGA Implmnttion o AES Algorithm, Intrntionl onrn on Eltronis omputr Thnology (IET), pp. -, r. All rights rsrv y