New challenges on Independent Gate FinFET Transistor Network Generation

Transcription

1 Nw hllngs on Inpnnt Gt FinFET Trnsistor Ntwork Gnrtion Viniius N. Possni, Anré I. Ris, Rnto P. Ris, Flip S. Mrqus, Lomr S. Ros Junior Thnology Dvlopmnt Cntr, Frl Univrsity o Plots, Plots, Brzil Institut o Inormtis, Frl Univrsity o Rio Grn o Sul, Porto Algr, Brzil {vnpossni, lipm, lomrjr}@in.upl.u.r {nris, rpris}@in.urgs.r Astrt This ppr shows tht oul gt vis, lik inpnnt-gt (IG) FinFETs, hv introu nw hllngs in th trnsistor ntwork gnrtion stp uring th logi synthsis. Suh nw prigm points tht just to minimiz th mximum numr o litrls in Booln xprssion is not nough to hiv optimiz trnsistor ntworks. This wy, tritionl toriztion mthos or grph-s optimiztions my not usul to gnrt ntworks or oul gt vis. In this sns, this ppr prsnts two iint ltrntivs to xplor th nits o suh vis uring th trnsistor ntwork gnrtion. Th irst on monstrts two wys or toring Booln xprssions whih ontriut to rs th trnsistor ount. Through th propos toriztion, it is possil to hiv mor optimiz trnsistor rrngmnts ompr to othr toriztion thniqus vill in th litrtur. Th son ltrntiv propos hrin is grph-s mtho l to in promising rrngmnts to xplor th sprt gts o h IG FinFET. Th xprimnts monstrt tht th propos mtho n ru th numr o IG FinFETs ompr to th tritionl mthos o trnsistor ntwork gnrtion. Kywors FinFET; logi synthsis; toriztion; grph thory; trnsistor ntwork; logi gt; EDA. I. INTRODUCTION Although th ontinuous CMOS trnsistor sling hs n proviing prormn improvmnts o igitl iruits, its thnology pross s grt hllngs u to th vis shrinking n th unmntl mtrils limits [1]. Sin 2001, th Intrntionl Thnology Romp or Smionutors (ITRS) hs point th FinFET [2] n th UTB-SOI [3] s promising thnologis or trnsistor sling yon CMOS limits. In th lst yrs, irnt solutions o oul-gt (DG) vis wr propos [4-6]. In this work w hv spil intrst or DG FinFET vis, whih n sign in two irnt wys oring to th gt onigurtion. On possiility is to ining th two gts yiling singl-gt (SG) FinFET, s illustrt in Fig. 1(). This onigurtion is lso known s short-gt FinFET. Th othr on is to uil two inpnnt-gts (IG) FinFET, in suh wy tht h gt n ontroll y irnt input signl, s illustrt in Fig. 1(). Ths irnt onigurtions hv llow rih projt sp n introu nw hllngs to xplor oth in logi n physil synthsis. () () Fig. 1. In (), SG FinFET trnsistor n in () IG FinFET trnsistor. Looking or th IG FinFET strutur in Fig. 1(), it is possil to intiy tht prlll rrngmnt, i.. ( + ), n implmnt using th sprt gts o th trnsistor. Thus, rsrhrs hv osrv th possiility to mrg prlll trnsistors in IG FinFETs n ru th trnsistor ount in logi gts [7-9]. Furthrmor, som uthors introu th possiility o mrg sris trnsistors, i.. (. ), in n IG FinFET. It is on s on th thrshol work untion, whih will turn on th trnsistor (I on ) i n only i oth gts r in th on stt [10-12]. Othrwis, th urrnt is low nough to kp th trnsistor in th o stt (I o ). This wy, th mrg o sris n prlll trnsistors is powrul strtgy to rs th trnsistor ount in logi gts. In th rmining o this work th SG FinFET, th IG FinFET (prlll) n th IG FinFET (sris) will rprsnt y th nottions illustrt in Fig. 2(), Fig. 2() n Fig. 2(), rsptivly. It is importnt to mntion tht th ntworks n implmnt using only SG FinFETs or omining oth SG n IG FinFETs. gt sour rin gt1 sour rin gt2 () () () Fig 2. Dirnt FinFET rprsnttions: in () SG FinFET, in () IG FinFET (prlll) n in () IG FinFET (sris). Consiring th nw possiilitis provi y th FinFET thnology, svrl works vill in th litrtur r onrn to us it to sign si gts n othr w irnt Booln untions [7-12]. Rntly, som works hv prsnt novl solutions to implmnt lmntry gts s AND, NAND, OR n NOR, y mrging sris n prlll trnsistors using IG FinFETs [7-10][12]. Fig. 3() shows nw implmnttion or th 2-inputs NAND n Fig. 3() shows nw implmnttion or th 2-inputs NOR. Noti tht, h logi gt n implmnt using only two trnsistors. Morovr, som works hv lso synthsiz nhmrks iruits using suh novl gts s ll lirry.

2 Th xprimnts hv monstrt tht rs in th trnsistor ount through IG FinFETs is n iint wy to sv r n powr in igitl sign [9][12]. VDD GND () () Fig. 3. In (), 2-inputs NAND n in () 2-inputs NOR, otin y mrging sris trnsistors n prlll trnsistors in IG FinFETs. Thr r mny irnt mthos vill in th litrtur to rs trnsistor ount n to gnrt optimiz ntworks to implmnt logi gts [13-17]. Suh mthos r l to livr stistory solutions or singl gt vis, i.. onvntionl CMOS or SG FinFET. In gnrl, ths mthos im to minimizing th mximum numr o litrls in Booln xprssion y pplying toriztion [13-14] or grph-s optimiztions [15-17]. Tritionlly, minimiz th numr o litrls ls to ru trnsistor ntwork. It ours us thr is irt rltion twn litrls n trnsistors. In othr wors, h litrl in tor xprssion n irtly mpp to trnsistor in ntwork. This rltion lso hppns whn th litrls, rprsnt y gs in grph-s solution, r mpp to trnsistors in ntwork. Howvr, s prviously isuss, nw prigm hs n introu y mrging sris n prlll trnsistors using IG FinFETs. It impts in how to gnrt iint trnsistor rrngmnts uring th logi synthsis. Thus, whn th gol is to rs th trnsistor ount y using IG FinFETs, minimiz th numr o litrls in givn Booln xprssion my not riv to th st solution. It hppns us som runnt litrls, in tor xprssion or in grph-s solution, n ontriut to hiv th st sris n prlll mrging n to rs th totl numr o FinFETs in ntwork. Thror, s oth th onvntionl toriztion mthos n th grph-s thniqus im to minimiz th litrl ount, ths mthos [13-17] my not th st ltrntiv to gnrt IG FinFET trnsistor ntworks. Consiring tht th mrg o sris n prlll trnsistors in IG FinFETs hs om sil wy to ru r n powr onsumption in VLSI sign, it is xtrmly importnt to trmin n utomt mtho to in iint IG FinFET rrngmnts. To th st o our knowlg, thr is no work tht prsnts n utomt mtho l to xplor th potntil o DG vis. In this sns, this work prsnts n nlysis out th nw hllngs to implmnt Booln untions using IG FinFETs. This ppr lso VDD GND isusss how this nw prigm ts th implmnttion o Booln untions rom spil lsss lik r-on (RO) [18] n r-polrity-on (RPO) [19]. W r prsnting two ltrntiv wys or toring Booln xprssions, whih r l to livr optimiz IG FinFET rrngmnts ompos o wr trnsistors thn th toriztions prsnt in [12]. Finlly, w propos n ltrntiv mtho to utomtilly gnrt optimiz IG FinFET trnsistor ntworks. Th rmining o this ppr is orgniz s ollows. Stion II prsnts mor til nlysis out th nw hllngs n possiilitis tht th IG FinFET thnology provis. Stion III prsnts th propos ltrntivs or toring Booln xprssions. Th propos mtho to gnrt IG FinFET trnsistor ntworks is prsnt in Stion IV. Som xprimntl rsults n omprison r prsnt in Stion V. Finlly, onlusions r outlin in Stion VI. II. NEW CHALLENGES AND POSSIBILITIES This stion prsnts som xmpls tht monstrt how th mrg o sris n prlll trnsistors using IG FinFETs impts in th trnsistor ntwork gnrtion. Exmpl 1: Th irst intrsting point is tht two irnt tor orms, whih rprsnt th sm logi untion n r ompos o th sm numr o litrls, n rsult in trnsistor ntworks with irnt numr o vis. Thus, in orr to monstrt tht, lt us onsir th tor orms rprsnt y Eqution (1) n Eqution (2) in Tl I, oth ompos o 8 litrls. Whn onsiring singl gt vis, i.. onvntionl CMOS or SG FinFETs, ths tor orms n us to uil two irnt trnsistor ntworks, oth ompos o 8 vis. Howvr, whn onsiring th possiility to mrg sris n prlll trnsistor in IG FinFETs, it is possil to sv 2 trnsistors y using th Eqution (2) inst o th Eqution (1). Th trnsistor ntwork otin rom Eqution (1) is illustrts in Fig. 4() n th mor optimiz rrngmnt, otin rom Eqution (2), is illustrt in Fig. 4(). As n sn, it is iiult to trmin th st qution to us i onsiring only th litrl ount s mtri.!!!! () () Fig. 4. In (), trnsistor ntwork otin rom Eqution (1) n in () th mor optimiz solution otin rom Eqution (2).!!!!

3 TABLE I SOME FACTORIZED EQUATIONS. Litrl Count Ftor Form Eqution 8 litrls = ( + (. ( + ))). (! + (!. (! +!))) (1) 8 litrls = ((!. ). ( + )) + ((.!). (! +!)) (2) 14 litrls g = (! + ((! +!). ( + ( + )))). ((.!) + ((! + ). ( + (!. ( +!))))) (3) 15 litrls g = ((!. ). ((!. ) + (.!))) + ((!.!). ((!.!) + (. ))) + (!. (. )) (4) Exmpl 2: This son xmpl monstrts tht minimizing th numr o litrls in Booln xprssion my not l to th minimum numr o IG FinFETs. Lt us onsir th logi untion g, whih n tor o two irnt wys s prsnt in Eqution (3) n Eqution (4) in Tl I. Ths two tor orms n us to uil trnsistor ntworks ompos o singl gt vis. In this s, th ntworks otin rom Eqution (3) n Eqution (4) r ompos o 14 n 15 trnsistors, rsptivly. As xpt, th ntwork otin rom Eqution (3) will sv on trnsistor ompr to th ntwork otin rom Eqution (4). On th othr hn, whn onsiring vis lik IG FinFETs to implmnt th untion g, w hv th opposit. Noti tht, through th Eqution (3) it is possil to uil ntwork ompos o 9 trnsistors, s shown in Fig. 5(). Howvr, through th Eqution (4), it is possil to uil n iint rrngmnt using only 8 trnsistors, s show in Fig. 5(). In, th st input qution or singl gt vis my not th st nit qution or inpnnt gts vis n vi vrs.!!!!!! ()!!!!! Exmpl 3: Whn th gol is to minimiz th trnsistor ount, th non-sris-prlll (NSP) rrngmnts r sil wy to o tht [17]. In gnrl, th grph-s thniqus r l to in NSP rrngmnts whil th toriztion mthos r limit to SP rrngmnts. Thus, whn onsiring singl gt vis, th NSP rrngmnts n rsult in ntwork with th sm numr o trnsistors or with wr trnsistors thn th srisprlll (SP) ountrprt. Howvr, whn onsiring th mrg o sris n prlll trnsistors using IG FinFETs, in som ss, th SP rrngmnts n rsult in ntwork with wr trnsistors thn th NSP solution. To monstrt n instn o this prolm, lt us onsir th Eqution (5). This qution n tor rsulting in n xprssion ompos o 7 litrls, s prsnt in Eqution (6). h =.. +!. +.. (5) h =. ((.) + (.)) + (!.) (6) Suh tor orm n us to uil SP trnsistor ntwork with 7 singl gt vis, s shown in Fig. 6(). Anothr ltrntiv is to pply grph-s thniqu ovr th Eqution (5), rsulting in NSP trnsistor ntwork omprising 6 singl gt vis, s shown in Fig. 6(). Noti tht, th NSP rrngmnt ontriuts to rs th trnsistor ount. Thus, in irst nlysis w n lim tht th NSP solution is ttr thn th SP solution, onsiring SG FinFETs.!!!!!! () Fig. 6. Two possil solutions to implmnt th logi untion h using SG FinFETs: in () SP ntwork otin rom Eqution (6) n in () NSP ntwork otin through grph s thniqu. () () Fig. 5. Two possil solutions to implmnt th logi untion g using IG FinFET (sris) n IG FinFET (prlll): in () ntwork otin rom Eqution (3) n in () ntwork otin rom Eqution (4). Howvr, onsiring IG FinFETs, th sris trnsistors o th SP ntwork illustrt in Fig. 6() n mrg rsulting in th ntwork illustrt in Fig. 7(). Similrly, y mrging trnsistors in th NSP ntwork illustrt in Fig. 6(), it is possil to hiv th ntwork illustrt in Fig. 7(). As n sn, th NSP ntwork rsults in 5

4 trnsistors whil th SP ntwork ns only 4 trnsistors to implmnt th untion h. Thus, w hv osrv tht, in som ss, th NSP onigurtion prohiits th mrg o trnsistors. () Fig. 7. Two possil solutions to implmnt th logi untion h using IG FinFETs: in () SP ntwork otin rom Eqution (6) n in () NSP ntwork otin through grph s thniqu. Exmpl 4: This xmpl monstrts tht in som ss, th NSP rrngmnts still ing th st solution to minimiz trnsistor ount. For instn, lt us onsir th Eqution (7). By pplying toriztion thniqu ovr this qution w otin tor orm ompos o 10 litrls, s prsnt in Eqution (8). z = (7) z =. ( + (..)) +. ((. ) + + ) (8) Suh tor orm n irtly mpp to ntwork ompos o 10 singl gt vis, s shown in Fig. 8(). Howvr, whn pplying grph-s thniqu ovr th Eqution (7), it is possil to hiv n iint NSP rrngmnt with 7 trnsistors, s shown in Fig. 8().! () Fig. 8. Two possil solutions to implmnt th Eqution (7): in (), SP ntwork otin through toriztion thniqu n in (), NSP ntwork otin through grph-s thniqu. In this s, th gins otin y using th NSP rrngmnt rmin whn onsiring IG FinFETs. It is illustrt in Fig. 9() n Fig. 9(), whih prsnt th SP n NSP solutions, rsptivly. Noti tht th NSP rrngmnt is th st solution, kping rution o 2 trnsistors whn ompr to th SP implmnttion. () ()! () Fig. 9. Two possil solutions to implmnt th Eqution (6): in (), SP ntwork otin through toriztion thniqu n in (), NSP ntwork otin through grph-s thniqu. Th prvious xmpls hv monstrt, or gnrl Booln untions, th hllngs whn gnrting miniml trnsistor ntworks using th FinFET thnology. Howvr, th nxt xmpl ims to monstrt how IG FinFETs t th implmnttion o trnsistor ntworks riv rom spil Booln untions lsss lik r-on (RO) n r-polrity-on (RPO). A Booln untion is onsir RO i it n rprsnt in tor orm whr h vril pprs only on [18]. Th untion rprsnt y Eqution (9) is RO. () = ( + ). ((.) + ) (9) Similrly, Booln untion is onsir RPO i it n rprsnt in tor orm whr h polrity (positiv or ngtiv) o vril pprs t most on in th minimum tor xprssion [19]. Th untion rprsnt y Eqution (10) is RPO. = (!. + ). ( + ) (10) Funtions rom RO n RPO lsss r ttrtiv, spilly us th optimlity n gurnt or ths lsss. In othr wors, RO n RPO untions n lwys tor with th minimum numr o litrls. This wy, it is possil to gnrt iint trnsistor ntworks ompos o th minimum numr o singl gt vis. Howvr, whn onsiring oul gt vis, s IG FinFETs, ths lsss nnot gurnt th optimlity in trms o trnsistor ount uring th ntwork gnrtion. It ours u th sm t prsnt in th Exmpl 2, whr tor orm with th minimum numr o litrls os not livr th minimum ntwork. Thus, w hv osrv tht, lthough th inition o RO lss sys tht h vril must pprs on, in som ss, it is opportun to rpt som vrils in th tor xprssion in orr to hiv th st mrg o sris n prlll trnsistors in IG FinFETs. This osrvtion is lso vli or Booln untion rom RPO lss. Exmpl 5: For instn, lt us onsir th RO untion rprsnt y Eqution (11). This tor orm n us to uil th ntwork illustrt in Fig. 10(), whr h litrl prsnt in th xprssion ws irtly mpp to singl gt trnsistor in th ntwork. Anothr possiility is to uil ntwork using this tor orm n mrging sris n prlll trnsistors in IG FinFETs, rsulting in th ntwork illustrt in Fig. 10(). Howvr, th ntwork prsnt in Fig. 10() is not th st solution

5 in numr o trnsistors. Osrv tht, y rpliting th litrl in th tor orm o Eqution (11), it is possil to hiv th ntwork prsnt in Fig. 10(), whih svs on trnsistor ompr to th ntwork illustrt in Fig. 10(). = (. (. ( + ) + (.. g))) (11) g () g g () () () Fig. 11. Originl rrngmnt in (), ntwork otin y toring oring [12] in (), n th propos mrging in (). Th son toriztion thniqu prsnt in [12] ims to mp th originl rrngmnt, similr to tht illustrt in Fig. 12(), to mor iint ntwork. It is on y toring n mrging sris trnsistors (litrls), s shown in Fig. 12(). Agin, w hv osrv tht thr is nothr wy or toring th rrngmnt illustrt in Fig. 12(), rsulting in wr trnsistors thn th solution otin y toring oring to [12]. W monstrt it y mrging prlll trnsistors, s shown in Fig. 12(). () Fig. 10. In () SG FinFET implmnttion n in () IG FinFET implmnttion, oth otin rom th tor orm o Eqution (11). In () IG FinFET implmnttion otin y rpliting th litrl in th tor orm o Eqution (11). III. PROPOSED DEFACTORIZATION TECHNIQUE In t, th IG FinFET hs stlish innovtions n hllngs uring th trnsistor ntwork gnrtion. Consquntly, th rrngmnts livr y onvntionl thniqus, s on toriztion or grph optimiztions, my not usul nough to xplor th potntil o mrging sris n prlll trnsistors. In this sns, n ltrntiv is to pply toriztion thniqu ovr th tor orm. It ws irstly monstrt in [12], whr th uthors prsnt two wys or toring Booln xprssions. Th irst toriztion thniqu prsnt in [12] ims to mp tritionl rrngmnts, lik th ntwork illustrt in Fig. 11(), to n optimiz ntwork y toring n mrging prlll trnsistors (litrls), s shown in Fig. 11(). As n sn, it ls to rs th numr o trnsistors. Howvr, w hv osrv tht it my not th st solution in trms o trnsistor ount. Thus, whn thr is similr onigurtion to th illustrt in Fig. 11(), w propos th mrg o sris trnsistors, rsulting in th ntwork illustrt in Fig. 11(). Noti tht, y mrging sris trnsistors inst prlll ons, it ws possil to sv on trnsistor i ompr to th solution otin y toring oring to [12]. () () () Fig. 12. Originl rrngmnt in (), ntwork otin y toring oring [12] in (), n th propos mrging in (). Whn th purpos is to gnrt ru trnsistor ntworks y pplying toriztion thniqu, w suggst tht our two ltrntivs, illustrt in Fig. 11() n Fig. 12(), r us to rs th trnsistor ount. Howvr, inst o using toriztion thniqu, mor sophistit huristi n propos, it to ining th st mrg o sris n prlll trnsistors long o th optimiztion pross. This is rss in th nxt sssion. IV. PROPOSED METHOD TO GENERATE REDUCED IG FINFET TRANSISTOR NETWORKS Although it is possil to gnrt optimiz trnsistor ntworks y pplying th toriztion thniqu prsnt or, suh thniqu must ppli togthr with (or tr) tritionl toriztion mtho. It my omputtionl xpnsiv, onsiring th ost o toring ssoit to th ost o toring Booln xprssion. Bsis tht, th qulity o th inl solution is strongly pnnt o th ntwork prviously gnrt y th rsultnt Booln xprssion. Consiring this snrio, w propos n ltrntiv mtho tht tris to in th st ()

6 mrg o sris n prlll trnsistors uring th ginning o th optimiztion pross without prorming toriztions. This wy, it is possil to iintly xplor th sprt gts in IG FinFETs uring th ntwork gnrtion. Th propos mtho is ivi in thr stps n oprts ovr n irrunnt-sum-o-prouts (ISOP). Th irst stp (A), tris to in iint rrngmnts through grph-s strutur ll SP krnl, whih ws prviously prsnt in [17]. Th son stp (B), prsnts strtgy to prorm simpl toring oprtions onsiring som onstrints to mximiz th mrg o sris n prlll trnsistors. Finlly, th thir stp (C) is rsponsil or uiling th inl ntwork y omposing th SP krnls with th tor rrngmnts, whih wr otin uring th prvious stps. A. Sris-Prlll Krnl Finr Th SP krnls prsnt hr llows or iint rrngmnts with lrg shring twn th pths o th ntwork. Bsis tht, suh rrngmnts r promising to mrg in IG FinFETs. Ths, r two ttrtiv hrtristis tht ontriut to rs in th trnsistor ount. Th min i hin th SP krnls is to omin th us o th input ISOP, tking our thm t tim, in orr to uil n unirt grph whr th us r rprsnt through th vrtx n th gs rprsnt ommon litrl twn pir o us (vrtis). A SP krnl is trmin oring to th initions n rstritions prsnt low. For h omintion, th lgorithm slts our us omposing untion h tht is rprsnt y n ISOP orm. In squn, n unirt grph G = (V, E) is uilt, whr th vrtis in V = {v 1,v 2,v 3,v 4 } rprsnt irnt us in h, so V = 4. To nsur tht th otin grph is vli SP krnl, two ruls must hk: Rul 1 Lt E vi th st o gs tht r onnt to v i n E vi th numr o gs in this st. For h vrtx v i V, th st o litrls o v i (i.., litrls(v i )) must shr through th gs j E vi. This rul is stisi i n only i th ollowing qution rsults in th vlu 1: (( ) ) (12) Rul 2 Th grph G otin must isomorphi to th grph shown in Fig. 13(), rrr hrin s SP krnl. v 1 4 = v 4 v 1 1 = v 1 v 2 v 4 3 = v 3 v 4 2 = v 2 v 3 v 3 v () () () Fig. 13. SP krnl tmplt (), uxiliry tmplt grph () n rsulting trnsistor ntwork () Th SP krnl inr stp must pply som trnsormtions ovr th grph in orr to mp h krnl oun to swith ntwork. Thror, th irst stp onsists on mpping th krnl gs, illustrt in Fig. 13(), to n uxiliry tmplt grph pit in Fig. 13(). Atr, n g rorring routin is ppli ovr th uxiliry tmplt grph, moving th g 1 to th pl o 3, thus, th g 3 is mov to th pl o 2, n inlly, th g 2 is mov to th pl o 1. This g rorring rsults in th trnsistor ntwork illustrt in Fig. 13(). Through ths oprtions, it is possil to nsur tht h pth o th swith ntwork rprsnts u rom th untion h. Exmpl 6: In orr to monstrt how trnsistor ntwork is otin rom SP krnl, lt us onsir th krnl illustrt in Fig. 14(), whih ws otin rom th ollowing qution: = (13) Th g lls r mpp rom th krnl to th uxiliry grph shown in Fig. 14(). Consquntly, y pplying th g rorring ovr th uxiliry grph, th krnl oun is mpp to th trnsistor ntwork pit in Fig. 14(). Noti tht th uxiliry tmplt grph n th g rorring routin r nssry to implmnt th us rom Eqution (13) through th shring twn th pths o th ntwork. As n sn in Fig. 14(), th prlll trnsistors ( + ) n ( + ) n mrg in IG FinFETs (prlll), rsulting in ntwork with only two trnsistors. It is worth to mntion tht th SP krnl llows th gnrtion o ntworks with mor trnsistors thn this xmpl prsnt in Fig. 14, nling lso th mrg o sris trnsistors..... () () () Fig. 14. SP krnl () riv rom Eqution (13), uxiliry grph tmplt () n trnsistor ntwork () otin tr pplying th g rorring routin. B. IG FinFET Dit Ftoriztion This stp is rsponsil or toring th us rom th input ISOP in suh wy tht thr r t lst two litrls ommon to group o us. This onstrint ws opt in orr to prioritiz toriztions whih llow th mrg o two litrls in n IG FinFET n so, minimiz th us o SG FinFETs in th ntwork. Thus, th lgorithm uss tl to trmin th rltionship twn th us. This is monstrt in th ollowing xmpl. Exmpl 7: For instn, onsir th Booln untion sri y Eqution (14). =. +!..!.! (14)

7 Firstly, th lgorithm uils tl using th us n th vrils rom th input ISOP s prsnt in Fig. 15. Th ourrn o vril in th irt or omplmntry polrity is rprsnt y 1 n 0, rsptivly, in th tl. Thn, th nxt stp onsists o prorming srh ovr th tl in orr to in th wnt groups, lik this irl y sh lin in Fig. 15. Th i hin this group is to init tht thr r t lst two ommon litrls, i.. (. ), in u3 n u4. Thus, ths us will tor s ollow: (. ). ( + ). This lol toriztion n implmnt using only two IG FinFETs, on (sris) n on (prlll), s n sn in th ltmost rnh o th ntwork illustrt in Fig. 16. In squn, th rmining us, u1 n u2, whih not long to ny group, r implmnt s inpnnt rnhs using IG FinFETs (sris), s n sn in th rightmost rnhs o th ntwork illustrt in Fig. 16. Fig. 15. Cus rltionship to trmin groups tht shr t lst two litrls n rsult in th wnt toriztions. Noti tht, y opting toriztions with t lst two litrls, it ws possil to voi th shring o th litrl, whih pprs thr tims, s irl y ott lin in Fig. 15. Tritionl toriztion mthos tn to prorm th unwnt shring, rsulting in th ntwork illustrt in Fig. 17. As n sn in Fig. 16, th ntwork otin y th propos mtho svs on trnsistor i ompr to th onvntionl solution prsnt in Fig. 17. Fig. 16. Trnsistor ntwork livr y th propos mtho, otin rom Eqution (14). Fig. 17. Trnsistor ntwork livr y onvntionl mthos, otin rom Eqution (14). C. Ntwork Composition u u2!..!.! u u wnt wnt unwnt! unwnt As mntion or, this stp ims to ompos th SP krnls n th tor rrngmnts otin uring th prvious stps in orr to uil th inl ntwork. Thus,!!!!! suh ntwork n gnrt o irnt wys oring to th input ISOP: (i) ntwork n implmnt using on or mor SP krnl ssoit in prlll; (ii) ntwork n implmnt using on or mor SP krnls, ssoit in prlll to othr tor rrngmnt otin in th stp (B); (iii) no SP krnls r oun uring th stp (A), so, th ntwork is ompltly gnrt in th stp (B). Atr th ntwork ing gnrt y ssoiting th surrngmnts s prlll rnhs, th g shring thniqu prsnt in [16] is ppli ovr th ntwork. It is on in orr to prorm lol optimiztions n rmov som runnis, whih my vntully xist twn th SP krnls n th tor rrngmnts. An intrsting hrtristi o th propos mtho is tht, y pplying suh g shring thniqu in this lst stp, th mtho is l to in sris-prlll n lso non-srisprlll rrngmnts. As prsnt in th Exmpl 4, in som ss, it n ontriut to rs th trnsistor ount. In gnrl, th ntworks gnrt y th propos mtho tn to ompos only o sris-prlll rrngmnts. It is u to th t tht th stps (A) n (B) prou sris-prlll rrngmnts oming vry similr to th solution o onvntionl toriztion. V. RESULTS W hv implmnt th mtho propos in Stion IV n us two irnt sts o Booln untions in orr to vlut it. Th irst xprimnt ws prorm ovr th st o ll 5-inputs NPN-lss (ngtion-prmuttion-ngtion), whih is ompos o 616,126 untions. This st ws ppli to th propos mtho n lso to th most rnt pulish mthos o toriztion [14] n grph-s optimiztions [17]. Th son xprimnt ws prorm ovr th st o ll r-on untions with t most 6- inputs, whih is ompos o 456,772 untions. This st ws ppli to th propos mtho n to mtho it to r-on untions [18]. It is worth to rmmr tht ths mthos [14][17][18] wr sign or toring n gnrt ntworks onsiring only singl gt vis. Thus, w hv mrg sris n prlll trnsistors in orr to mp th originl rrngmnts livr y suh mthos to IG FinFETs trnsistor ntworks. This wy, it is possil to prorm ir omprison o th propos mtho with ths othr thniqus. Tl II prsnts th totl numr o trnsistors otin y h vlut mtho, whn onsiring th 5-inputs NPN-lss Booln untions. As n sn, th propos mtho ws l to minimiz mor trnsistors thn th othr thniqus. TABLE II TOTAL NUMBER OF TRANSISTORS FOR THE SET OF 5-INPUTS NPN-CLASS BOOLEAN FUNCTIONS. [14] [17] Propos Mtho Totl Numr o Dvis 7,350,852 8,037,628 6,843,272

8 Tl III prsnts th totl numr o trnsistors otin y h mtho, whn onsiring th st o 6-inputs ron untions. Agin, th propos mtho ws l to minimiz mor trnsistors thn th othr thniqu, whih is it to r-on untions. In othr wors, th mtho [18] lwys livrs th xt (minimum) solution whn onsiring singl gt vis. Howvr, not nsurs th optimlity or IG FinFETs. TABLE III TOTAL NUMBER OF TRANSISTORS FOR THE SET OF 6-INPUTS READ-ONCE FUNCTIONS. [18] Dit to R-On Propos Mtho Totl Numr o Dvis 1,760,248 1,714,131 In, th propos mtho is n ltrntiv wy to gnrt IG FinFET trnsistor ntworks, ing l to rs th trnsistor ount y iintly xploring oul gt vis. It is worth to mntion tht th propos mtho prsnt in this work only xplors som hrtristis tht n l to ru trnsistor ntwork implmnttion. W hv intii tht, in som ss, th propos mtho livrs solutions with n ovrh o trnsistors whn ompr to th tritionl thniqus. Ths ss will rully invstigt in th utur in orr to improv th propos thniqu. VI. CONCLUSIONS This ppr hs prsnt til isussion out nw hllngs on IG FinFET trnsistor ntwork gnrtion. Through th xmpls n rsults prsnt in this work it ws possil to intiy tht th tritionl mthos or gnrting trnsistor ntworks my not th st ltrntiv to uil ntworks s on IG FinFETs. Thus, this ppr hs prsnt two possiilitis to improv th ntwork sign. Th irst on is s on toriztion thniqu, whih llow th gnrtion o mor optimiz rrngmnts whn ompr to rlt works. Th son on is grph-s mtho l to in su-rrngmnts tht mk sil th mrg o sris n prlll trnsistors in IG FinFETs. Th prliminry otin rsults hv monstrt tht th propos mtho is sil ltrntiv. ACKNOWLEDGMENT Rsrh prtilly support y Brzilin uning gnis CAPES, CNPq, FAPERGS unr grnt 11/ (Pronm), n th Europn Community's Svnth Frmwork Progrmm unr grnt Synpti. REFERENCES [1] Frnk, E. J., Dnnr, R. H., Nowk, E., Solomon, P. M., Tur, Y. n Wong, H.-S. P. Dvi sling limits o Si MOSFETs n thir pplition pnnis, Pro. IEEE, 89(3): , Mr [2] Hung, X., L, W., Kuo, C., Hismoto, D., Chng, L., Kzirski, J., Anrson, E., Tkuhi, H., Choi, Y., Asno, K., Surmnin, V., King, T., Bokor, J., Hu, C. "Su 50-nm FinFET: PMOS," Thnil Digst. Intrntionl Eltron Dvis Mting (IEDM '99), pp , [3] Choi, Y., Jon, Y., Rn, P., Tknuhi, H., King, T., Bokor, J., Hu, C. "30 nm ultr-thin-oy SOI MOSFET with sltivly posit G ris S/D, in Pro. 58th DRC Dvi Rsrh Conrn, Jun 2000, pp [4] Chng, L., Choi, Y., H, D., Rn, P., Shiying, X., Bokor, J., Hu, C. n King, T. J. Extrmly sl silion nno-cmos vis, Pro. IEEE, vol. 91, no. 11, pp , Nov [5] Nowk, E. J., Allr, I., Luwig, T., Kim, K., Joshi, R. V., Chung, C. T., Brnstin, K. n Puri, R. Turning silion on its g, IEEE Ciruits Dvis Mg., vol. 20, no. 1, pp , Jn./F [6] Roy, K., Mhmooi, H., Mukhophyy, S., Anthn, H., Bnsl, A. n Ckii, T. Doul-gt SOI vis or low-powr n highprormn pplitions, in Pro. IEEE Int. Con. CAD (ICCAD 2005), pp [7] Ching, M., Kim, K., Trtz, C. n Chung, C. Novl High-Dnsity Low-Powr Logi Ciruit Thniqus Using DG Dvis, IEEE Trnstions on Eltron Dvis, Vol. 52, No. 10, pp , Ot [8] Dtt, A., Gol, A., Ckii, R. T., Mhmooi, H., Lkshmnn, D. n Roy, K. "Moling n Ciruit Synthsis or Inpnntly Controll Doul Gt FinFET Dvis," IEEE Trnstions on Computr-Ai Dsign o Intgrt Ciruits n Systms, Vol. 26, No. 11, pp , Nov [9] Muttrj, A., Agrwl, N., Jh, N. K. "CMOS logi sign with inpnnt-gt FinFETs," in Pro. 25th Int. Con. on Computr Dsign (ICCD 2007). pp [10] Ching, M., Kim, K., Chung, C. n Trtz, C."High-Dnsity Ru-Stk Logi Ciruit Thniqus Using Inpnnt-Gt Controll Doul-Gt Dvis," IEEE Trnstions on Eltron Dvis, Vol. 53, No. 9, pp , Sp [11] Wng, M. C. "Inpnnt-Gt FinFET Ciruit Dsign Mthoology," Intrntionl Journl o Computr Sin, Vol. 37 Issu 1, pp. 50, Mr [12] Rostmi, M. n Mohnrm, K. "Dul-Vth Inpnnt-Gt FinFETs or Low Powr Logi Ciruits," IEEE Trnstions on Computr-Ai Dsign o Intgrt Ciruits n Systms, Vol. 30, No. 3, pp , Mr [13] Sntovih, E., t l. SIS: A systm or squntil iruit synthsis. Thnil Rport No. UCB/ERL M92/41, EECS Dprtmnt, Univrsity o Cliorni, Brkly, [14] Mrtins, M. G. A., D Ros Junior, L. S., Rsmussn, A., Ris, R. P. n Ris, A. I. Booln Ftoring with Multi-Ojtiv Gols, in Pro. 28th Int. Con. on Computr Dsign (ICCD 2010), p [15] Kgris, D. n Hniotkis, T. A Mthoology or Trnsistor- Eiint Suprgt Dsign, IEEE Trns. on Vry Lrg Sl Intgrtion (VLSI) Systms, p , [16] Possni, V. N., Souz, R. S., Domingus Junior, J. S., Agostini, L. V., Mrqus, F. S. n D Ros Junior, L. S. Optimizing Trnsistor Ntworks Using Grph-Bs Thniqu, Journl o Anlog Intgrt Ciruits n Signl Prossing (ALOG), My 2012, v. 73, p , [17] Possni, V. N., Cllgro, V., Ris, A. I., Ris, R. P., Mrqus, F. S. n D Ros Junior, L. S. Improving th Mthoology to Buil Non-Sris-Prlll Trnsistor Arrngmnts, in Pro. 26th Symp. on Intgrt Ciruits n Systms Dsign (SBCCI 2013), pp [18] Golumi, M. C., Mintz, A. & Rotis, U. (2008). An improvmnt on th omplxity o toring r-on Booln untions, Disrt Appli Mthmtis, 156(10), [19] Cllgro, V., Mrtins, M. G. A., Ris, R. P. & Ris, A. I. R- Polrity-On Funtions, in Pro. 26th Symp. on Intgrt Ciruits n Systms Dsign (SBCCI 2013), pp. 1-6.