Lecture 6. Thermal-Aware Design

Transcription

1 Summer Course: Advanced Topics in Modern VLSI design Lecture 6. Thermal-Aware Design Instructor: Yuan Xie Course website:

2 Motivation Outline Run-time Temperature Mitigation Solutions Dynamic Thermal Management Activity Migrations Design time thermal-aware techniques Design Time Temperature Estimation Thermal-Aware Floorplanning Thermal-Aware Allocation and Scheduling Thermal-Aware Loop Parallelization for CMP 2/50

3 What is the thermal impact? Performance Interconnect delay increases & MOS current drive capability decreases with temperature increase. Power: Leakage current increases exponentially with temperature increase. Temperature vs. Delay (Source: H. Amir, VLSI Technology 2001) Temperature vs. Leakage (Source: V. De, ISLPED 1999) 3/50

4 Reliability: What is the thermal impact? Cost: e.g.: electromigration (EM), time-dependent cost of cooling is $1-3 or more per dielectric (gate oxide) breakdown (TDDB) Watt when the average power exceeds are all significantly accelerated 40 Watts (Intel Technology Journal, Q1, 2001) Tpeak (65nm) = Tpeak(180nm)+15 C Failure rate (65nm) processor is 316% higher than the Failure rate at 180nm (IBM DSN 2004) 4/50

5 Thermal Packaging is Expensive P4 packaging Heating and therefore cooling costs are rising exponentially Currently $2-3/W 5/50

6 What is the thermal impact? Performance Cost a. higher temperature lower performance a d b. higher temperature higher leakage power c. higher temperature higher hard error rate b e Temperature c d. higher temperature higher cooling cost e. higher power density higher temperature Power Reliability 6/50

7 温度与功耗密度 (power density) 的关系 Power Map On-Die Temperature Heat Flux (W/cm2) Temperature (C) Heat dissipation => temperature, higher power density => higher temperature Power density is not uniformly distributed across the chip Intel Pentium 4: (0.18 um) mm 2 Intel Pentium 4: (90 nm) 112 mm 2 7/50

8 一些芯片温度的例子 IBM Power G4 die temperature profile 8/50

9 一些芯片温度的例子 9/50

10 一些芯片温度的例子 10/50

11 Apple Power G 年号称最快的台式机 问题 : 机箱里有多少风扇? 答案 : 21 thermal sensors, 9 fans 11/50

12 Motivation Outline Run-time Temperature Mitigation Solutions Dynamic Thermal Management Activity Migrations Design time thermal-aware techniques Design Time Temperature Estimation Thermal-Aware Floorplanning Thermal-Aware Allocation and Scheduling Thermal-Aware Loop Parallelization for CMP Thermal issues in 3D Chip Design What is 3D Chip? Will temperature be a showstopper for 3D adoption? 12/50

13 DTM Trigger Mechanisms Mechanism: How to deduce chip temperature? Direct approach: on-chip temperature sensors Based on differential voltage change across two diodes of different sizes May require more than one sensor Policy: When to begin responding? Trigger level set too high means higher packaging costs Trigger level set too low means frequent triggering and loss in performance 13/50

14 Dynamic Thermal Management (DTM) Trigger Mechanism: When do we enable DTM techniques? Brooks et. al. Initiation Mechanism: How do we enable technique? Response Mechanism: What technique do we enable? 14/50

15 temperature DTM Activation and Deactivation Cycle Cooling capacity without DTM Cooling capacity with DTM DTM trigger level savings Trigger Reached Turn Response On Check Temp Check Temp Turn Response Off InitiationResponse Delay Delay Policy Delay Shutoff Delay Initiation Delay OS interrupt/handler Response Delay Invocation time (adjust clock, V DD ) Policy Delay Number of cycles engaged Shutoff Delay Disabling time (re-adjust clock, V DD ) 15/50

16 An Example of DFS and DVS Transmeta LongRun 32 levels of V DD from 1.1V to 1.6V Frequency from 200MHz to 700MHz in 33MHz incrs. heavier load detected lighter load detected f V DD 16/50

17 Fetch Gating/ I-cache Toggling Disable the instruction fetch unit (I-$ and branch prediction) Fetch unit can be disabled every N cycles until disengaged, N=1,2~n At microarchitecture level and have less performance loss compared to DVS/DFS Performance slows down 12% while 22% for DVS/DFS Brooks and Martonosi, HPCA /50

18 Migrating Computation When one unit overheats, migrate its functionality to a distant, spare unit Spare register file (Skadron et al. 2003) Separate core (CMP) (Heo et al. ISLPED 2003) Microarchitectural clusters (Intel, ICCD 2004) Raises many interesting issues Cost-benefit tradeoff for that area Use both resources (scheduling) Extra overhead for long-distance communication Floorplanning 18/50

19 Migrating Computation Two units run hot will tend to run even hotter when adjacent Observation: Integer register file is the hottest! Stall the primary IntRegFile and use the secondary IntRegFile. One extra cycle latency incurred for longer communication distance. 19/50

20 Activity Migration to Reduce Peak Temp Using Spare unit. When one unit overheats, migrate its functionality to a distant, spare unit T max T H Temperature ( C) T L T a t cycle t cool t heat Time (s) 20/50

21 Migration Types Type 1-Time-based:Migrate between units every n clock cycles Insensitive to dynamic temp. fluctuations May cause too much performance overhead No need for temp sensing Type 2- Primary/Secondary Migration: Migrate between primary and secondary unit based on two temperature thresholds Secondary may overheat while waiting for the primary to cool Difficult to choose thresholds well Type 3: Swapping Migration: Migrate amongst units based on one temperature threshold When unit A hits threshold, move to unit B When unit B hits threshold, move to unit A Ref: T.Richardson and Y.Xie, ASICON /50

22 Thermal Scheduling (Intel 2002) Primary FE DE OOP EX Majority mobile apps with performance requirements Secondary RF Primary pipeline: maximal performance, complex pipeline structure Second pipeline: Minimum power and energy consumption, very simple in order structure and target mobile anywhere-anytime applications. Transparent to OS and applications DE IOP Text , caller-id, reminder and other none high performance w/ anywhereanytime requested apps Ref: Cai. Et al. ISQED /50

23 Reference: DTM Techniques Dynamic volt./freq. scaling (DVS/DFS)(Transmeta, Pentium M) Clock gating (PowerPC, Pentium III/4, Gunther, Intel 01) Fetch gating or toggling (Brooks, HPCA 01) Speculation control/pipeline gating (Manne, ISCA 98) Dual pipeline (Lim, ISQED 02) Dynamic energy efficiency and temperature management (DEETM) (Huang, Micro 00) Feedback-controlled fetch gating (Skadron, HPCA 02) Temperature-tracking frequency scaling (Skadron, ISCA 03) Migrating computation (Skadron, ISCA 03) 24/50

24 Motivation Outline Run-time Temperature Mitigation Solutions Dynamic Thermal Management Activity Migrations Design time thermal-aware techniques Design Time Temperature Estimation Thermal-Aware Floorplanning Thermal-Aware Allocation and Scheduling Thermal-Aware Loop Parallelization for CMP Thermal issues in 3D Chip Design What is 3D Chip? Will temperature be a showstopper for 3D adoption? 25/50

25 Design-time Thermal-Aware techniques My group: Thermal-Aware IP Virtualization and Placement for NOC, ICCD 2004 Thermal-Aware Allocation and Scheduling for MPSOC Design DATE 2005 Thermal-Aware Floorplanning Using Genetic Algorithms ISQED 2005 Thermal-Aware Voltage-island architecting, ICCD 2005 Thermal-Aware Loop Parallelization for CMP, ICCD 2005 Thermal Issues for on-chip bus, DATE 2006 Thermal Issues in 3D Chip (ISQED 2006, ISCA 2006, JETC 2006) Other groups: National Tsinghua Univ./ National Taiwan Univ./Northwestern Univ./ UT.Austin/UIUC/Wisconsin etc. Industry: Gradient Design Automation (a start-up showcases at DAC 2006) 26/50

26 Compact thermal model Electrical-thermal duality V temp (T) I power (P) R thermal resistance (Rth) C thermal capacitance (Cth) Kirchoff Current Law differential eq. I = C dv/dt + V/R thermal domain P = Cth dt/dt + T/Rth where T = Thot Tamb Thot Tamb 27/50

27 Thermal modeling Want a fine-grained, dynamic model of temperature That accounts for adjacency and package That does not require detailed designs That is fast enough for practical use Need a compact model based on thermal R, C Parameterized to automatically derive a model based on various Architectures Power models Floorplans Thermal Packages 28/50

28 Package Heat sink Heat spreader PCB IC Package Pin Die Interface material 29/50

29 Thermal Estimation Tool Power dissipations can come from any power simulator, act as current sources in RC circuit ('P' vector in the equations) Requires models of Floorplan: important for adjacency Package: important for spreading and time constants R and C matrices are derived from the above HS3D, PennState, 30/50

30 Thermal-Aware Floorplanning * * + * 1 + : cut horizontally * : cut vertically Polish Expression : 2 3 * * + * 31/50

31 Floorplanning Encoding chromosome A * chromosome B * 1 * Rotate Slicing 4 32/50

32 Design-time thermal-aware Floorplanning GA Framework Area Estimates Power consumption profile Floorplan info. HotSpot Temp. Extracts Fitness Evaluation 33/50

33 Example 34/50

34 Temperature ('C) Example Area vs Temperature Balanced Optim. (max) apte xerox hp ami33 ami49 Circuits area opt. area opt.+t. Reference: Thermal-Aware Floorplanning using Genetic Algorithms, W.Hung, Y. Xie Proc. of Intl Symposium on Quality Electronic Device, /50

35 Motivation Outline Why temperature-aware design is important Chip examples Run-time Temperature Mitigation Solutions Dynamic Thermal Management Activity Migrations Design time thermal-aware techniques Design Time Temperature Estimation Thermal-Aware Floorplanning Thermal-Aware Allocation and Scheduling Thermal-Aware Loop Parallelization for CMP 36/50

36 Thermal-aware allocation and scheduling HW/SW co-synthesis is the first step in embedded system designs. Prior work only consider traditional design metrics (performance /power/area) Thermal-aware approach in tasks allocation and scheduling. Reference: Thermal-Aware Allocation and Scheduling for MPSOC Design, W. Hung, Y. Xie et al. (DATE 2005) 37/50

37 What is co-synthesis Technology Library Task graph Co-Synthesis Interface Allocation & Scheduling Procedure No Meets requirement? Yes Target architecture & Tasks mapping 38/50

38 Allocation and Scheduling both (a) and (b) meet timing requirement, which one has better thermal profile? 39/50

39 Thermal-Aware Allocation and Scheduling platform-based and co-synthesis architecture. Technology Library Task graph Co-Synthesis Interface Pre-defined platform Task graph Allocation & Scheduling Procedure Platform-based System Interface No Thermal-Aware Floorplanning Meets requirement? HotSpot Tool Temperature Extraction Allocation & Scheduling Procedure Solution (a) Solution (b) 40/50

40 Comparison of Power-aware vs. Thermalaware heuristics 41/50

41 The Trends of CMP 1. How do we feed so many bunnies? 2. Will they get hot? 3. How to train them? Intel researchers and scientists are experimenting with "many tens of cores, potentially even hundreds of cores per die, per single processor die... Justin R. Rattner, Intel director of the Corporate Technology Group, Spring 2005 IDF 42/50

42 Loop Parallelization for CMP for (i=1; i<=600; i++) for (j=1; j<=1000; j++) B[i][j] = (A[i-1][j] + A[i+1][j] + A[i][j-1] + A[i][j+1]) / 4; Jacobi s Algorithm Iteration Core Time chunk number Slot number Time P P P P P P 5 P 6 P 7 Parallel Schedule for (i=k*120+1; i<=(k+1)*120; i++) for (j=1; j<=1000; j++) B[i][j] = (A[i-1][j] + A[i+1][j] + A[i][j-1] + A[i][j+1]) / 4; Parallelized Algorithm for 5 cores 43/50

43 Temperature Aware Scheduling Time P P P P P P 5 P 6 Original Schedule P 7 Slot P P P P P P P P Slot P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 Slot P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 44/50

44 Locality and temperature aware scheduling Algorithm Use temperature aware scheduling to obtain the schedulable slots. Use locality aware scheduling to assign chunks to these slots. Great Locality No temperature problems Good performance Analysis - Best of both worlds C = { I 0, I 1, I 2, I 3, I 4 } C = { } Time P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 Time P 0 P 1 P 2 P 3 P 4 P 5 P 6 P /50

45 Thermal issues for Bus Which bus line is the hottest? 46/50

46 Activities Spreading Encoding TSMC 90nm 4151 um uw. To compare: T0CAC 9243 um mw. 47/50

47 Activities Spreading Encoding 48/50

48 Activities Spreading Encoding Ref: On-Chip Bus Thermal Analysis and Optimization, Feng Wang, DATE /50

49 Motivation Outline Run-time Temperature Mitigation Solutions Dynamic Thermal Management Activity Migrations Design time thermal-aware techniques Design Time Temperature Estimation Thermal-Aware Floorplanning Thermal-Aware Allocation and Scheduling Thermal-Aware Loop Parallelization for CMP Thermal issues in 3D Chip Design What is 3D Chip? Will temperature be a showstopper for 3D adoption? 50/50

50 Thermal issues in 3D Reduction of global interconnect L L Power Density increases! Will Thermal Be a Showstopper for 3D architecture? 51/50

51 Key EDA Challenges to Enable 3D Architecture Under the Temperature Constraints Tools for Early Analysis To estimate temperature (e.g. HS3D, HotSpot3.0) To study the tradeoff: performance vs. power vs. temperature (e.g. ICCD 2005) -- How many layers? -- Power reduction benefits from 3D may help mitigate thermal issues 52/50

52 Key EDA Challenges to Enable 3D Architecture Under the Temperature Constraints Thermal-aware 3D Design 3D Physical Design tools must be thermal-aware Vertical optimization Horizontal optimization (e.g. 3D ISQED 06, 3D Mem-in-net@ ISCA 06) Thermal Via planning (similar to the elevator in highrise) (e.g. GIT/UMN/UCLA research) 53/50

53 Example: Thermal-aware 3D floorplanning An Alpha-like verilog implementation was used. The design was synthesized in both 160nm and 90nm at the granularity of functional module level. The power values for both modules and interconnects are obtained. fetch0 fetch1 fetch2 L1 Ins Cache S-ALU0 AGEN0 4x Decoder TLB Rename0 Rename1 Rename2 S-ALU1 AGEN1 Arch RAT Scheduler Register File C-ALU L1 Data Cache ReOrder Buffer TLB Fetch Decode Rename Schedule RegRead Execute Retire Ref: W.Hung, Y. Xie. Et al. ISQED /50

54 B*-tree floorplan model B*-tree was originally designed for 2D floorplanning. In our 3D model, each layer is represented by one specific B*-tree. Six perturbations are used in exploring design space (the last two are intended for interlayer operations.) 1. Node swap, 2. Rotation (change orientation), 3. Move, 4. Resize (for soft module), 5. Interlayer swap, 6. Interlayer move. 55/50

55 Temperature profiles Temperature('C) avgt avgt(int) peakt peakt(int) Temperature Profile 30 2D 2D(Ther) 3D 3D(Ther) Architecture configuration Temperature('C) peakt(160) peakt(int-160) peakt(90) peakt(int-90) Temperature Profile (160 vs 90) 2D 2D(Ther) 3D 3D(Ther) Architecture configuration 56/50

56 What other problems you can tackle? Thermal-aware xxxxx Testing? High level synthesis? Can you find other applications??? Check Hotspot 3 57/50

57 Conclusion Power dissipation => Heat => temperature BUT power-aware design alone is not able to address the temperature challenge, many low-power techniques have insufficient impact on chip temperature Why? Because they do not directly target the spatial and temporal behavior of the operating temperature. Conclusion: thermal-aware design itself is a distinct and important research area, even though it is related to the poweraware design area. For example, Thermal-Aware Computer System (TACS) Workshop is now associated with ISCA starting from /50