Introduction to Digital Logic

Transcription

1 Introduction to Digital Logic Lecture 15: Comparators

2 EXERCISES Mark Redekopp, All rights reserved

3 Adding Many Bits You know that an FA adds X + Y + Ci Use FA and/or HA components to add 4 individual bits: W + X + Y + Z X Y C out Full Adder S C in

4 Adding 3 Numbers Add X[3:] + Y[3:] + Z[3:] to produce F[?:] using the adders shown plus any FA and HA components you need 11 B3 C A3 S B2 14 A2 S B A1 S1 1 6 B 5 A S 4 7 C C A B A1 B1 A2 B2 A3 B3 283 S 4 S1 1 S2 13 S3 1 C4 9

5 Mapping Algorithms to HW Wherever an if..then..else statement is used usually requires a mux if(a[3:] > B[3:]) Z = A+2 else Z = B+5 B[3:] 11 A[3:] 1 A[3:] B[3:] Adder Circuit Adder Circuit Comparison Circuit I I 1 Y S Z[3:]

6 Mapping Algorithms to HW Wherever an if..then..else statement is used usually requires a mux if(a[3:] > B[3:]) Z = A+2 else Z = B+5 B[3:] A[3:] 11 1 A[3:] B[3:] I I 1 I I 1 S S Y Y Comparison Circuit Adder Circuit Z[3:]

7 Adder / Subtractor If sub/~add = 1 Z = X[3:]-Y[3:] Else Z = X[3:]+Y[3:] I1 I I1 I I1 I I1 I S S S S Y Y Y Y B3 B2 B1 B A3 A2 A1 A C4 4-bit Binary Adder C S3 S2 S1 S

8 Adder / Subtractor If sub/~add = 1 Z = X[3:]-Y[3:] SUB/~ADD Else C Z = X[3:]+Y[3:] SUB/ ~ADD Yi 1 1 Bi Y Y1 Y2 Y3 X X1 X2 X3 A A1 A2 A3 B B1 B2 B3 C4 4-bit Binary Adder S3 S2 S1 S Z Z1 Z2 Z3 1 1 SUB/~ADD

9 Adder / Subtractor X + 5, when A5,M1 = 1, Z = X 1, when A5,M1 =,1 X, when A5,M1 =, C M1 A5 X X1 X2 X3 B3 B2 B1 B A3 A2 A1 A C4 4-bit Binary Adder S3 S2 S1 S Z Z1 Z2 Z3

10 Multiplication By Powers of 2 In decimal, multiplication by 1 n can easily be achieved by adding n s to the right of the number 937 * 1 = 937 * 1 2 = 93,7 145 * 1 = 145 * 1 4 = 1,45, In binary, multiplication by 2 n can easily be achieved by adding n s to the right of the number 3 1 = = 3*2 1 = = 3*2 2 = = 3*2 3 = 11 2

11 Division By Powers of 2 In decimal, division by 1 n can easily be achieved by shifting the decimal point n places to the left 937 / 1 = 937 / 1 2 = ,768 * 1 = 145,768 / 1 4 = In binary, division by 2 n can easily be achieved by shifting the decimal point n places to the left 12 1 = 11 => 12/2 1 = = = 11 => 12/2 2 = = = 111 => 7/2 1 = = 3.5

12 Constant Multiplication w/ Adders Design a circuit to calculate Y = 1X, where X is a 4-bit unsigned number (1 1 is a constant) Break it down to powers of 2 (e.g. 1X = 8X+2X) Recall, multiplying by a power of 2 is equal to shifting X to the left that number of bits (i.e. 8X is just X shifted to the left 3 places) if X = 11 2 = 3 1 8X = 11 2 = X = 11 2 = = 8X + 11 = 2X 1111 = 1X

13 Constant Multiplication w/ Adders Design a circuit to calculate Y = 1X, where X is a 4-bit unsigned number (1 1 is a constant) Break it down to powers of 2 (e.g. 1X = 8X+2X) Recall, multiplying by a power of 2 is equal to shifting X to the left that number of bits (i.e. 8X is just X shifted to the left 3 places) if X = 11 2 = 3 1 8X = 11 2 = X = 11 2 = = 8X + 11 = 2X 1111 = 1X

14 Performing Multiplication w/ Adders How many 4-bit adders do we need? X 3 X 2 X 1 X = 8X + X 3 X 2 X 1 X = 2X Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y = 1X

15 Performing Multiplication w/ Adders To implement using 4-bit adders, Assume 4-bit number X = X 3 X 2 X 1 X These are the bits that need to be added X 3 X 2 X 1 X = 8X + X 3 X 2 X 1 X = 2X Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y = 1X We don t need an adder to figure out what the sum of these 3 columns are because we re adding with

16 Y = 1*X Circuit X 3 X 2 X 1 X x 3 x 2 x 1 x 3 x x 2 X 1 X C out B 3 B 2 B 1 A B C in S 3 S 2 S 1 S Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y

17 COMPARATORS Mark Redekopp, All rights reserved

18 Comparators Compare two numbers and produce relational conditions,,, A B, and A B Suppose we want to compare two, 4-bit numbers: A[3:] and B[3:] Too big to build directly decompose the problem Compare: A3 A2 A1 A B3 B2 B1 B

19 Start Easy Build a circuit to compare a bit, A, with a bit, B The only way one bit, A, can be greater than another bit, B, is if A=1 and B= The only way one bit, A, can be less than another bit, B, is if A= and B=1 A and B are equal when they are the same A B 1 A B X Y A B Comp. GT EQ LT Mark Redekopp, All rights reserved XNOR A B A B A B

20 4-bit Comparator A3 B3 A2 B2 A1 B1 A B X Y X Y X Y X Y Comp. Comp. Comp. Comp. GT EQ LT GT EQ LT GT EQ LT GT EQ LT Merger

21 Merging Comparison Results Suppose we have the comparison results of individual digits of a 2-digit number, how can we combine them to produce the overall result? Key: More significant digits/bits fully determine results of overall comparison unless they are equal in which case we use the result of the less significant digits A=(9 3) 1 B=(7 8) 1 MSD: 9 > 7 LSD: 3 < 8 Overall? A > B (9x > 7x)

22 Greater-Than, Less-Than, Equal Find an algorithm to check whether one decimal number is greater than, less than, or equal to another 837 > 756 Start with the MSD, 8 > 7 and you re done any number with 8 in the 1 s place is greater than a number with 7 in the 1 s place 621 < 649 Start with the MSD, 6 = 6 you can t tell yet which is greater or less than so move to the next digit 2 < 4 and you re done 62x is always less than 64x Algorithm: Start with the MSD and keep comparing digits to the right. Once any digit of A is > or < corresponding digit of B then you know the whole number A > B or A < B, respectively. If all digits are equal then both number are equal.

23 Merging Results MS Digit Results LS Digit Results Outputs (MS) (MS) (MS) (LS) (LS) (LS) A > B A< B A = B Mark Redekopp, All rights reserved A=(9 3) 1 B=(7 8) 1 MSD: 9 > 7 LSD: 3 < 8 Overall?

24 Merging Results MS Digit Results LS Digit Results Outputs (MS) (MS) (MS) (LS) (LS) (LS) A > B A< B A = B 1 X X X 1 1 X X X Mark Redekopp, All rights reserved A=(9 3) 1 B=(7 8) 1 MSD: 9 > 7 LSD: 3 < 8 Overall?

25 Merging Logic MS Digit Results LS Digit Results Outputs MGT MLT MEQ LGT LLT LEQ GT LT EQ 1 X X X 1 1 X X X GT = MGT + MEQ LGT LT = MLT + MEQ LLT EQ = MEQ LEQ MGT MEQ MLT GT EQ LT. Merger LGT LEQ LLT

26 4-bit Comparator A3 B3 A2 B2 A1 B1 A B X Y X Y X Y X Y Comp. Comp. Comp. Comp. GT EQ LT GT EQ LT GT EQ LT GT EQ LT MGT MEQ MLT MGT MEQ MLT MGT MEQ MLT MGT MEQ MLT GT EQ LT. Merger LGT LEQ LLT GT EQ LT. Merger LGT LEQ LLT GT EQ LT. Merger LGT LEQ LLT GT EQ LT. Merger LGT LEQ LLT 1 Delay: Linear in the length of the chain Mark Redekopp, All rights reserved Can we try to implement the merging in 2-levels?

27 4-bit Equality Check XNOR gate outputs 1 when two bits are equal A B A B XNOR To check whether two 4- bit numbers are equal use 4 XNOR gates to XNOR each pair of bits only if all the pairs are equal, are the 2 numbers equal (i.e. AND the outputs together) A B B 1 B 2 A =B =B 1 =B 2 =B 3 B 3

28 4-bit Greater-Than Consider 2 numbers A ( A ) and B (B 3 B 2 B 1 B ) There are 4 cases for when A > B > B 3 and who cares about the other bits = B 3, > B 2 and the other bits don t matter = B 3, = B 2, > B 1 and the other bits don t matter = B 3, = B 2, = B 1, A > B Case 1 Case 2 Case 3 Case 4 1xxx = A 1xx = A 111x = A 1 = A xxx = B xx = B 11x = B = B

29 4-bit Less-Than The same style algorithm can be used to check for less-than. There are 4 cases for when A < B < B 3 and who cares about the other bits = B 3, < B 2 and the other bits don t matter = B 3, = B 2, < B 1 and the other bits don t matter = B 3, = B 2, = B 1, A < B Case 1 Case 2 Case 3 Case 4 xxx = A xx = A 11x = A = A 1xxx = B 1xx = B 111x = B 1 = B

30 4-bit Comparator A3 B3 A2 B2 A1 B1 A B X Y X Y X Y X Y Comp. Comp. Comp. Comp. GT EQ LT GT EQ LT GT EQ LT GT EQ LT GT3 LT3 EQ3

31 4-bit Cascabable Comparator (74LS85) 4-bit Magnitude Comparator (Non-cascadable) A B A B 1-bit comparator LT GT EQ A1 B1 A B 1-bit comparator LT1 GT1 EQ1 A2 B2 A B 1-bit comparator LT2 GT2 EQ2 A3 B3 A B 1-bit comparator LT3 GT3 EQ3 of LSB s of LSB s of LSB s

32 Less-Than Rather than using the previous logic, put less-than in terms of equal and greaterthan = () ()

33 4-bit Magnitude Comparator A A =B B B 1 =B 1 =B 2 B 2 B 3 =B 3 B 3 B 2 B 1 A B

34 4-bit Magnitude Comparator A A =B B B 1 B 2 B 3 =B 3 =B 1 =B 2 A 4-bit Magnitude Comparator B 3 B B 2 B 1 B 2 B 1 B 3 A B

35 4-bit Magnitude Comparator A 4-bit Magnitude Comparator B B 1 B 2 B 3

36 Building Larger Comparators Try to build an 8-bit comparator Can we chain cascade (chain) together 4-bit magnitude comparators? Try to connect 4-bits of each input to a 4-bit comparator Problem: No way to communicate results of lower bits to higher bit comparator -A A 4-bit Magnitude Comparator A LSB < B LSB A LSB = B LSB A 7 -A 4 A 4-bit Magnitude Comparator A MSB < B MSB A MSB = B MSB B B B 3 -B B 1 B 2 A LSB > B LSB B 7 -B 4 B 1 B 2 A MSB > B MSB B 3 B 3 LSB s of A,B MSB s of A,B

37 Building Larger Comparators Remember if the MSB s of A are Greater-Than or Less-Than MSB s of B we don t need to look at LSB s Only when MSB s of A = MSB s of B do we need to look at the relationship of the LSB s MSB s of A > MSB s of B 11 xxxx = A 11 xxxx = B MSB s of A < MSB s of B 1 xxxx = A 111 xxxx = B MSB s of A = MSB s of B = A 11 1 = B A > B LSB s don t matter A < B LSB s don t matter Relationship of LSB s is now needed to find out whether,,

38 Building Larger Comparators Just add one of our merger circuits -A LSB s of A,B A 4-bit Magnitude Comparator LLT LEQ A 7 -A 4 MSB s of A,B A 4-bit Magnitude Comparator MLT MEQ B 3 -B B B 1 B 2 LGT B 7 -B 4 B B 1 B 2 MGT B 3 B 3 MLT MEQ MGT LGT LEQ LLT. Merger GT EQ LT

39 Building Larger Comparators Just add one of our merger circuits -A LSB s of A,B A 4-bit Magnitude Comparator LLT LEQ A 7 -A 4 A Mid Bits of A,B 4-bit Magnitude Comparator MidLT MidEQ 1 -A 8 MSB's of A,B A 4-bit Magnitude Comparator MLT MEQ B 3 -B B B 1 B 2 LGT B 7 -B 4 B B 1 B 2 MidGT B 11 -B 8 B B 1 B 2 MGT B 3 B 3 B 3 To make a block that can be repeated and chained arbitrarily, cut the design as shown: MLT MEQ MGT LGT LEQ LLT. Merger GT EQ LT MLT MEQ MGT LGT LEQ LLT. Merger GT EQ LT

40 Building Larger Comparators Solution: Add cascade inputs I, I, I, to each 4-bit comparator where the comparison of LSB s can be connected Cascaded inputs will only be passed when the MSB s are equal A A Comparison of less significant bits B B 1 74LS85 O O Comparison of more significant bits B B 1 74LS85 O O Overall comparison result B 2 B 2 B 3 O B 3 O I I I New cascaded inputs I I I Only use these inputs when MSB s are equal

41 4-bit Cascadable Comparator Below is the logic needed to add these cascaded inputs A A O O B B 1 B 2 B B 1 B 2 4-bit Magnitude Comparator O B 3 B 3 I I I

42 4-bit Cascadable Comparator Below is the logic needed to add these cascaded inputs A A O O B B 1 B 2 B B 1 B 2 4-bit Magnitude Comparator O B 3 I I B 3 Notice that all 3 of the cascaded inputs are qualified with from the MSB s. When =, the cascaded inputs are forced to I

43 4-bit Cascadable Comparator Below is the logic needed to add these cascaded inputs A A O O B B 1 B 2 B B 1 B 2 4-bit Magnitude Comparator O B 3 I I I B 3 If the MSB s of A are > or < the MSB s of B then the overall outputs are fully determined. Thus those outputs go into the final OR gate. If they are 1 then the output will be 1 no matter what the other input to the OR gate is.

44 Cascaded Comparator Example A = B = A O A O 1 1 B B 1 B 2 B 3 74LS85 O O B B 1 B 2 B 3 74LS85 O O 1 use initial values of 1 I I I I I I these input values have lower priority Since the MSB s of A > MSB s of B we don t need the results of the LSB comparator.

45 Cascaded Comparator Example A = B = A O A O B B 1 B 2 B 3 74LS85 O O B B 1 B 2 B 3 74LS85 O O use initial values of 1 I I I I I I these input values have lower priority Since the MSB s of A = MSB s of B the comparison of the LSB s determines the final output

46 XOR APPLICATIONS Mark Redekopp, All rights reserved

47 XOR Gate Review X Y Z XOR Z X Y X Y Z True if an odd # of inputs are true 2 input case: True if inputs are different

48 XOR Conditional Inverter If one input to an XOR gate is, the other input is passed If one input to an XOR gate is 1, the other input is inverted Use one input as a control input which can conditionally pass or invert the other input X Y Z Y Y

49 XOR / XNOR Equivalents XOR gate with Odd number of input/output inversions => XNOR gate Even number of input/output inversions => XOR gate X Y Z

50 Parity & Error Detection When digital data is transmitted there is some probability that a bit will be corrupted (flipped) We d like a way to detect an error so that the receiver can ask for a retransmission rather than using the wrong data We will attach an extra parity bit, P, to the data to help determine if there is an error A 111 P 11 P B

51 Even & Odd Parity Even Parity: All transmissions will contain an even number of 1 s We will choose even parity in example below Odd Parity: All transmissions will contain an odd number of 1 s A B Make P=1 to ensure even # of 1 s Receiver sees odd # of 1 s and knows there is an error

52 Generating & Checking Parity To generate even parity bit P at sender: P = 1 when odd number of 1 s in data This is nothing more than an XOR function To check if error at receiver Error = 1 when odd number of 1 s in data and parity bit message Again, nothing more than an XOR function A B