DS Tap Silicon Delay Line FEATURES PIN ASSIGNMENT. PIN DESCRIPTION TAP 1 TAP 5 TAP Output Number +5 Volts
|
|
- Wendy Rich
- 6 years ago
- Views:
Transcription
1 DS00 -Tap Silicon Delay Line FEATURES All-silicon time delay taps equally spaced Delay tolerance ± ns or ±%, whichever is greater Stable and precise over temperature and voltage range Leading and trailing edge accuracy Economical Auto-insertable, low profile Standard -pin DIP, -pin DIP, or -pin SOIC Tape and reel available for surface-mount Low-power CMOS TTL/CMOS compatible Vapor phase, IR and wave solderability Custom delays available P ASSIGNMENT TAP 0 9 Vcc TAP TAP DS00 -P DIP (00 MIL) TAP TAP 0 9 V CC TAP TAP DS00S -P SOIC (00 MIL) Vcc TAP TAP DS00M -P DIP (00 MIL) Quick turn prototypes Extended temperature range available DESCRIPTION The DS00 -Tap Silicon Delay Line provides five equally spaced taps with delays ranging from ns to 0 ns, with an accuracy of ± ns or ±%, whichever is greater. This device is offered in a standard -pin DIP making it compatible with existing delay line products. Space-saving -pin DIPs and -pin SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is achieved by the combination of a 00% silicon delay line and industry standard DIP and SOIC packaging. In order to maintain complete P DESCRIPTION TAP TAP Output Number V CC + Volts Ground No Connection Input pin compatibility, DIP packages are available with hybrid lead configurations. The DS00 reproduces the input logic level at each tap after the fixed delay specified by the dash number in Table. The device is designed with both leading and trailing edge accuracy. Each tap is capable of driving up to ten LS loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests and rapid delivery, call (). 09 /
2 LOGIC DIAGRAM Figure TAP TAP TAP 0% 0% 0% 0% 0% PART NUMBER DELAY TABLE (t PHL, t PLH ) Table PART NO. TAP TAP TAP DS00-0 ns ns ns ns 0 ns DS00- ns 0 ns ns 0 ns ns DS ns 0 ns 0 ns 0 ns 00 ns DS00- ns 0 ns ns 00 ns ns DS ns 0 ns 90 ns 0 ns 0 ns DS00- ns 0 ns 0 ns 0 ns ns DS ns 0 ns 0 ns 0 ns 00 ns DS ns 00 ns 0 ns 00 ns 0 ns Custom delays available 09 /
3 ABSOLUTE MAXIMUM RATGS* Voltage on Any Pin Relative to Ground -.0V to +.0V Operating Temperature 0 C to 0 C Storage Temperature - C to + C Soldering Temperature 0 C for 0 seconds Short Circuit Output Current 0 ma for second * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (0 C to 0 C; V CC =.0V ± %) PARAMETER SYMBOL TEST COND. M TYP MAX UNITS NOTES Supply Voltage V CC..00. V High Level Input Voltage V IH. V CC +0. V Low Level Input Voltage V IL V Input Leakage Current I I 0.0V < V I < V CC u A Active Current I CC V CC = Max; Period = Min. High Level Output Current I OH V CC = Min. V OH = Low Level Output Current I OL V CC = Min. V OL = ma -.0 ma ma AC ELECTRICAL CHARACTERISTICS (T A = C; V CC =.0V ± %) PARAMETER SYMBOL M TYP MAX UNITS NOTES Input Pulse Width t WI 0% of t PLH ns Input to Tap Delay (leading edge) t PLH Table ns,,, Input to Tap Delay (trailing edge) t PHL Table ns,,, Power-up Time t PU 00 ms Period (t WI ) ns CAPACITAE (T A = C) PARAMETER SYMBOL M TYP MAX UNITS NOTES Input Capacitance C 0 pf 09 /
4 NOTES:. All voltages are referenced to ground.. Measured with outputs open.. V CC = C. Delays accurate on both rising and falling edges within ± ns or ±%, whichever is greater.. See Test Conditions.. The combination of temperature variations from C to 0 C or C to 0 C and voltage variations from.0v to.v or.0v to.v may produce an additional input-to-tap delay shift of ±. ns or ±%, whichever is greater.. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP slows down, all other taps will also slow down; TAP can never be faster than TAP.. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-sensitive (decoupling, layout, etc.). TERMOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following t WI (Pulse Width): The elapsed time on the pulse between the.v point on the leading edge and the.v point on the trailing edge, or the.v point on the trailing edge and the.v point on the leading edge. t RISE (Input Rise Time): The elapsed time between the 0% and the 0% point on the leading edge of the input t FALL (Input Fall Time): The elapsed time between the 0% and the 0% point on the trailing edge of the input t PLH (Time Delay, Rising): The elapsed time between the.v point on the leading edge of the input pulse and the.v point on the leading edge of any tap output t PHL (Time Delay, Falling): The elapsed time between the.v point on the trailing edge of the input pulse and the.v point on the trailing edge of any tap output TEST SETUP DESCRIPTION Figure illustrates the hardware configuration used for measuring the timing parameters on the DS00. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (0 ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE bus. TEST CONDITIONS PUT: Ambient Temperature C ± C Supply Voltage (V CC ).0V ± 0.V Input Pulse High =.0V ± 0.V Low = 0.0V ± 0.V Source Impedance 0 ohm maximum Rise and Fall Time.0 ns maximum Pulse Width 00 ns Period µs OUTPUT: Each output is loaded with the equivalent of a F0 input gate. Delay is measured at the.v level on the rising and falling edge. NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. 09 /
5 TIMG DIAGRAM: SILICON DELAY LE Figure PERIOD t RISE t FALL V IH V IL 0.V.V.V.V.V 0.V.V t WI t WI t PHL t PLH.V.V TAP DALLAS SEMICONDUCTOR TEST CIRCUIT Figure PULSE GENERATOR START Z O 0 TIP TIME TERVAL COUNTER STOP TIP (TIME TERVAL PROBE) DEVICE UNDER TEST VHF SWITCH CONTROL UNIT 09 /
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP
More informationCD54HC11, CD74HC11, CD54HCT11, CD74HCT11
CDHC, CD7HC, CDHCT, CD7HCT Data sheet acquired from Harris Semiconductor SCHS7E August 997 - Revised September 00 High-Speed CMOS Logic Triple -Input AND Gate [ /Title (CD HCT, CD7 HC, CD7 HCT ) /Subject
More informationNTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
More informationBCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA
TECHNICAL DATA BCD-TO-DECIMAL DECODER HIGH-OLTAGE SILICON-GATE CMOS IW4028B The IW4028B types are BCD-to-decimal or binary-tooctal decoders consisting of buffering on all 4 inputs, decoding-logic gates,
More informationCD54/74HC32, CD54/74HCT32
Data sheet acquired from Harris Semiconductor SCHS7A September 997 - Revised May 000 CD/7HC, CD/7HCT High Speed CMOS Logic Quad -Input OR Gate [ /Title (CD HCT, CD7 HC, CD7 HCT ) /Subject High Features
More informationMM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
More informationNTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register
NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package
More informationMM74HC151 8-Channel Digital Multiplexer
8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation
More informationMM74HC157 Quad 2-Input Multiplexer
Quad 2-Input Multiplexer General Description The MM74HC157 high speed Quad 2-to-1 Line data selector/multiplexers utilizes advanced silicon-gate CMOS technology. It possesses the high noise immunity and
More informationMM74HC373 3-STATE Octal D-Type Latch
MM74HC373 3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power
More informationDual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
TECHNICAL DATA IN74ACT74 Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT74 is identical in pinout to the LS/ALS74, HC/HCT74. The IN74ACT74 may be used as a level converter
More informationCD54/74HC147, CD74HCT147. High Speed CMOS Logic 10-to-4 Line Priority Encoder. Features. [ /Title (CD74 HC147, CD74 HCT14 7) /Subject
CD/7HC7, CD7HCT7 Data sheet acquired from Harris Semiconductor SCHS9B September 997 - Revised March 00 High 0-to- Encoder [ /Title (CD7 HC7, CD7 HCT 7) /Subject (High 0-to- Encode r) /Autho r () /Keywords
More information74HC86. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS
Quad 2 Input Exclusive OR Gate MARKING DIAGRAMS High Performance Silicon Gate CMOS The is identical in pinout to the LS86. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
More informationPO3B14A. Description. Truth Table. High Bandwidth Potato Chip V CC N.C. EN EN S 1 A 3 B 3 B 2 A 2 A 1 B 1 Y A Y B GND
www.potatosemi.com FEATURES: Patented technology High signal -3db passing bandwidth at 1.2GHz Near-Zero propagation delay VCC = 1.65V to 3.6V Ultra-Low Quiescent Power: 0.1 A typical Ideally suited for
More informationMM74HC373 3-STATE Octal D-Type Latch
3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
More informationMM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity
More informationMM74HC573 3-STATE Octal D-Type Latch
MM74HC573 3-STATE Octal D-Type Latch General Description The MM74HC573 high speed octal D-type latches utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low
More information74LV393 Dual 4-bit binary ripple counter
INTEGRATED CIRCUITS Supersedes data of 1997 Mar 04 IC24 Data Handbook 1997 Jun 10 FEATURES Optimized for Low Voltage applications: 1.0 to.6v Accepts TTL input levels between V CC = 2.7V and V CC =.6V Typical
More informationINTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1998 Apr 13 IC24 Data Handbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels
More informationMM74HC4020 MM74HC Stage Binary Counter 12-Stage Binary Counter
February 1984 Revised February 1999 MM74HC4020 MM74HC4040 14-Stage Binary Counter 12-Stage Binary Counter General Description The MM74HC4020, MM74HC4040, are high speed binary ripple carry counters. These
More information1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS The IN74ACT138 is identical in pinout to the LS/ALS138, HC/HCT138. The IN74ACT138 may be used as a level converter for interfacing TTL or NMOS
More informationINTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28
INTEGRATED CIRCUITS -to-8 line decoder/demultiplexer; inverting 998 Apr 8 FEATURES Wide supply voltage range of. to. V In accordance with JEDEC standard no. 8-A Inputs accept voltages up to. V CMOS lower
More informationDS K x 8 Static RAM FEATURES PIN ASSIGNMENT PIN DESCRIPTION
8K x 8 Static RAM FEATURES Low power CMOS design Standby current 50 na max at t A = 25 C V CC = 3.0V 100 na max at t A = 25 C V CC = 5.5V 1 µa max at t A = 60 C V CC = 5.5V Full operation for V CC = 4.5V
More informationMM74HC374 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
More informationMM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
More informationNTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability
More informationMM74HC32 Quad 2-Input OR Gate
Quad 2-Input OR Gate General Description The MM74HC32 OR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
More informationMM74HC74A Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part.
More informationMM74HC00 Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption
More informationINTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook
INTEGRATED CIRCUITS 1998 Jun 23 IC24 Data Handbook FEATURES Optimized for Low Voltage applications: 1.0 to 5.5V Accepts TTL input levels between V CC = 2.7V and V CC = 3.6V Typical V OLP (output ground
More informationCD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
CD/HC, CD/HCT, CD/HC, CDHCT Data sheet acquired from Harris Semiconductor SCHSD November - Revised October 00 High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting [ /Title
More informationPI4GTL bit bidirectional low voltage translator
Features 2-bit bidirectional translator Less than 1.5 ns maximum propagation delay to accommodate Standard mode and Fast mode I2Cbus devices and multiple masters Allows voltage level translation between
More informationMM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 2005 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
More informationINTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels
More informationINTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook
INTEGRATED CIRCUITS Octal D-type flip-flop with reset; positive-edge trigger 1997 Apr 07 IC24 Data Handbook FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V
More informationMM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS
More information1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS The IN74AC138 is identical in pinout to the LS/ALS138, HC/HCT138. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
More informationPO3B20A. High Bandwidth Potato Chip
FEATURES: Patented technology High signal -3db passing bandwidth at 1.6GHz Near-Zero propagation delay CC = 1.65 to 3.6 Ultra-Low Quiescent Power: 0.1 A typical Ideally suited for low power applications
More informationCD4028BC BCD-to-Decimal Decoder
BCD-to-Decimal Decoder General Description The is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A,
More informationMM74HC251 8-Channel 3-STATE Multiplexer
8-Channel 3-STATE Multiplexer General Description The MM74HC251 8-channel digital multiplexer with 3- STATE outputs utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and
More informationMM74HC08 Quad 2-Input AND Gate
Quad 2-Input AND Gate General Description The MM74HC08 AND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
More informationCD54/74HC30, CD54/74HCT30
CD/7HC0, CD/7HCT0 Data sheet acquired from Harris Semiconductor SCHSA August 997 - Revised May 000 High Speed CMOS Logic 8-Input NAND Gate [ /Title (CDH C0, CD7H C0, CD7H CT0) /Subject High peed MOS ogic
More informationCD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
More informationMM74HC154 4-to-16 Line Decoder
4-to-16 Line Decoder General Description The MM74HC154 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses high
More informationMM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 1999 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
More information74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 4HC4 is identical in pinout to the LS4. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
More informationMM74HCT540 MM74HCT541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
February 1984 Revised February 1999 MM74HCT540 MM74HCT541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer General Description The MM74HCT540 and MM74HCT541 3-STATE buffers utilize advanced silicon-gate
More informationOctal 3-State Noninverting Transparent Latch
SL74HC73 Octal 3-State Noninverting Traparent Latch High-Performance Silicon-Gate CMOS The SL74HC73 is identical in pinout to the LS/ALS73. The device inputs are compatible with standard CMOS outputs;
More informationMM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
More informationMM74HC244 Octal 3-STATE Buffer
MM74HC244 Octal 3-STATE Buffer General Description The MM74HC244 is a non-inverting buffer and has two active low enables (1G and 2G); each enable independently controls 4 buffers. This device does not
More informationCD54HC257, CD74HC257, CD54HCT257, CD74HCT257
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Data sheet acquired from Harris Semiconductor SCHS171D November 1997 - Revised October 2003 High-Speed CMOS Logic Quad 2-Input Multiplexer with Three-State
More informationThe 74HC21 provide the 4-input AND function.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
More informationMM74HCT08 Quad 2-Input AND Gate
MM74HCT08 Quad 2-Input AND Gate General Description The MM74HCT08 is a logic function fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS low quiescent
More informationCD4013BC Dual D-Type Flip-Flop
Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each
More informationSGM7SZ00 Small Logic Two-Input NAND Gate
GENERAL DESCRIPTION The SGM7SZ00 is a single two-input NAND gate from SGMICRO s Small Logic series. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. September 2001 S7C256 5V/3.3V 32K X 8 CMOS SRM (Common I/O) Features S7C256
More informationCD4024BC 7-Stage Ripple Carry Binary Counter
CD4024BC 7-Stage Ripple Carry Binary Counter General Description The CD4024BC is a 7-stage ripple-carry binary counter. Buffered outputs are externally available from stages 1 through 7. The counter is
More informationUNISONIC TECHNOLOGIES CO., LTD U74HC244
UNISONIC TECHNOLOGIES CO., LTD OCTAL BUFFER AND LINE DRIVER WITH 3-STATE OUTPUT DESCRIPTION DIP-20 The are octal buffer and line drivers with non-inverting 3-state outputs. When n OE is High, the outputs
More informationMM74HC139 Dual 2-To-4 Line Decoder
MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.
More informationMM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
September 1983 Revised February 1999 MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer General Description The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate
More information74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting
3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible
More informationUNISONIC TECHNOLOGIES CO., LTD U74LVC1G125
UNISONIC TECHNOLOGIES CO., LTD U74LVC1G125 BUS BUFFER/LINE DRIVER 3-STATE DESCRIPTION The U74LVC1G125 is a single bus buffer/line driver with 3-state output. When the output enable ( ΟΕ ) is high the output
More informationCD74HC147, CD74HCT147
Data sheet acquired from Harris Semiconductor SCHS149 September 1997 CD74HC147, CD74HCT147 High Speed CMOS Logic 10-to-4 Line Priority Encoder [ /Title (CD74 HC147, CD74 HCT14 7) /Subject (High Speed CMOS
More informationUNISONIC TECHNOLOGIES CO., LTD
UNISONIC TECHNOLOGIES CO., LTD SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT DESCRIPTION The U74AUC1G126 is single bus buffer gate with 3-state output. The output is disabled When the output enable (OE) is
More informationUNISONIC TECHNOLOGIES CO., LTD U74HC14
UNISONIC TECHNOLOGIES CO., LTD U74HC14 HIGH-SPEED CMOS LOGIC HEX INVERTING SCHMITT TRIGGER DESCRIPTION The UTC U74HC14 each contain six inverting Schmitt triggers in one package. Each of them perform the
More informationCD4021BC 8-Stage Static Shift Register
8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages.
More information74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting. Product data sheet
3-to-8 line decoder, demultiplexer with address latches; inverting Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky
More informationNTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register
NTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register Description: The NTE4035B is a 4 bit shift register in a 16 Lead DIP type package constructed with MOS P Channel an N Channel
More informationCD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset
October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits
More informationMM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high
More informationCD4528BC Dual Monostable Multivibrator
Dual Monostable Multivibrator General Description The CD4528BC is a dual monostable multivibrator. Each device is retriggerable and resettable. Triggering can occur from either the rising or falling edge
More informationINTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook
INTEGRATED CIRCUITS Triple 3-Input AND gate 1991 Feb 08 IC05 Data Handbook TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 5.5ns 1.3mA PIN CONFIGURATION 1A 1 1B 2 14 13 V CC 1C ORDERING INFORMATION
More information2 Input NAND Gate L74VHC1G00
Input NAND Gate The is an advanced high speed CMOS input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
More informationUNISONIC TECHNOLOGIES CO., LTD
UNISONIC TECHNOLOGIES CO., LTD QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS DESCRIPTION The U74LVC125A consists of four bus buffers with 3-state output controlled by enable input ( ΟΕ ), when ΟΕ is high,
More informationMM74HC138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features
More informationCD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed
More information74LS393 Dual 4-Bit Binary Counter
74LS393 Dual 4-Bit Binary Counter General Description Each of these monolithic circuits contains eight masterslave flip-flops and additional gating to implement two individual four-bit counters in a single
More informationMM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general
More informationFIN1531 5V LVDS 4-Bit High Speed Differential Driver
FIN1531 5V LVDS 4-Bit High Speed Differential Driver General Description This quad driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver
More informationMM74HCT138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits
More informationCD74HC93, CD74HCT93. High Speed CMOS Logic 4-Bit Binary Ripple Counter. Description. Features. Pinout. Ordering Information
Data sheet acquired from Harris Semiconductor SCHS138 August 1997 CD74HC93, CD74HCT93 High Speed CMOS Logic 4-Bit Binary Ripple Counter [ /Title (CD74 HC93, CD74 HCT93 ) /Subject High peed MOS ogic -Bit
More informationUNISONIC TECHNOLOGIES CO., LTD U74HC164
UNISONIC TECHNOLOGIES CO., LTD 8-BIT SERIAL-IN AND PARALLEL-OUT SHIFT REGISTER DIP-14 DESCRIPTION The is an 8-bit edge-triggered shift registers with serial input and parallel output. A LOW-to-HIGH transition
More informationUNISONIC TECHNOLOGIES CO., LTD
UNISONIC TECHNOLOGIES CO., LTD BUS BUFFER/LINE DRIVER 3-STATE DESCRIPTION The U74LVC1G125 is a single bus buffer/line driver with 3-state output. When the output enable ( ΟΕ ) is high the output will be
More informationFeatures. Functional Diagrams, Pin Configurations, and Truth Tables
Features Low On-Resistance (Ω typ) Minimizes Distortion and Error Voltages Low Glitching Reduces Step Errors in Sample-and-Holds. Charge Injection, pc typ Single-Supply Operation (+.V to +1V) Improved
More informationObsolete Product(s) - Obsolete Product(s)
BCD TO DECIMAL DECODER HIGH SPEED : t PD = 14ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
More informationCD54/74AC153, CD54/74ACT153
CD4/74AC13, CD4/74ACT13 Data sheet acquired from Harris Semiconductor SCHS237A September 1998 - Revised May 2000 Dual 4-Input Multiplexer Features Description [ /Title (CD74 AC13, CD74 ACT1 3) /Subject
More informationDS34C87T CMOS Quad TRI-STATE Differential Line Driver
DS34C87T CMOS Quad TRI-STATE Differential Line Driver General Description The DS34C87T is a quad differential line driver designed for digital data transmission over balanced lines The DS34C87T meets all
More informationUNISONIC TECHNOLOGIES CO., LTD L16B45 Preliminary CMOS IC
UNISONIC TECHNOLOGIES CO., LTD L16B45 Preliminary CMOS IC 16-BIT CONSTANT CURRENT LED SINK DRIVER DESCRIPTION The UTC L16B45 is designed for LED displays. UTC L16B45 contains a serial buffer and data latches
More information74HC257; 74HCT257. Quad 2-input multiplexer; 3-state
Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has four identical 2-input multiplexers with
More informationCD54/74HC164, CD54/74HCT164
Data sheet acquired from Harris Semiconductor SCHS155A October 1997 - Revised May 2000 CD54/74HC164, CD54/74HCT164 High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register Features Description
More information74LVC374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS
INTEGRATE CIRCUITS Octal -type flip-flop; positive edge-trigger (3-State) Supersedes data of February 1996 IC24 ata Handbook 1997 Mar 12 FEATURES Wide supply voltage range of 1.2V to 3.6V In accordance
More informationSGM7SZ32 Small Logic Two-Input OR Gate
Preliminary Datasheet GENERL DESCRIPTION The is a single two-input OR gate from SGMICRO's Small Logic series. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high
More informationFSUSB31 Low-Power 1-Port Hi-Speed USB 2.0 (480Mbps) Switch
Low-Power 1-Port Hi-Speed USB 2.0 (480Mbps) Switch Features Low On capacitance, 3.7pF (typical) Low On resistance, 6.5Ω (typical) Low power consumption (1µA maximum) 10µA maximum I CCT over and expanded
More informationCD4514BC CD4515BC 4-Bit Latched/4-to-16 Line Decoders
CD4514BC CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed
More informationMM54HCT193 MM74HCT193 Synchronous Binary Up Down Counters
MM54HCT193 MM74HCT193 Synchronous Binary Up Down Counters General Description These high speed synchronous counters utilize advanced silicon-gate CMOS technology to achieve the high noise immunity and
More information12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS
TECHNICAL DATA IW4040B 2-Stage Binary Ripple Counter High-oltage Silicon-Gate CMOS The IW4040B is ripple-carry binary counter. All counter stages are masterslave flip-flops. The state of a counter advances
More information74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter
Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output
More informationNC7SV74 TinyLogic ULP-A D-Type Flip-Flop with Preset and Clear
NC7SV74 TinyLogic ULP-A D-Type Flip-Flop with Preset and Clear Features Space-saving US8 surface-mount package MicroPak Pb-free leadless package 0.9V to 3.6V V CC supply operation 3.6V over-voltage tolerant
More information74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.
Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
More informationINTEGRATED CIRCUITS. 74LV259 8-bit addressable latch. Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 May 20 FEATURES Optimized for low voltage applicatio: 1.0 to 3.6 V Accepts TTL input levels between = 2.7 V and = 3.6 V Typical
More information