VNL5090N3-E, VNL5090S5-E

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1 OMNIFET III fully protected low-side driver Datasheet - production data 2 Features Type V clamp R DS(on) I D VNL5090N3-E VNL5090S5-E 1 2 SOT SO-8 41 V 90 mω 13 A Automotive qualified Drain current: 13 A ESD protection Overvoltage clamp Thermal shutdown Current and power limitation Very low standby current Very low electromagnetic susceptibility Compliant with European directive 2002/95/EC Open drain status output (VNL5090S5-E only) Specially intended for 2 x R10W or 4 x R5W automotive signal lamps Description The VNL5090N3-E and VNL5090S5-E are monolithic devices made using STMicroelectronics VIPower technology, intended for driving resistive or inductive loads with one side connected to the battery. Built-in thermal shutdown protects the chip from overtemperature and short-circuit. Output current limitation protects the devices in an overload condition. In case of long duration overload, the device limits the dissipated power to a safe level up to thermal shutdown intervention.thermal shutdown, with automatic restart, allows the devices to recover normal operation as soon as a fault condition disappears. Fast demagnetization of inductive loads is achieved at turn-off. Table 1. Devices summary Package Tube Order codes Tape and reel SOT-223 VNL5090N3TR-E SO-8 VNL5090S5-E VNL5090S5TR-E April 2015 DocID Rev 7 1/28 This is information on a product in full production.

2 Contents VNL5090N3-E, VNL5090S5-E Contents 1 Block diagrams and pins configurations Electrical specifications Absolute maximum ratings Thermal data Electrical characteristics Application information MCU I/O protection Package and PC board thermal data SOT-223 thermal data SO-8 thermal data Package and packing information ECOPACK SOT-223 mechanical data SO-8 mechanical data SOT-223 packing information SO-8 packing information Revision history /28 DocID Rev 7

3 List of tables List of tables Table 1. Devices summary Table 2. Pin function Table 3. Suggested connections for unused and N.C. pins Table 4. Absolute maximum ratings Table 5. Thermal data Table 6. PowerMOS section Table 7. Source drain diode Table 8. Input section Table 9. Status pin (VNL5090S5-E only) Table 10. Logic input (VNL5090S5-E only) Table 11. Openload detection (VNL5090S5-E only) Table 12. Supply section (VNL5090S5-E only) Table 13. Switching characteristics Table 14. Protection and diagnostics Table 15. Truth table (VNL5090S5-E only) Table 16. SOT-223 thermal parameters Table 17. SO-8 thermal parameters Table 18. SOT-223 mechanical data Table 19. SO-8 mechanical data Table 20. Document revision history DocID Rev 7 3/28 3

4 List of figures VNL5090N3-E, VNL5090S5-E List of figures Figure 1. VNL5090N3-E block diagram Figure 2. VNL5090S5-E block diagram Figure 3. VNL5090N3-E current and voltage conventions Figure 4. VNL5090S5-E current and voltage conventions Figure 5. Configuration diagrams (top view) Figure 6. Switching characteristics Figure 7. VNL5090N3-E application schematic Figure 8. VNL5090S5-E application schematic Figure 9. Maximum demagnetization energy (V CC = 16 V) Figure 10. SOT-223 PC board Figure 11. SOT-223 Rthj-amb vs PCB copper area in open box free air condition Figure 12. SOT-223 thermal impedance junction ambient single pulse Figure 13. Thermal fitting model of a LSD in SOT Figure 14. SO-8 PC board Figure 15. SO-8 Rthj-amb vs PCB copper area in open box free air condition Figure 16. SO-8 thermal impedance junction ambient single pulse Figure 17. Thermal fitting model of a LSD in SO Figure 18. SOT-223 package dimensions Figure 19. SO-8 package dimensions Figure 20. SOT-223 tape and reel shipment (suffix TR ) Figure 21. SO-8 tube shipment (no suffix) Figure 22. SO-8 tape and reel shipment (suffix TR ) /28 DocID Rev 7

5 Block diagrams and pins configurations 1 Block diagrams and pins configurations Figure 1. VNL5090N3-E block diagram Figure 2. VNL5090S5-E block diagram DocID Rev 7 5/28 27

6 Block diagrams and pins configurations VNL5090N3-E, VNL5090S5-E Table 2. Pin function Name Function INPUT DRAIN SOURCE Voltage controlled input pin with hysteresis, CMOS compatible; It controls output switch state (1) PowerMOS drain PowerMOS source and ground reference for the control section SUPPLY VOLTAGE Supply voltage connected to the signal part (5 V) STATUS Open drain digital diagnostic pin (2) 1. Internally connected to V supply in the VNL5090N3-E 2. Valid for VNL5090S5-E only. Figure 3. VNL5090N3-E current and voltage conventions Figure 4. VNL5090S5-E current and voltage conventions 6/28 DocID Rev 7

7 Block diagrams and pins configurations Figure 5. Configuration diagrams (top view) SOT-223 SO-8 Table 3. Suggested connections for unused and N.C. pins Connection / pin Status N.C. Input Floating X (1) X X To ground Not allowed X Through 10 kω resistor 1. X: do not care. DocID Rev 7 7/28 27

8 Electrical specifications VNL5090N3-E, VNL5090S5-E 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in the Table 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Absolute maximum ratings Symbol Parameter SOT-223 Value SO-8 Unit V DS Drain-source voltage (V IN = 0 V) Internally clamped V I D DC drain current Internally limited A -I D Reverse DC drain current 12.5 A I S DC supply current -1 to 10 ma I IN DC input current -1 to 10 ma I STAT DC status current -1 to 10 ma V ESD1 V ESD2 Electrostatic discharge (R = 1.5 kω; C = 100 pf) DRAIN SUPPLY, INPUT, STATUS Electrostatic discharge on output pin only (R = 330 Ω, C = 150 pf) V V 2000 V T j Junction operating temperature -40 to 150 C T stg Storage temperature -55 to 150 C E AS Single pulse avalanche energy (L = 1.1 m, T j = 150 C, R L = 0, I OUT = I liml ) 50 mj 2.2 Thermal data Symbol Parameter Table 5. Thermal data SOT-223 R thj-amb Thermal resistance junction-ambient 147 (1) Maximum value SO-8 Unit 102 C/W 1. When mounted on a standard single-sided FR4 board with 0.5 cm 2 of Cu (at least 35 µm thick) connected to all DRAIN pins 8/28 DocID Rev 7

9 Electrical specifications 2.3 Electrical characteristics Values specified in this section are for V supply = V IN = 4.5 V to 5.5 V, -40 C < T j < 150 C, unless otherwise stated. Table 6. PowerMOS section Symbol Parameter Test conditions Min. Typ. Max. Unit V supply Operating supply voltage V I D = 1.6 A; T j = 25 C; V supply = V IN = 5 V 90 R ON ON-state resistance I D = 1.6 A; T j = 150 C; V supply = V IN = 5 V 180 mω I D = 1.6 A; T j = 150 C; V supply = V IN = 4.5 V (1) 190 V CLAMP Drain-source clamp voltage V IN = 0 V; I D = 1.6 A V V CLT Drain-source clamp threshold voltage V IN = 0 V; I D = 2 ma 36 V I DSS OFF-state output current 1. Valid only for VNL5090N3-E. V IN = 0 V; V DS = 13 V; T j = 25 C V IN = 0 V; V DS = 13 V; T j = 125 C µa Table 7. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit V SD Forward on voltage I D = 1.6 A; V IN = 0 V 0.8 V Table 8. Input section (1) Symbol Parameter Test conditions Min. Typ. Max. Unit I ISS Supply current from input pin ON-state: V supply = V IN = 5 V; V DS = 0 V µa I S = 1 ma V ICL Input clamp voltage V I S = -1 ma -0.7 V INT Input threshold voltage V DS = V IN ; I D = 1 ma V 1. Valid for VNL5090N3-E option (input and supply pins connected together) Table 9. Status pin (VNL5090S5-E only) Symbol Parameter Test conditions Min. Typ. Max. Unit V STAT Status low output voltage I STAT = 1 ma 0.5 V I LSTAT Status leakage current Normal operation, V STAT = 5 V 10 µa DocID Rev 7 9/28 27

10 Electrical specifications VNL5090N3-E, VNL5090S5-E Table 9. Status pin (VNL5090S5-E only) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit C STAT Status pin input capacitance V STCL Status clamp voltage Normal operation, V STAT = 5 V I STAT = 1 ma I STAT = -1 ma pf V Table 10. Logic input (VNL5090S5-E only) Symbol Parameter Test conditions Min. Typ. Max. Unit V IL Low-level input voltage 0.9 V I IL Low-level input current V IN = 0.9 V 1 µa V I igh-level input voltage 2.1 V I I igh-level input current V IN = 2.1 V 10 µa V I(hyst) Input hysteresis voltage 0.13 V V ICL Input clamp voltage I IN = 1 ma I IN = -1 ma -0.7 V Table 11. Openload detection (VNL5090S5-E only) Symbol Parameter Test conditions Min. Typ. Max. Unit V Ol t d(oloff) Openload OFF-state voltage detection threshold Delay between INPUT falling edge and STATUS falling edge in openload condition V IN = 0 V V I OUT = 0 A µs Table 12. Supply section (VNL5090S5-E only) Symbol Parameter Test conditions Min. Typ. Max. Unit I S Supply current OFF-state; T j = 25 C; V IN = V DRAIN = 0 V; ON-state; V IN = 5 V; V DS = 0 V µa V SCL Supply clamp voltage I SCL = 1 ma I SCL = -1 ma -0.7 V 10/28 DocID Rev 7

11 Electrical specifications Table 13. Switching characteristics SOT-223 (1) SO-8 Symbol Parameter Test conditions Min. Typ. Max Min. Typ. Max. Unit t d(on) t d(off) t r t f W ON W OFF Turn-on delay time Turn-off delay time Rise time Fall time Switching energy losses at turn-on Switching energy losses at turn-off R L = 8.2 Ω, V CC = 13 V (2) 8 8 µs R L = 8.2 Ω, V CC = 13 V (2) µs R L = 8.2 Ω, V CC = 13 V (2) µs R L = 8.2 Ω, V CC = 13 V (2) µs R L = 8.2 Ω, V CC = 13 V (2) µj R L = 8.2 Ω, V CC = 13 V (2) µj V V supply = V IN 5.5 V 2. See Figure 6: Switching characteristics Note: See Figure 7: VNL5090N3-E application schematic and Figure 8: VNL5090S5-E application schematic Table 14. Protection and diagnostics Symbol Parameter Test conditions (1) I lim I liml DC short-circuit current Short-circuit current during thermal cycling 1. V supply = V input in VNL5090N3-E version. V DS = 13 V; V supply = V IN = 5 V V DS = 13 V; T R < T j < T TSD ; V supply = V IN = 5 V Min. Typ. Max. Unit A 8 A t dliml Step response current limit V DS = 13 V; V input = 5 V 44 µs T TSD Shutdown temperature C T (2) R Reset temperature T RS + 1 T RS + 5 C T (3) Thermal reset of RS STATUS 135 C T YST Thermal hysteresis (T TSD - T R ) 2. Valid for VNL5090S5-E option. 7 C DocID Rev 7 11/28 27

12 Electrical specifications VNL5090N3-E, VNL5090S5-E Table 15. Truth table (VNL5090S5-E only) Conditions INPUT DRAIN STATUS Normal operation L L Current limitation L X Overtemperature L L Undervoltage L X X Output voltage < V OL L L L L Figure 6. Switching characteristics 12/28 DocID Rev 7

13 Application information 3 Application information Figure 7. VNL5090N3-E application schematic Figure 8. VNL5090S5-E application schematic DocID Rev 7 13/28 27

14 Application information VNL5090N3-E, VNL5090S5-E 3.1 MCU I/O protection ST suggests to insert a resistor (R prot ) in line to prevent the microcontroller I/O pins from latching up (a). The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the LSD I/Os (input levels compatibility) with the latch-up limit of microcontroller I/Os: Equation ( V OμC V I ) R I prot latchup I I max Let: I latchup > 20 ma V OµC > 4.5 V 35 Ω R prot 100 KΩ Then, the recommended value is R prot = 1 KΩ Figure 9 shows the turn-off current drawn during the demagnetization. a. In case of negative transient on the drain pin. 14/28 DocID Rev 7

15 Application information Figure 9. Maximum demagnetization energy (V CC = 16 V) DocID Rev 7 15/28 27

16 Package and PC board thermal data VNL5090N3-E, VNL5090S5-E 4 Package and PC board thermal data 4.1 SOT-223 thermal data Figure 10. SOT-223 PC board GAPGCFT00530 Note: Layout condition of R th and Z th measurements (PCB FR4 area = 30 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 µm, copper areas: from minimum pad lay-out to 0.8 cm 2 ). Figure 11. SOT-223 R thj-amb vs PCB copper area in open box free air condition 16/28 DocID Rev 7

17 Package and PC board thermal data Figure 12. SOT-223 thermal impedance junction ambient single pulse Equation 2: pulse calculation formula Z Tδ = R T δ + Z Ttp ( 1 δ) where δ = t P /T Figure 13. Thermal fitting model of a LSD in SOT-223 GAPGCFT00533 Note: The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. DocID Rev 7 17/28 27

18 Package and PC board thermal data VNL5090N3-E, VNL5090S5-E Table 16. SOT-223 thermal parameters Area/island (cm 2 ) Footprint 2 R1 ( C/W) 0.8 R2 ( C/W) 1 R3 ( C/W) 4.5 R4 ( C/W) 24 R5 ( C/W) 0.1 R6 ( C/W) C1 (W.s/ C) C2 (W.s/ C) C3 (W.s/ C) 0.03 C4 (W.s/ C) 0.16 C5 (W.s/ C) 1000 C6 (W.s/ C) /28 DocID Rev 7

19 Package and PC board thermal data 4.2 SO-8 thermal data Figure 14. SO-8 PC board GAPGCFT00534 Note: Layout condition of R th and Z th measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 µm (front and back side), Copper areas: from minimum pad lay-out to 2 cm 2 ). Figure 15. SO-8 R thj-amb vs PCB copper area in open box free air condition DocID Rev 7 19/28 27

20 Package and PC board thermal data VNL5090N3-E, VNL5090S5-E Figure 16. SO-8 thermal impedance junction ambient single pulse Equation 3: pulse calculation formula Z Tδ = R T δ + Z Ttp ( 1 δ) where δ = t P /T Figure 17. Thermal fitting model of a LSD in SO-8 GAPGCFT00533 Note: The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 20/28 DocID Rev 7

21 Package and PC board thermal data Table 17. SO-8 thermal parameters Area/island (cm 2 ) Footprint 2 R1 ( C/W) 0.8 R2 ( C/W) 2.7 R3 ( C/W) 3.5 R4 ( C/W) 21 R5 ( C/W) 16 R6 ( C/W) C1 (W.s/ C) C2 (W.s/ C) C3 (W.s/ C) C4 (W.s/ C) C5 (W.s/ C) 0.35 C6 (W.s/ C) DocID Rev 7 21/28 27

22 Package and packing information VNL5090N3-E, VNL5090S5-E 5 Package and packing information 5.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 5.2 SOT-223 mechanical data Figure 18. SOT-223 package dimensions /28 DocID Rev 7

23 Package and packing information Table 18. SOT-223 mechanical data DIM. mm. inch Min. Typ. Max. Min. Typ. Max. A B B c D e e E V 10 (max) A SO-8 mechanical data Figure 19. SO-8 package dimensions GAPGCFT00145 DocID Rev 7 23/28 27

24 Package and packing information VNL5090N3-E, VNL5090S5-E Table 19. SO-8 mechanical data Symbol Millimeters Min. Typ. Max. A 1.75 A A b c D (1) E E1 (2) e 1.27 h L L k 0 8 ccc Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15 mm in total (both side). 2. Dimension E1 does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. 24/28 DocID Rev 7

25 Package and packing information 5.4 SOT-223 packing information The devices can be packed in tube or tape and reel shipments (see the Table 1: Devices summary on page 1). Figure 20. SOT-223 tape and reel shipment (suffix TR ) Reel dimensions Base Q.ty 1000 Bulk Q.ty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb Tape width W 12 Tape ole Spacing P0 (± 0.1) 4 Component Spacing P 8 ole Diameter D (+ 0.1/-0) 1.5 ole Diameter D1 (min) 1.5 ole Position F (± 0.05) 5.5 Compartment Depth K (max) 4.5 ole Spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top cover tape No components 500mm min Components Empty components pockets saled with cover tape. No components 500mm min User direction of feed DocID Rev 7 25/28 27

26 Package and packing information VNL5090N3-E, VNL5090S5-E 5.5 SO-8 packing information Figure 21. SO-8 tube shipment (no suffix) B C A Base q.ty 100 Bulk q.ty 2000 Tube length (± 0.5) 532 A 3.2 B 6 C (± 0.1) 0.6 All dimensions are in mm. Figure 22. SO-8 tape and reel shipment (suffix TR ) Reel dimensions Base q.ty 2500 Bulk q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4 All dimensions are in mm. Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb Tape width W 12 Tape hole spacing P0 (± 0.1) 4 Component spacing P 8 ole diameter D (+ 0.1/-0) 1.5 ole diameter D1 (min) 1.5 ole position F (± 0.05) 5.5 Compartment depth K (max) 4.5 ole spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top cover tape No components 500mm min Components Empty components pockets saled with cover tape. No components 500mm min User direction of feed 26/28 DocID Rev 7

27 Revision history 6 Revision history Table 20. Document revision history Date Revision Changes 15-Dec Initial release. 20-Jan Table 4: Absolute maximum ratings: -I D : updated value 18-Apr Updated Features list 10-Aug Updated Table 13: Switching characteristics 18-Sep Updated disclaimer. 13-Nov Updated Features list Table 8: Input section: I ISS : updated maximum value Table 12: Supply section (VNL5090S5-E only): I IS : updated maximum value Updated Figure 7: VNL5090N3-E application schematic and Figure 8: VNL5090S5-E application schematic Updated Section 3.1: MCU I/O protection 01-Apr Updated Table 1: Devices summary DocID Rev 7 27/28 27

28 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved 28/28 DocID Rev 7

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