Computer Organization I CRN Test 3/Version 1 CMSC 2833 CRN Spring 2017

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1 . Print your name on your SANTRON in the space labeled NAME. 2. Print MS 2833 in the space labeled SUBJET. 3. Print the date , in the space labeled DATE. 4. Print your RN in the space labeled PERIOD. 4.. Your RN is 275 if you are enrolled in the on-campus section Your RN is 2542 if you are enrolled in the IVE section. 5. Print the test number and version, T3/V, in the space labeled TEST NO. 6. This is a closed-book examination. No reference materials are permitted. No notes are permitted. 7. You may not consult your neighbors, colleagues, or fellow students to answer the questions on this test. 8. ellular phones are prohibited. The possessor of a cellular phone will receive a zero () if the phone rings or is visible during the test. 9. You may use your personal calculator on this test. You are prohibited from loaning your calculator or borrowing a calculator from another person enrolled in this course.. Mark the best selection that satisfies the question. If selection b is better that selections a and d, then mark selection b. Mark only one selection.. Darken your selections completely. Make a heavy black mark that completely fills your selection. 2. Answer all 5 questions. 3. Record your answers on SANTRON form 882-E (It is green!) 4. When you have completed the test, place your SANTRON, face up, between pages 2 and 3 of your questionnaire and submit both the questionnaire and your SANTRON to your instructor.

2 . What is an ISA? a. Independent Service Agreement b. Instruction Set Architecture c. Industry Standard Architecture d. International Society of Automation 2. What unit is typically used to measure the speed of a computer clock? a. nanosecond b. mflops c. mips d. hertz 3. To what power of does the prefix micro- refer? What is the (approximate) equivalent power of 2? a. MMss = 6 ss 2 2 ss b. mmmm = 3 ss 2 ss c. μμμμ = 6 ss 2 2 ss d. kkkk = 3 ss 2 ss 4. The third generation of computers was characterized by the a. Introduction of the transistor b. Introduction of single-chip computers c. Introduction of minicomputers. d. Introduction of integrated circuits 5. Which of the following pairs consisting of inventor, invention is incorrect? a. John Mauchly, GENIA b. harles Babbage, Difference Engine c. Konrad Zuse, Z d. Seymour ray, D onvert to hexadecimal. a. 2AAAA4.266 b AAAA4 c AAAA4 d AAAA4 7. onvert. TTTTTTTT 36 to decimal. a b c d

3 8. Express 297 in a 2-bit one s complement representation. a. b. c. d. 9. Add 334 to 37 using 2-bit one s complement arithmetic. a. b. c. d.. Express 54 using 2-bit two s complement arithmetic. a. b. c. d.. Subtract 32 from 3 using 2-bit two s complement arithmetic. a. b. c. d. 2. Find the excess binary representation of -237 in a -bit integer field. a. b. c. d. 3

4 3. Select the Figure that correctly computes the unsigned binary product of 5 3. X X Figure a. Figure b. X X Figure c. Figure d. 4. ompute the quotient and remainder modulo 2 of uotient Remainder a. b. c. d. 5. Find the IEEE-754 single binary representation in hexadecimal of a. 429D8 b c d Which of the values below can be converted to this IEEE-754 single binary value, , in hexadecimal representation? a b c d

5 7. Which of the following messages, MM, that were received, have no errors given polynomial PP = was used to create MM. a. b. c. d. 8. Which truth table specifies function ff(xx, yy, zz) = yyyy + zz(xxxx)? xx yy zz ff xx yy zz ff a. b. xx yy zz ff xx yy zz ff c. d. 9. Using DeMorgan s Law, select the expression that is the complement of ff(xx, yy, zz) = (xx + yy)(xx + zz)(yy + zz)? a. ff (xx, yy, zz) = xx + yy + zz b. ff (xx, yy, zz) = xx + yy + zz c. ff (xx, yy, zz) = xx + yy + zz d. none 2. Which of the following is NOT equivalent to ff(ww, xx, yy, zz) = (ww + xx + zz )(ww + xx + zz)(xx + yy + zz)(xx + yy + zz )? a. ff(ww, xx, yy, zz) = xx zz + xxxx + wwww b. ff (ww, xx, yy, zz) = (,2,5,7,8,,,3,4,5) c. ff (ww, xx, yy, zz) = ww xx zz + ww xxxx + wwwwww + wwwwww + wwxx zz + wwww yy d. none 5

6 2. Simplify ff(xx, yy, zz) = xxxxzz + (yy + zz) + xx yyyy using Boolean algebra and its identities. a. ff (xx, yy, zz) = (yy zz) b. ff (xx, yy, zz) = (yy zz) c. ff (xx, yy, zz) = (xx yy) d. none 22. Select the expression for ff(xx, yy, zz), in sum-of-products form, NOT simplified, given by the truth table shown. xx yy zz ff a. ff(xx, yy, zz) = xx yy zz + xx yyzz + xxyy zz + xxxxzz + xxxxxx b. ff(xx, yy, zz) = (xx + yy + zz )(xx + yy + zz )(xx + yy + zz) c. ff(xx, yy, zz) = xx zz + xxxx + xxxx d. ff(xx, yy, zz) = xx zz + yyyy + xxxx 6

7 23. Select the logic diagram that implements simplified expression for ff(xx, yy, zz) = yy(xx zz + xxzz ) + xx(yyyy + yyzz ). x y z x y z a. b. 7

8 x y z x y z c. d. 8

9 24. Select the truth table that specifies a full adder given xx is the augend, yy is the addend, zz is the carry-in, cc is the carry-out, and ss is the sum. xx yy zz cc ss xx yy zz cc ss a. b. xx yy zz cc ss xx yy zz cc ss c. d. 9

10 25. Select the logic diagram that implements a full adder. x y z s c a. x y z c s b.

11 x y z s c c. x y z c s d.

12 26. Find the truth table for function FF whose logic diagram is given below. x y z F(x,y,z) xx yy zz FF xx yy zz FF a. b. xx yy zz FF xx yy zz FF c. d. 2

13 27. Find the equations for the next state decoder in the diagram below. X A A B B X X D B D A LOK a. DD AA = AA + BB + XX, DD BB = BB b. DD AA = AA BB XX, DD BB = BB c. DD AA = AA BB XX, DD BB = BB d. DD AA = AA + BB + XX, DD BB = BB 3

14 28. Find the K-Maps for the next state decoder in the diagram below. X A A B B X X D B D A LOK D A D B X AB X AB a. 4

15 D A D B X AB X AB b. D A D B X AB X AB c. D A D B X AB X AB d. 5

16 29. Derive the state table for the sequential circuit in the diagram below. X A A B B X X D B D A LOK 6

17 urrent Next Decoder Next AA BB XX DD AA DD BB AA BB urrent urrent Next Decoder Next AA BB XX DD AA DD BB AA BB a. b. Next Decoder Next AA BB XX DD AA DD BB AA BB urrent Next Decoder Next AA BB XX DD AA DD BB AA BB c. d. 7

18 3. Derive the state diagram for the sequential circuit in the diagram below. X A A B B X X D B D A LOK 8

19 a. b c. d.

20 3. Select the state table that corresponds to the state diagram for the sequential circuit in the below urrent Next Next Decoder AA BB AA BB JJ AA KK AA JJ BB KK BB JJ KK x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x a. urrent Next Next Decoder AA BB AA BB JJ AA KK AA JJ BB KK BB JJ KK x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x b. 2

21 urrent Next Next Decoder AA BB AA BB JJ AA KK AA JJ BB KK BB JJ KK x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x c. urrent Next Next Decoder AA BB AA BB JJ AA KK AA JJ BB KK BB JJ KK x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x d. 32. Select the logic diagram that corresponds to the state diagram for the sequential circuit in the below

22 V B B A A J K A J K B J K LK a. 22

23 V B B A A J K A J K B J K LK b. 23

24 V B B A A J K A J K B J K LK c. 24

25 V B B A A J K A J K B J K LK d. 25

26 33. Select the characteristic table for a T-Flip-flop that inverts the current state when TT = and retains the current state when TT =. T n n+ haracteristic Table T n n+ haracteristic Table a. b. n n+ T haracteristic Table n n+ T haracteristic Table c. d. 34. Augment the characteristic table for a T-Flip-flop to design the flip-flop from a S-R Flip-Flop. T n n+ S R x x Augmented haracteristic Table T n n+ S R x x Augmented haracteristic Table a. b. T n n+ S R x x Augmented haracteristic Table T n n+ S R x x Augmented haracteristic Table c. d. 26

27 35. Draw K-Maps for the T-Flip-flop. S T R T n n 2 x 2 x 3 3 S T a. R T n n 2 x 2 x 3 3 S T b. R T n n 2 2 x 3 x 3 S T c. R T n n 2 2 x 3 x 3 d. 27

28 36. Draw a logic diagram for the T-Flip-flop. S T R LK a. T S R LK b. S T R LK c. 28

29 S T R LK d. 37. A composite memory, 32G 32 is created using component memory chips, 2G 8. How many component memory chips are required to create the composite memory? a. 2 5 b. 2 4 c. 2 7 d A composite memory, 32G 32 is created using component memory chips, 2G 8. How many address lines are required to access the composite memory? a. 35 b. 34 c. 3 d A composite memory, 32G 32 is created using component memory chips, 2G 8. How many address lines are connected to the component chips? a. 35 b. 3 c. 34 d A composite memory, 32G 32 is created using component memory chips, 2G 8. How many of the address lines must be decoded to produce the chip select inputs? a. 4 b. 5 c. 6 d. 3 29

30 4. A composite memory, 32G 32 is created using component memory chips, 2G 8. How many component memory chips are connected to each output of the decoder? a. 5 b. 6 c. 3 d A composite memory, 32G 32 is created using component memory chips, 2G 8. Specify the size of the decoder needed to construct the composite memory. a. 4-line-to-6-line decoder b. 5-line-to-32-line decoder c. 6-line-to-64-line decoder d. 3-line-to-8-line decoder 43. How many address lines are required to address a M 8 main memory if the memory is byte-addressable? a. 9 address lines b. 8 address lines c. 2 address lines d. 7 address lines 44. How many address lines are required to address a M 8 main memory if the memory is word-addressable and each word consists of 8 bytes? a. 2 address lines b. 7 address lines c. 9 address lines d. 8 address lines 45. Select the correct Register Transfer Notation (RTN) sequence for the MARIE Load instruction. MAR P IR M[MAR} P P+ MAR X MBR M[MAR] A A+MBR MAR P IR M[MAR} P P+ MAR X MBR M[MAR] A MBR a. b. 3

31 MAR P IR M[MAR} P P+ MAR X MBR A M[MAR] MBR MAR P IR M[MAR} P P+ MAR X MBR M[MAR] P MBR c. d. 46. Select the correct signal pattern for the register transfer MAR XX during clock signal T 3. The table of control signals and their associated registers is given to assist you for this question. Register Memory MAR P MBR A IN OUT IR Signals P 2P P (Read) P 5P 4P 3(Write) a. P 3 P 2 P P T 3 b. P 4 P 3 T 3 M r c. r A P 5 T 3 L ALT d. P 3 P T 3 3

32 T T T 2 T 3 T 4 T 5 P P P 2 P 3 P 4 P 5 R IncrP A A M R M W L ALT Figure 47. Diagram for uestions 47, 48 32

33 47. Which register transfer is executed at TT 3 in the timing diagram of Figure 47? a. MAR P b. IR M[MAR] c. P P+ d. MAR IR[-] 48. To which of MARIE s instructions does the timing diagram in Figure 47 refer? a. Load X b. Subt X c. Store X d. Add X 49. Among other things, assembler directives can: a. determine the next action after numeric overflow b. distinguish a value as hexadecimal or decimal c. invoke interrupt service routines d. control conditional assembly using macro instructions 5. During the first pass of an assembler: a. instructions are only partially assembled b. the symbol table is only partially completed c. addresses from the symbol table are placed in object code d. external code is merged with the object code 33

Computer Organization I Solution 3/Version 1 CMSC 2833 Autumn 2007

Computer Organization I Solution 3/Version 1 CMSC 2833 Autumn 2007 omputer Organization I Solution /Version MS 8 utumn. Print your name on your scantron in the space labeled NME.. Print MS 8 in the space labeled SUJET.. Print the date, --, in the space labeled DTE.. Print