Efficient Implication - Based Untestable Bridge Fault Identifier*

Transcription

1 Efficient Impliction - Bsed Untestle Bridge Fult Identifier* Mnn Syl, Michel S. Hsio, Kirn B. Doreswmy nd Sreejit Chkrvrty Brdley Deprtment of Electricl nd Computer Engineering, Virgini Tech, Blcksurg, VA. Intel Corportion, Portlnd, Oregon. Intel Architecture Group, Intel Corportion, Snt Clr, CA. Astrct: This pper presents novel, low cost technique sed on implictions to identify untestle ridging fults in sequentil circuits. Sequentil symolic simultion [] is first performed, s preprocessing step, to identify nets which re uncontrollle to specific logic vlue. Then, n impliction-sed nlysis is crried out for ech fult to determine if prticulr fult is testle or not. We lso use informtion out the untestle stuck-t fults to filter out some ridges erly in the nlysis process. The ppliction of our technique to ISCAS 89 sequentil enchmrk circuits nd few industril circuits showed tht lrge numer of untestle ridges could e identified t low cost, oth in terms of memory nd execution time.. Introduction: A ridge fult etween two or more nets refers to defect where the nets re unintentionlly shorted together. While the size of the more commonly studied stuck-t fult list is of the order of the size of the circuit, ridging fult lists cn potentilly e of polynomil order in the size of the circuit. Furthermore, the cost of ridge-fult ATPG cn exceed tht of the stuck-t counterprt. Thus, it would e eneficil to quickly identify ridging fults tht re redundnt/untestle, so tht tools such s ridging fult ATPG engines or ridging fult simultors do not wste time trgeting these fults. Our work focuses on efficient identifiction of such untestle ridging fults. Algorithms hve een proposed erlier for two node [2] nd multimode [3] ridge fult extrction/nlysis. In our pproch, we limit the nlysis to two-node ridges. Also, we ssume the ridge fult to e present etween the outputs of two nodes, nd no ridges internl to Boolen gte re considered for nlysis. Resistnce of ridge determines the kind of fult effect the ridge produces in circuit. Bridges of high resistnce type cuse the outputs of the succeeding gtes to hve delyed trnsition, leding to dely fult, while ridges hving low resistnce (hrd short) cuse the sttic ehvior of the circuit to chnge. In our nlysis, we ssume the ridge fult to e of the hrd short type, which cuses the functionlity of the circuit to chnge. A lot of models hve een proposed for the nlysis of such kind of ridges. Stuck-t fults hve een used to model the ehvior of ridges [4], long with the voting [5] nd the ised voting method [6], which re the more populr modeling methods. The model we use for our purpose of identifying untestle ridges is sed on the wired nd the dominnt fult models [7]. Untestle ridges re fults for which no test pttern exists tht cn either excite the fult or propgte the fult effect to n oservle point. Current utomtic test pttern genertors (ATPGs) wste lot of time on such fults * This reserch ws performed while the first two uthors were t Intel during the period extending from 05/02 to 08/02. This work is lso supported in prt y NSF grnt # efore identifying them s untestle or orting on them. Although much work hs een presented for the identifiction of untestle stuck-t fults [8][9][0], there hsn t een ny significnt contriution towrds the identifiction of untestle ridges in sequentil circuits. Thus, to the est of our knowledge, our work on the identifiction of untestle ridges using implictions is the first of its kind. Our implementtion is sed on the representtion of sequentil circuit s n itertive logic rry (ILA) of fixed length []. For ech ridge, we identify set of conditions tht re necessry for the fult to e testle. We imply these set of conditions within the ILA nd use this informtion to determine whether the ridge cn e declred s untestle or not. We evluted our tool ginst the lrger ISCAS 89 circuits long with few industril circuits. We vlidted nd compred these results with our internl ATPG engine for ridging fults. Interestingly, it ws oserved tht we could identify more untestle fults using this new tool thn the ATPG tool could identify. The reltionship etween the untestle fults identified y the ATPG tool nd our new implictions sed tool is shown in Figure. Unt. fults identified only y ATPG Unt. fults identified only y implictions sed tool Unt. fults identified y oth ATPG nd implictions sed tool Figure: Reltionship etween the untestle fults identified y ATPG nd the implictions sed tool It cn e seen tht ATPG cn identify some untestle ridges which the impliction-sed technique fils to cpture ( ); however, the implictions sed technique cn identify lot of untestle fults which the ATPG tool orts on ( ). Rest of the pper is orgnized s given elow: Section 2 gives n introduction to logic implictions, the symolic simultion we use to identify uncontrollle nets nd the fult model(s) we use to identify the ehvior of ridging fult. Section 3 descries our pproch nd lgorithm, with section 4 reporting the results otined for ISCAS 89 sequentil circuits, nd few industril circuits. Finlly, section 5 concludes the pper. 2. Preliminries 2. Logic Implictions: Sttic implictions re the implictions ssocited with inry logic vlues present t the output of every gte in the circuit. Sttic implictions consist of direct, indirect nd extended ckwrd implictions. Direct implictions of gte g re the implictions ssocited with the gtes directly connected to g. Direct implictions re esy to compute, unlike Indirect nd extended ckwrd

2 implictions which require extensive use of trnsitive nd contrpositive properties ssocited with implictions [0]. The concept of direct nd indirect implictions cn e understood from the following exmple: Exmple : Consider the circuit shown in Figure 2. B E A D F C Figure 2: Illustrtion of direct nd indirect implictions Consider the implictions of gte A = with respect to its directly connected nodes. A = { (B = ), (C = ), ( E = ), (F = ) } This set, long with A = forms the direct implictions for node A =. Now, nodes B = nd C = do not individully imply ny vlue on node D. However, together, they imply D =. Thus, A = indirectly implies D =. Hence D = ecomes n indirect impliction ssocited with gte A =. Another notion ssocited with implictions is tht of ckwrd nd forwrd implictions. Let s sy we need to find the implictions of gte g = v (v = 0 or ). All implictions ssocited with the input cone of gte g form the ckwrd implictions for g nd ll implictions ssocited with the output cone of g form the forwrd implictions of g. This concept is shown with the id of n AND gte in Figure 3. 0 () () Figure 3: () ckwrd implictions () forwrd implictions Although the grphicl representtion of implictions proposed in [0] is memory efficient pproch, it would still low up for lrge (sequentil) industril circuits (with size > 00K gtes). Also, the use of extended ckwrd implictions on such circuits would prove to e too expensive oth in terms of memory nd execution time. Thus, in our ppliction, we: ) Do not pre-compute nd store the implictions ssocited with ech gte in the circuit. We compute the implictions of gte on need sis, i.e. only for gtes tht re involved in ridge. We simply llocte the mximum spce tht cn possily e required to store the implictions of gte, or for the group of gtes involved in ridge, nd we re-use tht spce for every fult we nlyze. ) Do not compute extended ckwrd implictions corresponding to every unjustified gte in the impliction list of gte [0], ecuse it proves to e too expensive. It my e rgued tht: ) If gte g is involved in ridge with mny other gtes, then we might hve to re-compute the implictions of g ech time we nlyze ridge in which g is involved. Since we don t store the implictions of ll gtes upfront, 0 this dupliction of work my cost us in terms of time. However, since we compute the implictions of gte only on need-sis, i.e. only if the gte is involved in ridge, so the time penlty in potentilly re-computing the implictions of gte more thn once is fr less thn computing nd storing the implictions of ll gtes (most of which re not involved in ny ridging fult) upfront. ) We might lose some informtion in terms of constnts ( line tht is uncontrollle to some logic v is sid to e constnt with vlue v ), y not evluting the implictions of every gte in the circuit. However, we more thn compenste for this through the sequentil symolic simultion. c) By not performing extended ckwrd implictions, we might not hve s powerful n impliction engine, s we might hve with the ppliction of extended ckwrd implictions. Though this is true, the time penlty ssocited with the computtion of extended ckwrd implictions for every unjustified gte in the impliction list for gte outweighs the dvntge of more powerful impliction engine ville with extended ckwrd implictions. 2.2 Symolic Simultion: Symolic simultion is performed s preprocessing step to untestle ridge nlysis; it identifies nets tht re uncontrollle to specific logic vlue. For exmple, line in the circuit shown in Figure 4 is uncontrollle to logic 0 ssuming tht the initil stte of the flip-flop is unknown, nd line is fully controllle to ny vlue. D Q CLK Figure 4: concept of uncontrollle net We perform symolic simultion using symols, tht represent the controllility chrctersitics of ny given line. Node G is uncontrollle to logic vlue V mens: There is no single finite sequence I, which when pplied to the controllle points in the net-list, cn set G to vlue V for every possile power up stte of the sequentil elements in the design, where V {0,,Z}. Z in the vlue set refers to the high impednce stte of net. Since most of the industril circuits hve tri-stte devices nd us structures, we support the high impednce vlue in our tool. The symols used, nd their mening is descried elow: ) Strong_0 (Strong_): If line cn only tke vlue of strong 0 ( strong ), then it is ssocited with this symol. For exmple, net directly connected to VSS (VDD) would tke this symolic vlue. (Represented s ST_0 (ST_) ). 2) ControllleToAny (C_ANY) : If prticulr net cn ssume ny vlue from the defined vlue set, then it is ssocited with the ControllleToAny symol. This symol is ssocited with ll the primry inputs nd the scn elements. 3) UncontrollleTo_0 (UncontrollleTo_): A net tht cnnot e controlled to logic 0 (logic ) is ssocited with 2

3 the UncontrollleTo_0 (UncontrollleTo_) symol. For exmple, the output of the OR gte shown in Figure 4 cnnot e driven to logic 0, nd hence would ssume this symol. (Represented s UN_0 (UN_) ). 4) UncontrollleToAny (U_ANY): This symol is socited with the net tht cnnot e controlled to ny vlue. This is the symol ssocited with the output of every non-scn ltch/flip-flop t the eginning of symolic simultion. The symolic vlues descried ove cn e ssocited with ny gte/net in the circuit, while the ones descried elow cn only e ssocited with the nets tht produce/trnsmit high impednce (Z) stte. 5) Strong_Z : Associted with the net tht cn only tke the high impedence stte. For exmple, tri-stte device with n ctive high enle would ssume this symolic vlue, if the enle line is constnt 0. 6) UncontrollleTo_Z: A net would ssume this vlue if it cn never chieve the high impedence stte. For exmple, controlled uffer with n ctive high enle would e ssocited with this symolic vlue if the enle line is constnt. 7) UncontrollleTo_0: If net cn never e driven to either 0 or, then it would e ssocited with this symolic vlue. 8) UncontrollleTo_Z: A net which cnnot chive either high impedenece stte or cnnot e excited to logic would e ssocited with this symolic vlue. For exmple, wired-and gte (s shown in Figure 5) with one driver set t UncontrollleTo_Z would e ssocited with this symolic vlue, s the UncontrollleTo_Z on one of the driver s o/p would dominte the vlue on ny other driver. UncontrollleTo Z Wired - AND gte UncontrollleTo_Z Figure 5: Wired-AND gte gets ssocited with symolic vlue of UncontrollleTo_Z. 9) UncontrollleTo_0Z: A net which cnnot e excited to either logic vlue of 0 or Z would e ssocited with this symolic vlue. For exmple, wired-or gte with one driver s UncontrollleTo_0Z would e ssocited with the symolic vlue of UncontrollleTo_0Z (s shown in Figure 6). UncontrollleTo 0Z Wired -OR gte UncontrollleTo_0Z Figure 6: Wired-OR gte gets ssocited with symolic vlue of UncontrollleTo_0Z. Symolic simultion is initited y ssigning ControllleToAny symol to ll primry inputs nd scn elements, nd UncontrollleToAny symol to ll ltch elements/flip flops. The simultion is event-driven; it proceeds in levelized mnner, nd ech gte is evluted one time frme fter nother, until the circuit settles down to stle stte. To propgte symols, pre-computed chrcteristic propgtion tle for ech gte is looked up to determine the resulting symolic vlue for the gte. Such chrcteristic tle for 2-input OR gte is shown in Figure 7. A A B C_ANY U_ANY ST_0 ST_ UN_0 UN_ B () C_ANY U_ANY ST_0 ST_ UN_0 UN_ C_ANY UN_0 C_ANY ST_ UN_0 C_ANY UN_0 U_ANY U_ANY ST_ UN_0 U_ANY C_ANY U_ANY ST_0 ST_ UN_0 UN_ ST_ ST_ ST_ ST_ ST_ ST_ UN_0 UN_0 UN_0 ST_ UN_0 UN_0 C_ANY U_ANY UN_ ST_ UN_0 UN_ () Figure 7: () OR gte () Its symolic evlution tle 2.3 Fult Models The fult models tht we use to descrie the ehvior of ridge, long with conditions tht re required to excite the ridge fult of ech type, is shown in Tle [7]. Column one in Tle represents the ridge fult models used. Column two shows the representtion for ech model nd column three shows the excittion condition(s) for ech ridging fult type. Here, nd represent the nets in the good mchine, while nd represent the sme nets in the fulty mchine. Also, DOM implies tht logic vlues on net dominte tht on net, while DOMV mens tht net domintes only if = V. It my e rgued tht since the excittion conditions for the DOM ridge fult covers the excittion condition for the DOM0 nd DOM ridge fult, nlyzing DOM0 nd/or DOM ridge fult model etween two nets would not e necessry if the DOM ridge fult etween the nets is eing nlyzed. This would e true if the DOM ridge fult etween the two nets is found to e untestle. Then oth DOM0 nd DOM ridge fults would lso e untestle, nd it would e redundnt to nlyze them. However, the converse is not true. Tht is, it is possile tht even though DOM ridge etween two nets is testle, either DOM0 or DOM ridge fult could still e untestle. So, it would e necessry to consider the DOM0 nd DOM fult models even though they form suset of fult models such s DOM or Wired-AND or Wired-OR model. 3. Algorithm The following definition of n oservtion point is necessry to understnd efore we cn discuss the lgorithm: Definition : (Oservtion point) An oservtion point for fult is defined s the nerest fnout stem, primry output or ltch element, in the fnout cone of the fult site. 3

4 Fult Model Representtion Excittion Condition(s) Wired-AND Bridge ( AND ) ) ( = 0) nd ( = ) 2) ( = ) nd ( = 0) Wired-OR Bridge ( OR ) ) ( = 0) nd ( = ) 2) ( = ) nd ( = 0) DOM Bridge ( DOM ) ) ( = 0) nd ( = ) 2) ( = ) nd ( = 0) DOM0 Bridge ( DOM0 ) ) ( = 0) nd ( = ) DOM Bridge ( DOM ) ) ( = ) nd ( = 0) Tle : Fult models, their representtions nd excittion condition(s) Also, our nlysis is sed on the ILA (itertive logic rry, of fixed length K) representtion of sequentil circuit, where the ltch elements of the lowest time frme (i.e.frme K/2) of the ILA re fully controllle, nd the ltch elements in the right most time frme (i.e. frme K/2) re fully oservle. Figure 8 outlines the overll lgorithm: ) Perform Symolic Simultion to otin informtion out constnts in the circuit. Asor the untestle stuck-t informtion to screen out some ridging fults. ) For the remining fults (per-fult nlysis):.) Find the necessry condition(s) to excite the fult, nd to propgte the fult effect to n Oservtion Point..2) Bckwrd imply/justify these set of conditions..3) If no conflict exists, forwrd imply with the logic vlues set in the circuit. If conflict exists in ckwrd / forwrd implictions, ridge fult is untestle..4) Perform oservility nlysis to determine if the fult effect cn e propgted to PO or to the ltch/flip-flop oundry in the lst time frme of the k-frme unrolled circuit. Figure 8: Algorithm for untestle ridge identifiction Let us now look t the lgorithm in detil: )Symolic simultion nd sorption of stuck-t informtion: As discussed erlier in section 2., we perform sequentil symolic simultion using symols, to identify controllility chrcteristics of nets in the circuit. At the eginning of the simultion, we ssocite the primry inputs (PIs) nd the controllle ltch elements with the symol ControllleToAny, nd the other sequentil (ltch) elements with the symol UncontrollleToAny, nd propgte these symols cross the circuit. We use the tle look-up scheme descried erlier, until the circuit stilizes to stedy stte w.r.t. symolic vlues. We sor fult list which lists ll untestle stuck t fults in the circuit, nd screen out certin ridge fults efore strting the per-fult nlysis. For exmple, if the fult stuck-t 0 is untestle, then the ridging fult DOM0 etween nets nd would lso e untestle, nd cn e dropped from the originl ridge fult list. Our tool tht identifies untestle stuck-t fults is sed on symolic simultion nd Boolen stisfiility nlysis, ut we would not discuss the detils of tht tool in this pper. ) Per-Fult Anlysis: After filtering the initil fult list, we perform the following nlysis on ech fult in the reduced list:.) Identifiction of conditions necessry for fult detection: Depending upon the fult type, we identify the fult site nd the condition(s) for fult excittion (s previously shown in Tle ). For exmple, if DOM0 ridge exists etween nets nd, then the fult excittion condition would e ( = 0) nd ( = ), nd the fult site would e net, ecuse fult effect of 0/ (good mchine vlue / fulty mchine vlue) ppers on this net. Then, we identify the conditions necessry to propgte the fult effect to n oservtion point. This siclly mens tht we identify the non-controlling vlues on ech gte in the off-pth from the fult site to the oservtion point. These conditions must e met if the fult hs to e testle. 4

5 .2) A ckwrd impliction routine is then invoked on the necessry set of conditions. We could hve seprtely implied ech necessry condition nd dded the individul impliction lists to otin the composite impliction list corresponding to the set of necessry conditions. This is exctly wht would hve een done if implictions corresponding to ech gte were computed s pre-processing step. However, we compute the implictions ssocited with the entire set of necessry conditions in one go, ecuse this technique helps in lerning more implictions. The ckwrd impliction process egins t the fult injection frme, nd goes on till the lowest time frme in the ILA expnsion is reched (i.e. K/2, in n ILA representtion of K frmes) or till no more implictions cn e lernt..3) If no conflict is encountered in the ckwrd impliction process, then forwrd impliction process is invoked on the lredy lernt impliction set. This impliction process egins t the lowest level of the ILA expnsion, nd continues till the lst frme of the ILA is reched (i.e. egins t K/2, or the lowest frme tht hs vlid impliction ssocited with it, nd continues till frme K/2) or till no more implictions cn e lernt..4) If no conflict occurs during either the ckwrd impliction process or during the forwrd impliction process, then n oservility nlysis is crried out to determine if the fult effect cn e oserved or not. This oservility nlysis mrks the lst step of untestility nlysis for fult, nd the motivtion ehind the oservility nlysis is to check if the excittion conditions for the fult lock the fult effect from propgting to the primry output(s) or not. The wy we implement this oservility nlysis is through multiple ID propgtion. This is explined elow: We ssocite n ID with the fult site, (sy X), nd propgte it through the circuit. We lso keep trck of the polrity of this ID, nd identify the inverted vlue of this ID s X. This is done to identify msking of fult effects (For exmple, if n id of X nd X pper t the input of n AND gte, the fult effect would get killed due to the opposite polrities of the fult IDs). Since most of the industril designs contin tri-stte devices, nd uses, we use nother ID, which is generic ID, nd we cll it IDG. The motivtion of using IDG cn e understood through Figure 9. 0 X Z/0 Z/ Figure 9: Use of generic ID, IDG Let s ssume tht fult ID X (lets ssume X represents fulty stte of 0/) ppers t the select line of tri-stte device, s shown in figure 9, with n ctive high enle. The fulty mchine vlue t the output of the gte would e the vlue pplied t the input of the gte, ut the good mchine vlue will e Z, i.e. high impednce stte. A fult effect of Z/0 or Z/ cnnot e directly ssocited with either X or X (ecuse X nd X re of the form 0/ or /0). Thus, this fult effect is represented y new ID, i.e. IDG. Thus, if ny of these IDs, i.e. X, X or IDG propgte to either PO or to the ltch oundry in the lst time frme of the ILA expnsion, then the fult is not declred untestle. However, if none of these IDs cn propgte to completely oservle point, then the ridge is mrked s untestle. 4. Results: The proposed lgorithm ws implemented in C++ nd experiments were conducted on ISCAS89 nd some industril circuits on 500 MHz, HP worksttion. The results re reported in Tle 2. Column in Tle 2 shows the ISCAS 89 circuits, nd the industril circuits (C, C2, C3) for which the tool ws evluted. Column 2 shows the numer of fults our ridge fult ATPG engine identified s untestle, with the cktrck limit set to 000. Column 3 shows the numer of fults identified s untestle using the new implictions-sed tool, with the time frme expnsion of the circuit eing from 2 to 2. The numers in the prenthesis in this column show two vlues. The first vlue is the numer of fults identified s untestle oth y the new tool nd y ATPG, nd the second vlue in old identifies the numer of fults tht our tool identified s untestle, for which ATPG orted fter 000 cktrcks. For exmple, for circuit s5378, ATPG identified 26 fults s untestle. With the implictions sed pproch, we identified 552 fults s untestle. Out of these 552 fults, 87 fults were identified s untestle y oth ATPG nd the implictions sed tool, while the rest 365 fults identified s untestle, were the fults on which ATPG orted. So, the gin here is w.r.t the 365 fults which our new tool could identify s untestle, while for which ATPG could not generte pttern. Column 5 shows the numer of fults identified s untestle y the new tool, using K = 0, i.e. y unrolling the sequentil circuit in just one time frme (effectively comintion nlysis). Finlly, columns 4 nd 6 show the time tken y the implictions sed tool to nlyse ll fults for n ILA size of 5 (K = 2) nd ILA size of (K = 0) respectively. Tle 3 shows the time spent y ATPG to nlyze the fults identified s untestle using the implictions sed lgorithm. Column in Tle 3 shows the circuit nme, nd the 2 nd column shows the time spent y ATPG only on the fults which were identified s untestle using the implictions sed tool (S unt for K = 2). For exmple, for s5850, the ATPG engine took 953 seconds to nlyze the 90 fults identified s untestle y our tool for K = 2. It ws oserved tht the numer of untestle fults identified with K = 0 (comintionl nlysis) is lmost the sme s the numer of fults identified y expnding the ILA to length of 5 frmes for most of the circuits. Thus, it cn e seen tht even in comintionl frmework, our tool cn quickly identify more untestle fults thn the ATPG tool cn cpture. It ws lso seen tht lthough our implictions sed pproch for identifying untestle ridges worked out etter thn ATPG for ISCAS circuits, it identified only suset of the fults identified s untestle y the ATPG engine for the 5

6 Circuit ATPG Red. (k = 000) s s s s s s s S unt (K* = 2) 552 (87/365) 5585 (679/4906) 363 (485/7) 90 (230/960) 945 (95/30) 428 (5/3) 868 (74/54) 39 C 54 (39/0) C2 (27/0) C (2/0) Time (sec) K = S unt (K = 0) 76 (76/0) 5568 (676/4892) 360 (485/708) 83 (228/955) 927 (897/30) 48 (/307) industril circuits. This is primrily due to the fct tht the us structures present more commonly in industril designs limit the strength of implictions, nd hence limit the untestle fult identifiction cpility. Nevertheless, our tool provides novel technique to quickly identify nontrivil untestle ridging fults, therey reducing the size of the ridging fult list to e nlyzed y ridge-fult ATPG engines. 5. Conclusion: In this pper, we proposed n impliction sed pproch complemented with symolic simultor to identify untestle ridging fults t gte level. Our tool ws tested on lrge ISCAS 89 circuits, nd three industril circuits. We found the following: ) The proposed lgorithm could identify lot of untestle ridging fults in ISCAS 89 circuits. ) The proposed lgorithm when pplied to n ILA of size K = 0 could identify lmost s mny untestle fults s could e identified with n ILA of size 5. c) Our tool is very inexpensive in terms of oth memory nd the time tken to identify untestle fults. Both these performnce metrics (time nd memory) re lwys liner in the size of the circuit. Also, the fults tht we identify s untestle re non-trivil, s ATPG orts for most of these fults. References: [] Hsing - Chung Ling, Chung Len Lee, Jwu E. Chen. Identifying untestle fults in sequentil circuits. IEEE Design nd Test of Computers. Pges 4-23, Fll (7/50) 39 (39/0) 27 (27/0) 2 (2/0) Time (sec) K = 0 *K = ± numer of frmes in which the sequentil circuit is unrolled Tle 2: Results otined for 6000 rndomly generted ridges Circuit T ATPG (sec) s s s s s s s C 0 C2 3 C3 8 Tle 3: Time tken y ATPG to nlyze S unt [2] S. T. Zchrih, S. Chkrvrty, C. D. Roth. A novel lgorithm to extrct two-node ridges. Design Automtion Conf., pges [3] S.T. Zchrih, S. Chkrvrty. A novel lgorithm for multinode ridge nlysis of lrge VLSI circuits. VLSI Design, 200, pges [4] S.D. Millmn, E.J. McCluskey, nd J.K. Acken. Dignosing CMOS ridging fults with stuck-t fult dictionries. In Int l Test Conf., pges , 990. [5] S. D. Millmn, Sir J.P. Grvey. An ccurte ridging fult test pttern genertor. Int l Test Conf., pges 4-47, 99. [6] P.C. Mxwell nd R.C. Aitken. Bised voting: A method for simulting CMOS ridging fults in the presence of vrile gte logic thresholds. In Int l Test Conf., pges 63-72, 993. [7] M. Armovici, M.A. Breuer nd A.D. Friedmn. Digitl Systems Testing nd Testle Design. Cmputer Science Press, 990. [8] M. A. Iyer nd M. Armovici, FIRE: fult independent comintionl redundncy lgorithm, IEEE Trns. VLSI sy.s, June 996, pges [9] M.A. Iyer, D.E. Long, Armovici, "Identifying sequentil redundncies without serch," Design Automtion Conference, 996, pges [0] J. Zho, J. A. Newquist nd J. Ptel, A grph trversl sed frmework for sequentil logic impliction with n ppliction to c-cycle redundncy identifiction, Proc. VLSI Design Conf., 200, pp [] V. D. Agrwl nd S. T. Chkrdhr, "Comintionl ATPG Theorems for Identifying Untestle Fults in Sequentil Circuits," IEEE Trns. CAD, vol. 4, Sept. 999, pp