Jin-Fu Li. Department of Electrical Engineering National Central University Jhongli, Taiwan

Transcription

1 Trnsprent BIST for RAMs Jin-Fu Li Advnced d Relible Systems (ARES) Lb. Deprtment of Electricl Engineering Ntionl Centrl University Jhongli, Tiwn

2 Outline Introduction Concept of Trnsprent Test Trnsprent Test Techniques Conclusions Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 2

3 Relibility-Enhncement Techniques Fult-tolernt techniques re widely used to improve the relibility of systems All fult-tolernt techniques require redundncy Redundncy is simply the ddition of informtion, resources, or time beyond wht is needed for norml system opertion Types of redundncy Hrdwre redundncy Softwre redundncy d Informtion redundncy Time redundncy Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 3

4 Memory Relibility-Enhncement Hrdwre redundncy Techniques Built-in self-repir technique Error correction code Use informtion redundncy to protect stored dt from soft error Periodic trnsprent testing Periodiclly pply tests to detect hrd fults mnifested by ltent fults Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 4

5 Typicl Error-Correction-Code Scheme Check Bit Genertor RAM Dt redundncy Syndrome Genertor Dt Dt Input Dt Correct tor Dt Output Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 5

6 Hmming Error-Correction Code The Hmming single error-correction code uses c prity check bits to protect k bits of informtion. The reltionship between the vlues of c nd k is c 2 c + k + 1 Suppose tht there re four informtion bits (d 3, d 2, d 1, d 0 ) nd, s result, three prity check bits (c 1, c 2, c 3 ). The bits re prtitioned into groups s (d 3, d 1, d 0, c 1 ), (d 3, d 2, d 0, c 2 ), nd (d 3, d 2, d 1, c 3 ). Ech check bit is specified to set the prity of its respective group, i.e., c 1=d 3 +d 1 +d 0 c 2=d 3+d 2+d 0 c 3 =d 3 +d 2 +d 1 Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 6

7 Wht is Trnsprent Test? Trnsprent testing Leve the originl content of the circuit under test unchnged fter the testing is completed if no fults re presented Fetures Ensure the relibility of stored dt throughout its life time Provide better fult coverge thn non-trnsprent testing for unmodeled fults Limittion Must be performed while systems re idle Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 7

8 Principle of Trnsprent Testing RAM RAM RAM CONTENT XOR. TP NEW CONTENT XOR. TP CONTENT 1. Red (CONTENT), tke signture S(CONTENT) 2. Red (CONTENT), Write (CONTENT. XOR. TP)=NEW_CONTENT 3. Red (NEW_CONTENT), tke new signture S(NEW_CONTENT) 4. Write (NEW_CONTENT. XOR. TP) NEW_CONTENT. XOR. TP=CONTENT. XOR. TP. XOR. TP=CONTENT S(NEW_CONTENT)=S(CONTENT. S(CONTENT XOR. TP)=S(CONTENT). XOR. S(TP) Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 8

9 Issues of Trnsprent Testing Test interrupts In comprison with mnufcturing testing, one specil issue of trnsprent testing is tht the trnsprent testing process my be interrupted Alising If trnsprent built-in self-test scheme is considered, the signture genertion typiclly is done by MISR Fult loction If fult is detected, it is very difficult to locte the fult Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 9

10 A Typicl Trnsprent Mrch Test A typicl trnsprent Mrch test consists of two- phse testst Signture-prediction test Trnsprent Mrch test Types of trnsprent test schemes Trnsprent Mrch tests Symmetric trnsprent Mrch tests Combintion of Trnsprent Mrch tests nd ECCs Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 10

11 In test lgorithm Nottion D denotes the initil content of cell or word for bitoriented or word-oriented memories D is dt of the bit-wise XOR opertion on D nd ( ) represents the scending (descending) ddress sequence c denotes either scending or descending ddress sequence wx denotes write X opertion rx denotes red opertion with expect dt X Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 11

12 A Typicl Trnsformtion Method Bit-oriented mrch test Remove the initiliztion mrch element. Add Red opertion t the beginning of the first mrch element Replce r0 or r1 with rd or rd Replce w0 or w1 with wd or wd If the content of memory cell is the inverse of initil dt fter the lst Write opertion, insert two dditionl Red nd Write opertions in the end of the mrch test Trnsprent bit-oriented mrch test Remove ll Write opertions [M. Nicolidis, IEEE TC, 1996] Signture prediction lgorithm Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 12

13 An Exmple Consider the Mrch C- test: { c ( w0); ( r0, w1); ( r1, w0); ( r1, w0); ( r0, w1); c ( r0)} After Step 1 trnsformtion: { ( r0, w1); ( r1, w0); ( r1, w0); ( r0, w1); c ( r0)} After Step 2 trnsformtion: { ( rd, wd ); ( rd, wd ); ( rd, wd ); ( rd, wd ); c ( rd )} The content of memory cell fter the lst opertion is the sme s the initil stte. Step 3 is omitted. Thus, the trnsprent Mrch C- test is follows: { ( rd, wd ); ( rd, wd ); ( rd, wd ); ( rd, wd ); c ( rd )} Remove the Write opertions. The signture prediction lgorithm is s follows: { ( rd ); ( rd ); ( rd ); ( rd ); c ( rd )} { Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 13

14 Word-Oriented Trnsprent Tests Word-oriented trnsprent test cn be obtined By pplying the trnsformtion rules to ll the bits of ech word [Nicolids, ITC92]. E.g., word-orientedoriented Mrch C- for 4-bit words T1: T2: T3: { c ( w 0000 ); ( r 0000, w1111 ); ( r1111, w 0000 ); ( r1111, w 0000 ); ( r 0000, w1111 ); c ( r 0000 )} { c ( w 0101 ); ( r 0101, w1010 ); ( r1010, w 0101 ); ( r 0101, w1010 ( r1010, w 0101 ); c ( r 0101 )} { c ( w 0011 ); ( r 0011, w1100 ); ( r1100, w 0011 ); ( r 0011, w1100 ); ( r1100, w 0011 ); c ( r 0011 )} Thus, the trnsprent word-oriented Mrch C- T1 : { ( rd 0, wd ); ( rd, wd 0); ( rd 0, wd ); ( rd, wd 0); c ( rd 0, wd 1)} T2 : 0 0 { ( rd 1, wd ); ( rd, wd 1); ( rd 1, wd ); ( rd, wd 1); c ( rd 1, wd 2)} 1 1 T3 : { ( rd 2, wd ); ( rd, wd 2 ); ( rd 2, wd ); ( rd, wd 2 ); c ( rd 2, wd 0 )} ); Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 14

15 Problem Trnsprent tests re usully pplied in the idle stte of systems or components Reducing the test time is very importnt Avoiding the interrupt t of ftestingti However, conventionl trnsprent word-oriented mrch tests re directly obtined By executing the corresponding bit-oriented mrch test on ech bit of word Thus, conventionl trnsformtion does not generte time-efficiency word-oriented mrch test Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 15

16 Efficient Word-Oriented Trnsprent Tests Bit-oriented mrch test Replce the 0 or 1 of bit-oriented mrch test with ll-0 or ll-1 dt. Obtin mrch test clled SBMrch. If the first opertion of SBMrch is Write opertion, dd Red opertion in the beginning of SBMrch. TSMrch Replce ll r0 or r1 with rd 0 or rd 0 Replce w0 or w1 with wd 0 or wd 0 The lst Write opertion of TSMrch is wd 0 ATMrch= { c ( rd, TO1, TO2, K, TO TO = ( wd, wd, rd, wd, rd ) i i i i log B, wd )} i i The lst Write opertion of TSMrch is wd 0 ATMrch= { c ( rd0, TO1, TO2, K, TO 2 0 TO = ( wd, wd, rd, wd, rd i log B, wd )} ( i i i i i ) Trnsprent word-oriented mrch test= TSMrch+ATMrch Source: J.-F. Li, IEEE TCAD, 2007 (ccepted) Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 16

17 Exmple Consider bit-oriented i Mrch U [15] c ( w0); { ( r0, w1, r1, w0); ( r0, w1); ( r1, w0, r0, w1); ( r1, w0)} Then, the solid Mrch U (SBMrch U) is s follows r r r r r r r r r r r r r {c ( r 0, w 1, r 1, w 0); ( r 0, w 1); ( r 1, w 0, r 0, w 1); ( r 1, w 0)} { c ( w 0); where 0 r nd 1 r denote ll-0 nd ll-1 dt According to the trnsformtion ti rules described d bove, the trnsprent SBMrch U (TSMrch U) is { ( rd 0, wd, rd, wd ); (, ); (,,, ); (, 0)} rd 0 wd rd wd rd 0 wd rd wd 0 0 where 0 denotes ll-0 dt The lst opertion of TSMrch U is wd 0 ATMrch= c( rd, wd, wd, rd, wd, rd, wd, wd, rd, wd, ( rd, wd, wd, rd, wd, rd, wd ) Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 17

18 Feture Symmetric Trnsprent Tests The symmetric trnsprent test method tke dvntge of the symmetric chrcteristic of signture nlyzer to eliminte the signture prediction phse Symmetric chrcteristic ti of signture nlyzer Let sig(z, S, h)=u denote seril signture nlyzer which hs n initil stte S, feedbck polynomil h, dt string for nlysis z, nd the corresponding signture u. Then we cn obtin sig(z*, u*, h*)=s*, where z*, u*, h*, nd S* denote the reverse of z, u, h, nd S, respectively [V. N. Yrmolik nd S. Hellebrnd, DATE99] Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 18

19 An Exmple A 2n-bit dt string Z=(x 2n-1 x 2n-2 x n x n-1 x 1 x 0 ) is clled symmetric dt string if xn 1 = xn, xn 2 = xn+ 1, Kx1 = x2n 2, x0 = x2n 1 or x x x = x, K, x = x x x n 1 = n, n 2 n n 2, 0 = 2n 1 Consider symmetric dt string Z=(zz*). Assume tht reconfigurble signture nlyzer sig(-, 0,, h) is used to nlyze the symmetric dt string Z Step 1: z is nlyzed nd sig(z, 0, h)=u Step 2: nlyzer is configured s sig(-, u*, h*) Step 3: z* is nlyzed nd sig(z*, u*, h*)=0*=0 Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 19

20 Symmetric Trnsprent Mrch Tests A trnsprent Mrch test is symmetric trnsprent Mrch test if the red dt of the Red opertions of the trnsprent Mrch test is symmetric dt string Z For exmple, consider the Mrch test MATS+ { c ( w0); ( r0, w1); ( r1, w0)} It cn be trnsformed to trnsprent Mrch test { ( rd, wd ); ( rd, wd )} The red dt cn be expressed s Z=(z,z* c ) Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 20

21 Limittions Symmetric trnsprent Mrch tests hve two mjor limittions Fult msking effect Test interrupts cuse the symmetric chrcteristic i to be invlid Consider 4-bit memory with initil content (d 0 d 1 d 2 d 3 )=(0100). 00). Assume tht the memory hs n idempotent coupling fult in which the ggressor nd victim re t d 0 nd d 1. Also, the vlue of the victim is forced to 0 while the ggressor hs 0 to 1 trnsition Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 21

22 Fult Msking Effect Assume tht the symmetric trnsprent MATS+ is used to test 4-bit memory with CFid Trnsprent MATS+: ( rd, wd ); ( rd, wd )} { rd 0 d 0 d 1 d 2 d d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 Red dt (0000) wd d 0 is ddressed d 1 is ddressed d 3 is ddressed rd 0 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 Red dt (1111) wd d 0 is ddressed d 1 is ddressed d 3 is ddressed Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 22

23 Trnsprent Test Scheme for RAM with ECC Trnsprent BIST Code Genertion C Test 0 1 RAM 1 D Correction DI DO 0 Circuit Dt In D Red: Red the dt D t DO; Check if Code_Gen(D)=C Write: Write the dt D. XOR. TP Source: J.-F. Li, IEEE TCAD, 2007 (ccepted) Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 23

24 Fetures No signture prediction phse is needed. This shortens the testing time such tht the probbility of n interruption is reduced Relly restoring the originl content of the memory under test is chieved if the number of fulty bits of word is less thn the correction cpbility of the pplied ECC It cn locte the fulty bit of the fulty word by the checking response. The fult loction cpbility is lso relted to the correction cpbility of the pplied ECC Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 24

25 Exmple Consider 3x4-bit memory with Hmming ECC. Also, the trnsprent Mrch MATS+ is used to test the memory Trnsprent Mrch MATS+: { ( rd, wd ); ( rd, wd )} { Assume tht d2 of the first word hs stuck-t-0 fult d 3 d 2 d 1 d 0 h 2 h 1 h 0 d 3 d 2 d 1 d 0 h 2 h 1 h 0 d 3 d 2 d 1 d 0 h 2 h 1 h 0 W W W W W W W W W 2 h 0 =d 3 +d 1 +d 0 h 1 =d 3 +d 2 +d 0 h 2 =d 3 +d 2 +d 1 Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 25

26 Conclusions With the dvent CMOS technology, enhncing the relibility of n integrted t circuit it becomes one mjor chllenge Effective nd efficient relibility-enhncement techniques must be developed Vrious trnsprent test techniques hve been presented Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 26

27 References 1. M. Nicolidis, Theory of trnsprent BIST for RAMs, IEEE Trns. on Computers,vol. 45, no. 10, pp , Oct V. N. Yrmolik nd S. Hellebrnd, Symmetric trnsprent BIST for RAMs, in Proc. Conf. Design, Automtion, nd Test in Europe (DATE), 1999, pp J.-F. Li, Trnsprent test methodologies for rndom ccess memories with/without ECC, IEEE Trns. Computer-Aided Design of Integrted Circuits nd Systems, vol.26, no.10, pp , Oct Advnced Relible Systems (ARES) Lb., EE. NCU Jin-Fu Li 27