Efficiency Optimization of an Automotive Multi-Phase Bi-directional DC-DC Converter

Transcription

1 Efficiency Opimizaion of an Auomoive Muli-Phase Bi-direcional DC-DC Converer S. Waffler and J.W. Kolar Power Elecronic Sysems Laboraory ETH Zurich 892 Zurich, Swizerland Phone: Fax: Absrac The paper proposes mehods o improve he efficiency of a bi-direcional, muli-phase buck+boos DC-DC converer for applicaion in Hybrid Elecrical Vehicles (HEV) or Fuel Cell Vehicles (FCV). Thereo, he modulaion sraegy for a highly-compac, 3kW/Lier, consan-frequency sof-swiching converer is opimized based on a converer loss model ha includes he losses in he power semiconducors and he buck+boos inducor. An algorihm for numerical calculaion of he opimum swiching imes is given, whereas he values for he loss-opimized operaion of he converer are sored in a lookup-able ha is accessed by he digial conroller. In addiion, a novel mehod and conrol concep o ensure a Zero Volage Swiching (ZVS) of all semiconducor swiches by deerminaion of a zero volage across he MOSFET swiches wih analog comparaors is proposed ha resuls in he lowes inducor RMS currens for ZVS operaion a he same ime. Furhermore, a low oupu power an absolue efficiency gain of over 2.8% is achieved by parial operaion of he six inerleaved converer phases. A deailed descripion on he conrol concep ha deermines he opimum number of acivaed phases for he curren operaing poin of he converer is given and verified by experimenal resuls. The measuremens prove he capabiliy o insananeously swich he number of acive phases during operaion wihou a overshoo or drop in he converer oupu volage. Index Terms DC-DC Converer, Efficiency Opimizaion, Inerleaving, Muli-Phase I. INTRODUCTION Hybrid Elecrical Vehicles (HEVs) or Fuel Cell Vehicles (FCVs) have improved fuel economy and reduced emissions compared o convenional drive drains wih a single combusion engine []. Boh HEVs and FCVs require energy sorage elemens such as baeries or ulra-capaciors ha provide power o he elecric drive sysem during acceleraion and are used for regeneraive braking. The energy sorage elemens and he high volage (HV) inverer DC-link are conneced by bi-direcional DC-DC converers [2]. Requiremens for DC-DC converers in his applicaion are a high efficiency, an highly compac and low cos design as well as low EMI emissions. Therefore, o minimize he overall converer volume muli-phase converers are proposed [3][4][5] ha resul in a volume reducion for he passive componens. Typical mehods o improve he efficiency include sof swiching echniques [3] or he applicaion of Silicon Carbide (SiC) semiconducors [5]. An applicable bi-direcional buck+boos converer opology o inerconnec he HV baery of a HEV or FCV o he DClink is shown in Fig.. A consan-frequency sof-swiching modulaion of he MOSFET swiches S o ha is characerized by a negaive offse curren I a he sar of he pulse period T p, as depiced in Fig. 2 for he boos operaion mode, ensures a Zero Volage Swiching (ZVS) of he four swiches wihou an addiional circui effor [3]. An excellen efficiency over a wide oupu power range (cf. Fig. 9) and also for a wide volage ransfer raio /U is achieved. A picure of one ou of six converer phases ha has a power densiy of 3 kw/lier a a maximum oupu power of P 2,max = 2kW, an inpu volage range of U = 5..45V and an oupu volage range of = 5..45V is shown in Fig. 3. For furher efficiency improvemen of he converer phases, an algorihm based on he converer loss model ha idenifies he loss-opimized modulaion sraegy for he MOSFET swiches is presened in secion II and secion III. Addiionally, he efficiency of he muli-phase converer could be improved a ligh oupu power P 2 by parial phase operaion [5], bu no comprehensive heoreical resuls and measuremens of he ransien behavior when he number of acive phases is changed have been published so far. Therefore, he analyical U + C - side side 2 C oss C oss2 S i L () u () L u 2 () C oss3 C oss4 Fig.. Cascaded buck+boos converer for bi-direcional power-flow, shown wih parasiic MOSFET oupu capaciances C oss,i and he effecive loss resisance R i. R i C 2 + -

2 U +I I u, u 2, i L u () i L () u 2 () 2 3 T P of a converer phase module n, he exac ime funcion of inducor curren i L () mus be known, since he losses are approximaely proporional o he square of he inducor RMS curren (P loss IL,rms 2 ). Thus, he differenial equaion of he inducor curren including he loss resisor R i is solved for each of he ime inervals T i, under he assumpion of consan capacior volages U and and is given by S Fig. 2. Basic iming diagram for he swich S o conrol signals, he half-bridge volages u (), u 2 () and he inducor curren i L () for boos operaion ( > U ). Coolan Oule Inducor L (below cover) 4mm 3mm 23mm Liquid Cooler Filer Inducors MOSFET swiches Fig. 3. Phoo of a converer phase module wih a power densiy of 3 kw/lier a a maximum oupu power of 2kW. calculaion of he opimum number of phases o operae a parial load is given in secion IV and deailed experimenal resuls are provided in secion V. II. LOSS-OPTIMIZED MODULATION STRATEGY Efficiency opimizaion of he modulaion mehod depiced in Fig. 2 could be done analyically based on a converer loss model. Major loss mechanism are conducion losses in he swiches S o and he inducor L ha are modeled by a single effecive loss resisance R i conneced in series o he inducor L (cf. Fig. ). The numeric value of R i depends on he R ds,on of he four MOSFET swiches and on he inducor AC resisance for a given operaing poin and is varying for he four ime inervals T i = [ i.. i ]. The swiching losses and filer losses are negleced in he opimizaion, since hese are low for he given ZVS converer bu could also be modeled as par of he effecive loss resisance R i. In order o maximize he efficiency η(p 2,n ) = P 2,n P 2,n + P loss () i L,i () = (I L,i U L,i ) e R i L ( i ) + U L,i. (2) R i R i In (2), I L,i is he value of he inducor curren a he swiching ime i and U L,i he applied inducor volage ha is given by +U, U, and V in he four differen ime inervals T i. As can be seen from Fig. 4, here are differen combinaions of he swiching imes o 3 ha resul in he same converer oupu power 3 P 2 = i L ()d (3) whereas he bes efficiency is achieved for he swiching ime combinaion ha resuls in he lowes inducor RMS curren I L,rms since P loss IL,rms 2. However, wo consrains mus be me o form he inducor curren i L. Firsly, i L ( = T p ) mus mach he negaive offse curren I a he beginning of he subsequen pulse period I = i L,4 (T P ) (4) N swc oss L and a minimum magniude of I max(u, ) ha depends on he parasiic oupu capaciances C oss,i of he MOSFET swiches is required o provide sof-swiching condiions for he swiches S i. Secondly, also a = and = 2 he inducor curren mus be above I o achieve ZVS. These consrains induce a minimum swiching ime,min and a minimum lengh T 3,min of he ime inerval T 3. Since a ranscendenal equaion is obained when () is evaluaed wih (3) and (2) ha canno be maximized analyically, he imes o 3 for opimum efficiency are calculaed numerically for a given operaing poin (U,, P2,n). For insance, for he buck operaion mode (cf. Fig. 4 b)) he following algorihm is deployed: ) Shifing 3 oward he end of he pulse period and a maximum lengh of he ime inerval T 2 = [.. 2 ] resuls in he lowes RMS curren. Therefore, iniial values of =,min and 3 = T p T 4,min are chosen wih T 4,min as a small spare ime o compensae for inducor and swiching olerances. 2) Wih (2), known values of I, R i and he volages U and, he value of 2 is calculaed analyically. 3) Equaion (3) is evaluaed wih he resuls of seps ) and 2) and compared o he desired oupu power P2,n. In case of P 2,n < P2,n, is increased by he modulaion FPGA ime sep = ns, oherwise 3 is decreased by. 4) Seps 2) o 3) are repeaed unil P 2,n maches P2,n. A similar algorihm is uilized for he boos operaing mode. However, an iniial value for 2 is chosen o fulfill he

3 a) b) +I i L () U /L - /L P max 2 3 T p -I +I i L () U /L P max -U2 /L (U - )/L 2 3 T p -I (U - )/L Fig. 4. Degrees of freedom in selecion of he swiching ime 2 and 3 for he Boos operaion (a) and and 2 for he Buck operaion mode (b). consrain T 3 T 3,min, is calculaed analog o sep 2). 2 and 3 are adjused (cf. Fig. 4 a)) unil he desired oupu power is mached. A more deailed sysem model is advanageous in order o describe he influence of parasiic effecs on he ransferred power and on he efficiency. Therefore, wo addiional facors are considered in exension o he simplified model. Firsly, he oupu power P 2 srongly depends on he iniial value of i L () a he beginning of he pulse period, i.e. he offse curren I, especially for P 2. A uncerainy of I in he value of I leads o an error P 2,I = U T p Q 2 = U T p ( 3 ) I (5) in he oupu power. Therefore, a deailed model of I is required ha can be derived from he differenial equaions u L () = u () = L d d i L() i L () = i Coss () = N sw C oss (u ()) d d u () where C oss (u ()) is he nonlinear oupu capaciance of a single MOSFET and N sw is he oal number of MOSFETs applied for each half-bridge. The sysem of differenial equaions (6) can only be solved numerically due o he nonlinear characerisics of C oss (u ()) bu is uilized o calculae I (iniial condiions i L () = I, u = ) as well as he ime duraion of he resonan process iniiaed a a given value of i L. The calculaions are in good correspondence wih he offse curren I,min 25.5V max(u, ) +.9A. (7) (6) measured for he converer depiced in Fig. 3. Secondly, he volages U and are no consan bu show a superposed volage ripple ũ and ũ 2 respecively. Thus, also he volage applied o L varies over ime, resuling in an error P 2,U, whereas he influence of P 2,U is mos significan for equal volages U =. The deailed model ha is no shown in his paper also includes he differenial equaions for he capaciors C and C 2 o avoid ha error. Due o he high compuaion effor in he calculaion of he swiching imes wih he deailed model, he imes are no analyically calculaed by he Digial Signal Processor (DSP) bu deermined off-line by a compuer algebra program and sored in he DSP memory in he form of hree lookup-ables (LUT) in dependence on U, (LUT dimensions j, k) and I 2 (LUT dimension l). Assuming ha U, are measured and I 2 is equal o a conrol variable I 2,mod. Then e.g. is calculaed by consecuive inerpolaion,jkl,j+kl,jk+l,j+k+l,jkl+,j+kl+,jk+l+,j+k+l+, jkl, jk+l, jkl+, jk+l+, j kl, j k l (8), j kl+ in he hree LUT dimensions j, k, l o deermine he necessary iming for a given operaion poin. In (8), e.g.,jkl and,j+kl wih he indices j and j+ in he dimension j are he wo LUT elemens adjacen o he inpu quaniy U and, jkl is he linear inerpolaion of hese wo values in consideraion of he fracional par of U in respec o he wo values. III. OFFSET CURRENT CONTROL Besides he fac ha he value I mus be known o calculae he imes o 3 wih a sufficienly low error P 2,I, a higher magniude of I also increases he conducion losses. The addiional losses caused by an offse curren of I = I,min + I approximaely depends on he effecive loss resisance R 4 during he ime inerval T 4 ( P loss,i R 4 2I,min I + I 2 ) ( ) 3 (9) T p and become mos significan for a low oupu power P 2 since 3 is small in his case. Therefore, a closed loop conrol is implemened in he modulaion FPGA ha minimizes I o equal I,min. Two conrol conceps ha uilize digial signals generaed by fas analog comparaors, which monior he halfbridge volages u () and u 2 (), are applied depending on he operaing mode of he converer. In he buck operaion mode I mus be large enough o achieve ZVS a he inpu side of he converer, especially a =. An applicable conroller is shown in Fig. 5 and he

4 C (z) 2x - / -/ G I,bu 3,max 3,min z - 3a (z) a) u, u 2, i L b) c U u 2 () I hyseresis loop Fig. 5. b. I conroller for buck operaion, sampling ime T p, sampling poin i L () I,min 3a U U c c u, u 2, i L u () i L () u 2 () I C C 2 S 3a 3c 3b I > I,min diode D 3 charge Q D,3 3a,min I > I,min conducion of swich I C C 2 S Fig. 7. Deailed iming diagram of he swich S () o () gae signals and he comparaor signals C (), C 2 () for he boos operaion mode and = 3. The comparaor signal C 2 () is evaluaed by an hyseresis conroller ha adjuss he ime 3a ( is urned off) in order o minimize I. a c b 3a 3c 3b Fig. 6. Deailed iming diagram of he swich S () o () gae signals and he comparaor signals C (), C 2 () for he buck operaion mode and = and = 3. The comparaor signal C () is evaluaed by an inegral conroller ha adjuss he ime 3a ( is urned off) in order o minimize I. corresponding waveforms in Fig. 6. A b = a + T IL,, where T IL, is he inerlocking delay ime for he half-bridge a he converer inpu side, he analog comparaor signal { C () = for U U c, U c = 9% U () U < U c is sampled and scaled o / +. An inegral conroller wih gain G I,bu < ses he swiching ime 3a (urn-off of ). Thus, in he seady sae a negaive volage u L () = is applied o L during he ime inerval T 3, exacly long enough o obain he required value of I,min. The requiremens for ZVS of he oupu side half-bridge are fulfilled a he same ime since < U. However, for he boos operaion mode he concep described above is no applicable since wih a magniude of I = I,min ZVS condiions for he inpu side half-bridge are always fulfilled (cf. equaion (7)) and hus he comparaor signal C () canno be uilized o conrol he swiching ime of. On he oher hand, wih he ZVS modulaion sraegy as proposed in [3] and described in secion II i is essenial o have a feedback on he influence of he swiching ime 3. Oherwise, when he calculaed iming does no correspond o he acual siuaion in hardware, he average inducor curren migh drif oward zero as well as he ransferred power. A firs soluion o preven his problem is o urn off a 3a = 2 or a leas when i L ( 3a ) >. Then, in inerval T 3, he ani-parallel body diode D 3 conducs i L () for i L () >. A i L () =, D 3 blocks and during he subsequen resonan process i L charges C coss,3 and discharges C oss,4. Bu in addiion o he charge Q oss = N sw C oss ( ) sored in he MOSFET oupu capaciances, he diode diffusion charge Q D3 (reverse recovery charge) ha has been accumulaed during he diode conducion ime [6] now has o be considered and increases he offse curren. Diode recovery and lae urn-off of lead o a nonlinear dependence of I on 3a ha is depiced qualiaively in Fig. 7 (b). Assuming consan values for, 2, U,, a measuremen of 3b = 3c + T IL,2 (cf. Fig. 7 (a)), where T IL,2 is he inerlocking delay ime for he half-bridge a he converer oupu side, indicaes he end of he resonan process (ZVS urn-on of is allowed) and a lower 3b corresponds o a lower magniude of I. The ime insan 3b is deermined wih he help of he comparaor signal C 2 () = { for c < c, c = 9% () ha changes a = 3c and is inerpreed by he hyseresis conroller shown in Fig. 8. Due o he nonlinear behavior, he implemened conroller is a search algorihm ha coninuously adjuss 3a by T 3 and recognizes an improvemen or worsening of I. In he seady sae I,min is mainained wih a hyseresis loop as depiced in Fig. 7 (b). Boh offse curren conrol conceps are advanageous as no accurae high-speed DC curren measuremen of i L () is required.

5 sampling poin 3b a := 3a + T 3 limis exceeded? no N w imes worse? ( 3b > 3b,las ) yes yes inver direcion T 3 := - T 3 rese couners n w and n b Efficiency η Σ η n η Σ opimized no Relaive Oupu Power P 2 / P 2,max no N b imes beer? ( 3b < 3b,las ) yes Fig. 9. Measured efficiency and curve fi (blue), improved efficiency a low relaive oupu power P 2 /P 2,max by parial phase operaion (red). Fig. 8. Flow char of he I conroller for boos operaion, sampling ime T p, sampling poin 3b. IV. PARTIAL PHASE OPERATION In addiion o he loss reducion achieved by he uilizaion of he low-loss modulaion sraegy and he opimizaion of he swiching iming, wih a muli-phase converer furher improvemens in efficiency could be achieved in par-load condiions. For a muli-phase converer he overall converer oupu power is he sum of he oupu power of he N ou of N Σ acive phases: N P 2 = P 2,n. (2) n= A a low oupu power, for insance P 2 = 5% P 2,max and assuming ha all available phases operaed simulaneously (N = N Σ ) and wih he same power P 2,n, also he phase uilizaion is 5%. Typically he efficiency drops dramaically in his region due o he swiching losses or consan loss conribuions such as gae driver losses. Therefore, o improve efficiency, i is reasonable o urn off a cerain number of phases a ligh load condiions of he converer sysem. In order o deermine he number N ou of N Σ phases ha should be operaed a a cerain oupu power P 2, he measured efficiency η(p 2,n ) of a single converer phase is approximaed by a fi wih an analyical funcion. The fi funcion η(p 2,n ) = a b c P 2,n (3) P 2,n includes an inversely proporional erm ha primarily models he characerisic below he efficiency maximum and a linear erm o characerize he efficiency drop for a high oupu power. As depiced in Fig. 9 by a se of curves of he oal efficiency η Σ (P 2 ) = η(p 2 /N) in dependence on N, he efficiency is improved by parial phase operaion for ligh loads, whereas he oupu power P 2,sw (N) ha disinguishes beween N and N + operaed phases is calculaed by he inersecion of wo adjacen efficiency curves: ( η P 2,n = P ) ( 2 = η P 2,n = P ) 2 N N + a b N c P2 P 2 N = a b N + (4) P 2 c P 2 N + Solving (4) in respec o P 2 yields b N b ( ) P 2,sw (N) = N(N + ) 2 + N. (5) c c ha is approximaely a linear funcion in N. For he measured efficiency shown in Fig. 9 for U = 4V, = 2V, he coefficiens of he efficiency fi (3) are given by a = b = 2476 W c = W (6) and he vecor of power levels P 2,sw for changing he number of acive phases N is lised in able I. The expeced efficiency gain by parial phase operaion wih he efficiency characerisic depiced in Fig. 9 is approximaely 2.8% a P 2 = 5% P 2,max and 8.3% a P 2 = 2% P 2,max. TABLE I POWER LEVELS TO CHANGE NUMBER OF ACTIVE MODULES Acive Phases N Power P 2,sw Power per Phase kw 4.87 kw 2.44 kw kw 4.2 kw 2.8 kw kw 3.97 kw 2.98 kw kw 3.85 kw 3.8 kw kw 3.78 kw 3.5 kw V. EXPERIMENTAL RESULTS A block diagram ha illusraes he connecion of he phase modules and he implemenaion of he conrol concep o deermine he number N of acivaed phases is shown in Fig.. The phases, as depiced in Fig. 3, are individually

6 ,ref DSP G c,u I 2,ref P 2,sw G c,i G m,u U U,f,f LUT & I 2,mod Inerp... 3 N P 2 () (2) Onn Phase n Modulaor (FPGA) φ n I Conrol (3) s C L f,n Power Sage Phase i L f2,n I 2,f,f G m,i2 G m,u2 I 2 Bus Inerface C 2 Fig.. Inerconnecion of he N Σ phase modules by filer inducors L f,n, L f,n o common inpu and oupu capaciors C, C 2, conroller block diagram and communicaion inerface beween he converer phases. conneced by filer inducors L f,n and L f,n o he common inpu and oupu capaciors C and C 2. The volages U and as well as he oupu curren I 2 are measured, filered (filer ransfer funcions G m,u, G m,u2, G m,i2 ) and provided o a cascaded conroller wih reference volage inpu,ref. A comparaor wih hyseresis () ha is supplied wih he lis of power values P 2,sw (cf. able I) and he measured oupu power P 2 decides on he number N of acive phases. The curren conroller oupu I 2,mod is divided by N o calculae he reference for he phase oupu currens. This reference and he filered volages U,f and,f are uilized o calculae he swiching imes o 3 wih he help of he lookup-able (LUT) and inerpolaion (cf. secion II). Furhermore, he number N of acive phases is applied o a conroller (2) ha deermines he phases o acivae and calculaes he phase-shif angles ϕ n for a minimal oupu volage ripple in inerleaved operaion of he phases. Thereby, he phase shif angles are no necessarily equal o an ideal value of ϕ n = 36 /N bu are conrolled o compensae he influence of olerances in he inducors L ha cause subharmonics of he effecive swiching frequency f sw,eff = N/T p. The swiching imes, he phase shif angles ϕ n and he phase acivaion sae On n are passed o he phases ogeher wih a synchronizaion signal by a serial bus inerface. Each phase is equipped wih a FPGA ha generaes he gae signals s for he swiches S i and implemens he offse curren conrollers proposed in secion III. The urn-on of he second phase a U = 25V, = 6V and P 2 = 4.6kW, which is he wors case in respec o he power difference per phase (cf. able I), is shown in Fig.. Afer a shor period of ime he phase-shif conroller ses he opimum phase shif angles ϕ n and he volage ripple ũ 2 measured across he common oupu capacior C 2 reduces. Furher deails are depiced in Fig. 2 before (a), a (b) and afer (c) he urn-on of he second phase. Due o he quasinon-coninuous conducion mode ha is uilized o achieve ZVS, only a low amoun of energy is sored in he inducor L and he filer inducors L f. Therefore, an insananeous urnon or urn-off of a phase does no resul in an overshoo or drop of he oupu volage, as can be seen from he oupu ripple volage ũ 2 measuremen. Fig. 2 (b) also illusraes he funcionaliy of he offse curren conrol: Iniially, he inducor curren i L,2 of he second phase is zero and he herefore invalid iming is reason o an increased I a = 3. However, afer a few swiching periods he offse curren conroller compensaes ha error. The measuremens for he urn-on of he hird phase a U = 25V, = 222V, P 2 = 2kW is depiced in Fig. 3 and he urn-off of a second phase a U = 25V, = 23V, P 2 =.8kW in Fig. 4. In each case a smooh ransiion of he power flow beween he modules is observed. Afer a urn-off, he inducor curren i L () decays wih an damped oscillaion beween L and he oupu capaciances of he MOSFET swiches. Fig.. Overview on he urn-on process depiced in Fig. 2: The volage ripple ũ 2 across C 2 reduces afer he opimum phase shif angles ϕ n are se by he phase-shif conroller. u 2

7 u 2 u 2 u 2 i L, i L,2 (a) (b) (c) Fig. 2. Turn-on of he second phase a U = 25V, = 6V, P 2 = 4.6kW. Few swiching periods afer he urn-on insance he offse curren I is conrolled o a minimum and he phase shif is adjused o 8. Inducor currens i L,i, A/mV, oupu volage ripple ũ 2, V/mV. u 2 u 2 i L, i L,2 i L,3 i L, i L,2 Fig. 3. Turn-on of he hird phase a, U = 25V, = 222V, P 2 = 2kW. Inducor currens i L,i, A/mV, oupu volage ripple ũ 2, V/mV Fig. 4. Turn-off of he second phase a U = 25V, = 23V, P 2 =.8kW. Inducor currens i L, A/mV, oupu volage ripple ũ 2, V/mV VI. CONCLUSION In his paper differen mehods o opimize he efficiency of a bi-direcional muli-phase DC-DC converer are proposed. The overall converer efficiency benefis from he lower losses achieved wih he analyical opimizaion of he ZVS modulaion sraegy and he proposed conrol conceps for he offse curren ha reduces he inducor RMS curren. The novel concep ensures a Zero Volage Swiching (ZVS) of all semiconducor swiches by deerminaion of a zero volage across he MOSFET swiches wih analog comparaors insead of he applicaion of a high speed DC curren sensor. Furhermore, a concep for furher improvemen of he efficiency of he muli-phase converer a low oupu power by parial phase operaion is proposed and verified by experimenal resuls. An absolue efficiency improvemen of 2.8% is calculaed a 5% of he maximum oupu power. I is shown ha a sable oupu volage is mainained when swiching he phase coun during operaion. REFERENCES [] Williamson, S., Lukic, M., and Emadi, A., Comprehensive drive rain efficiency analysis of hybrid elecric and fuel cell vehicles based on moor-conroller efficiency modeling, IEEE Trans. Power Elecron., vol. 2, no. 3, pp , May 26. [2] Emadi, A., Williamson, S. S., and Khaligh, A., Power elecronics inensive soluions for advanced elecric, hybrid elecric, and fuel cell vehicular power sysems, IEEE Trans. Power Elecron., vol. 2, no. 3, pp , May 26. [3] Waffler, S. and Kolar, J. W., A novel low-loss modulaion sraegy for high-power bi-direcional buck+boos converers, in Proc. 7h Inernaonal Conference on Power Elecronics ICPE 7, Oc. 27, pp [4] Garcia, O., Zumel, P., de Casro, A., and Cobos, A., Auomoive DC-DC bidirecional converer made wih many inerleaved buck sages, IEEE Trans. Power Elecron., vol. 2, no. 3, pp , May 26. [5] Eckard, B. and Maerz, M., A kw Auomoive Powerrain DC/DC Converer wih 25kW/dm 3 by using SiC, in Power Conversion Inelligen Moion (PCIM), 26. [6] C. L. Ma, P. O. Laurizen, and J. Sigg, Modeling of power diodes wih he lumped-charge modeling echnique, IEEE Trans. Power Elecron., vol. 2, no. 3, pp , May 997.