Fatigue life estimation of FBGA memory device under vibration

Transcription

1 Journal o Mechanical Science and Technology 28 (1) (2014) 107~114 DOI /s Fatigue lie estimation o FBGA memory device under vibration Yusu Cinar and Gunhee Jang * Department o Mechanical Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-gu, Seoul, , Korea (Manuscript Received April 24, 2013; Revised August 5, 2013; Accepted August 9, 2013) Abstract This paper predicts the atigue lie o ine-pitch ball grid array (FBGA) solder joints in memory devices due to harmonic excitation through experiments and inite element analysis. Finite element models o the memory device with simpliied solder joints and with detailed solder joints were developed as a global model and a local model, respectively. A global-local modeling technique was used in the inite element simulation to calculate the stress magnitude o solder joints in the memory device under vibration. Stress versus lie (S-N) curve was generated or the memory devices under various vibration levels to derive the atigue constants o solder material. The atigue lie o the memory device was then determined by using the Basquin equation and Miner s rule. It was experimentally veriied that the predicted atigue lie o the memory device under cumulative damage conditions matches the experimental results within reasonable accuracy. Keywords: Basquin equation; Fatigue lie; Harmonic excitation; Memory device; Solder joint Introduction * Corresponding author. Tel.: , Fax.: address: ghjang@hanyang.ac.kr Recommended by Editor Jai Hak Park KSME & Springer 2014 Fine-pitch ball grid array (FBGA) package is a suracemounted integrated circuit package widely deployed in various applications such as dynamic random access memories (DRAMs), lash memory, handheld computing devices, and consumer electronics. DRAMs account or about one ith o the worldwide semiconductor market [1]. DRAM memory devices used in personal computers, workstations, and servers are composed o a number o packages mounted on a printed circuit board (PCB). These packages, which are integrated DRAM circuits, are mounted on PCBs using solder joints as presented in Fig. 1. The solder joints are used to transmit the electrical signals between the package chips and the PCB. Memory devices are exposed to vibration over various requency ranges [2], which may cause products to malunction. According to the U.S. Air Force, vibration and shock related ailures in electronic equipments are 20% under operation environments [2]. The reliability and perormance o memory devices are standardized by the Joint Electron Devices Engineering Council (JEDEC). The perormance and atigue lie o memory devices depend mainly on the solder joints. Predicting the atigue lie o solder joints in memory devices under various operating conditions is an important topic in designing the robust memory devices that are demanded by the manuacturing industry. Vibration results in dynamic stress in solder joints, and continuous vibration may lead to the ailure o electronic components. Thereore, the electronic packaging industry has taken an interest in understanding the atigue lie and reliability o solder joints under vibration. F.X. Che et al. [3] used the global-local modeling technique or three cases, including a plastic ball grid array (PBGA) assembly subjected to thermal cycling, a lip chip on-board assembly subjected to vibration, and the bending o a very thin quad lat non-lead package. Y. Cinar et al. [4] investigated ailure mechanisms o FBGA solder joints in memory devices under harmonic excitation. In their research, a swept sine test with a requency range between 20 and 2000 Hz showed that the resistance o memory devices continuously increased around the irst, second, and third natural requencies, and the biggest relative displacement between the package and the PCB occurs at the irst mode o the memory device. They ound that crack growth on solder joints inducing resistance increase reduces the stiness o the memory device, which decreases the natural requency o the memory device. F.X. Che, and H.L.J. Pang [5] studied lip chip solder joints under an out-o-plane sinusoidal vibration load with constant and varying amplitudes, and they used the Miner's cumulative damage law to estimate the atigue lie o lip chip solder joints. Several studies have determined the atigue constants o solder materials by using a stress versus lie curve. The most popular atigue constants o solder materials in the literature are those rom the Res. [2, 6]. Q.Z. Yao et al. [7] determined the solder material atigue constants

2 108 Y. Cinar and G. Jang / Journal o Mechanical Science and Technology 28 (1) (2014) 107~114 Table 1. Dimensions o the bare PCB and the packages o the memory device. Components Number o components (EA) Dimensions L x W x H (mm) Bare PCB x x Package x 7.50 x 0.77 Package register x 8.00 x Fig. 1. Section view o a solder joint. o Sn/Pb solder by using experimental test data. Y.S. Chen et al. [8] presented an S-N curve by combining both empirical and simulation tests to predict the vibration atigue lie o a single PBGA component. D. Yu et al. [9] investigated the high cycle atigue durability o SnAgCu alloys with dierent Ag content (SAC305 and SAC405) under random vibration. They developed S-N curves or SAC305 and SAC405 to predict the atigue lie o electronic components. Y. Cinar et al. [10] used the atigue constants ound in literature to calculate and compare the atigue lie o memory devices with dierent pad sizes. The atigue constants o solder material rom the Res. [2, 6] have been used in several studies or comparison with the data extracted rom their research [9] or to predict the atigue lie o solder joints [5, 10-13]. However, the atigue lie o FBGA solder joints has not been thoroughly investigated; prior research did not determine the atigue lie o FBGA solder joints in memory devices under high magnitude vibration by simulation or experiments, and the material constants or the atigue lie prediction o FBGA solder joints in memory devices has not been presented in the literature. The material constants presented in the literature have ailed to predict the atigue lie o memory devices [10]. This paper predicts the atigue lie o FBGA solder joints in a memory device with double-sided packages due to harmonic excitation through experiments and the inite element method. A inite element model o the memory device presented by the global-local model was developed, and the calculated displacements rom the global model were substituted along the boundary o the local model with detailed solder joints in order to calculate the stress magnitude o solder joints o the memory device under vibration. The atigue lie o the memory device was predicted using the Basquin equation and the Miner s rule, and was veriied experimentally. 2. Analysis model Fig. 2 shows the double-data-rate three synchronous dynamic random access memory (DDR3 SDRAM) memory device that was used in this study. It is composed primarily o a PCB, packages and package registers, and Sn-3.0Ag-0.5Cu solder joints. The PCB is composed o ten layers o copper (c) Fig. 2. A DDR3 SDRAM type memory module: ront view; back view; (c) side view. Fig. 3. BGA patterns o a package and package register: package; package register. conductor and FR-4, and the packages and package register are composed o a number o integrated circuits while the solder joints are composed o solder balls and solder pads. This memory device has 36 packages and 2 package registers. Table 1 shows the mechanical dimensions o the PCB, package, and package register. Two types o solder balls are used in the packages and the package registers. The BGAs o the package and package register have dierent patterns, as shown in Fig. 3. The red square in the package and package

3 Y. Cinar and G. Jang / Journal o Mechanical Science and Technology 28 (1) (2014) 107~ register in Fig. 3 indicates their orientations in the memory device in Fig S-N curve development or the memory device 3.1 Experiment Swept sine tests are required and have been standardized or memory devices by the JEDEC. The conditions o the swept sine test recommended by JEDEC or state that the peak acceleration should be 20 G with a requency range rom 20 to 2000 Hz at a constant logarithmic sweep rate (1 decade / minute) [14]. The swept sine test with a requency range between 20 and 2000 Hz showed that the resistance o the memory devices continuously increased around the irst, second, and third natural requencies, and the biggest relative displacement between the packages and the PCB occurs at the irst mode o the memory device and crack growth on solder joints inducing resistance increase reduces the stiness o the memory device, which decreases the natural requency o the memory device [4]. Thereore, only the irst mode is considered to generate a stress-lie curve. The requency range used in the experiment is rom 906 Hz to 1001 Hz, which is 5% above and below the irst natural requency. The sweep sine tests were carried out with excitation magnitudes o 20, 24, and 28 G. Two test samples are used or each excitation magnitude as shown in Table 2. The atigue lie o the solder joints can be observed by monitoring the resistance increase o the memory device with a daisy chain assembly as cracks increase the resistance. The 36 packages on the memory device, excluding the two package registers, were assembled in daisy chains. The daisychained packages on the ront and back o the memory device were connected in series. The total resistance o the memory device daisy chain was measured to be around Ohm. Failure o the solder joint is assumed to occur when the total resistance is greater than 300 Ohm [15]. The experimental setup shown in Fig. 4 was used to determine the atigue lie o the memory devices. An EDS electro-dynamic shaker was used to excite the memory device ixed on a jig. The variation in the input acceleration proile was measured with an accelerometer on top o the shaker that was controlled by VibrationVIEW sotware, as shown on the right side o Fig. 4. An electric voltage o 2.5 V was supplied rom a power supply to the memory device with the daisy chain assembly. Variations in the acceleration on the top o the shaker, current, and voltage were measured simultaneously in real time, and the acceleration and resistance (voltage/current) were then obtained using an oscilloscope. DDR-type memory devices are usually inserted in a slot in a motherboard, so the memory device ixed to the jig mounted on the shaker (shown in Fig. 4) had a ixed boundary condition o two short sides and one long side and a ree boundary condition o one long side based on the assumption that the boundary condition o the memory device in the slot is completely ixed. Table 2 shows the experimental results o the sweep sine test or two test samples at each excitation magnitude o 20, 24, and 28 G, and it can be Table 2. Time to ailure or memory devices (min). Sample no. 20 G 24 G 28 G Table 3. Number o cycles to ailure or memory devices (cycle). Sample no. 20 G 24 G 28 G 1 5,487, ,772, ,572, ,687, ,315, ,686,644.2 Fig. 4. Experimental setup used to monitor the atigue lie o memory devices. seen that the atigue lie decreases as the excitation level increases. The time to ailure given in Table 2 or memory devices should be converted into the number o cycles to ailure in order to develop an S-N curve. For a logarithmic sweep with a constant rate, Eq. (1) can be written as ollows [16]: log = At + B (1) where A and B are constants that determine the sweep rate. Eq. (1) can be written as ollows: 1 dt = d. Aln10 (2) The number o cycles or a logarithmic sweep in a requency range rom 1 (906 Hz) to 2 (1001 Hz) can then be calculated as ollows: D D n = D t =. (3) Aln10 Using Eqs. (1) and (3), the number o cycles to ailure o the memory devices was calculated and is listed in Table 3.

4 110 Y. Cinar and G. Jang / Journal o Mechanical Science and Technology 28 (1) (2014) 107~114 Table 4. Material properties o each component in the memory device. Component Material type Density (kg m -3 ) Young s modulus (MPa) Poisson s ratio (-) Element type Number o elements Bare PCB FR4 2, , brick 116,220 Package - 1, , brick 77,184 Package register - 2, , brick 13,928 Solder ball Sn-3.0Ag-0.5Cu 7, , brick 47, Finite element analysis by a global-local modeling technique Global model analysis The solder joints o memory devices are too small to measure the stress magnitude under various vibration levels. Finite element analysis can be used to calculate the stress magnitude on the solder joints. Finite element analysis o memory devices requires enormous computer memory and computational time because some components, such as solder balls, are very small relative to the overall size o the memory device. The global-local modeling technique has been suggested as an alternative approach with reasonable accuracy to calculate the stress magnitude o solder joints. In this study, the submodeling technique was used as a global-local modeling technique [17]. The cut boundary is the boundary o the local model (submodel), which represents a cut through the global model (coarse model). Displacements calculated on the cut boundary o the global model are speciied as boundary conditions or the local model with detailed solder joints. The accuracy o the submodeling technique depends on the cut boundaries, which should be ar rom the stress concentration region. A inite element model o a memory device with simpliied solder joints was developed as a global model, as shown in Fig. 5. Table 4 shows the material type and properties o each component. The PCB, packages, package register, and solder balls are modeled by linear brick elements with eight nodes, and each node has three degrees o reedom. In this global model, a solder ball is modeled as an octagonal structure with 16 elements. The total number o elements was 255,076. In the inite element model, the PCB, packages, and solder balls were connected by node sharing. Three sides o the inite element model were ixed to maintain the same boundary conditions as in the sweep sine test. The natural requencies and mode shapes were calculated using ANSYS. Experimental modal testing was perormed to veriy the proposed simulated results. Fig. 6 shows the experimental setup or the modal testing. An impact hammer was used to excite a memory device. The responses on the memory device were measured at 18 points using a laser Doppler vibrometer sensor and a PULSE 3560C signal analyzer. The mode shapes were determined using the STAR modal system. Table 5 shows a comparison between the undamped simulated and experimental natural requencies o the memory device. Fig. 7 shows a comparison between the simulated and experimental mode shapes o vibration modes 1, 2, and 3 in the memory (c) Fig. 5. Finite element model o a memory device: ront view; back view; (c) side view. Fig. 6. Experimental setup or modal testing. device. Table 5 and Fig. 7 show that the simulated natural requencies and the mode shapes match the experimental results closely. Fig. 8 shows the inite element model or the orced vibration analysis. Two short sides and one long side o the inite element model were rigidly coupled with a nodal mass. The dynamic response o a memory device subjected to harmonic excitation was investigated using the mode superposition. The accuracy o the mode superposition depends on how many

5 Y. Cinar and G. Jang / Journal o Mechanical Science and Technology 28 (1) (2014) 107~ Table 5. Simulated and measured natural requencies and modal damping ratios o the memory device. Mode Simulation Experiment number (Hz) (Hz) Error (%) Modal damping ratio (%) Table 6. Comparison o the number o elements in the global and local models. Component Number o elements (EA) Global model Local model Bare PCB 116,220 41,856 Package 77,184 46,544 Solder ball 47, ,832 Solder pad - 39,936 Fig. 8. Finite element model o a memory device or harmonic analysis. Fig. 9. Finite element model o a local model. (c) Fig. 7. Comparison o simulated and experimental results o three modes: mode 1; mode 2; (c) mode 3. modes are superposed to calculate the response. A convergence test was perormed by increasing the superposed mode numbers, and 50 modes were selected to calculate the response under vibration. The modal damping ratios o a memory device were calculated rom a plot o the requency response unction using the bandwidth (hal power) method or the three modes [18]. The modal damping ratios are listed in Table 5. These were inputted into the inite element model o the memory device. The method used or orced vibration analysis was explained previously [4]. Forced vibration analysis was perormed around the irst natural requency as prior research [4] showed that the irst mode is the most destructive mode up to 2 khz Local model analysis First, it must be conirmed that the cut boundary or the local model is ar enough rom the stress concentration region, because the accuracy o the submodeling technique depends on the cut boundaries. A inite element model o a part o the memory device, which is composed o packages, PCB, and detail solder joints, was developed as a local model with a veriied cut boundary, as shown in Fig. 9. The solder joints o the local model are modeled with detailed solder joints. The diameter and height o a solder ball are 500 µm and 350 µm,

6 112 Y. Cinar and G. Jang / Journal o Mechanical Science and Technology 28 (1) (2014) 107~114 respectively. Number o inite elements o each solder joint in the local model is 928 or volume o mm 3. The local model with total element numbers o 233,168 has the same element type as the global model. Table 6 compares the number o elements in the global and local models. Prior research results [4] showed that the packages near the ixed boundary o the memory device shown in Fig. 8 are the most vulnerable packages due to relative displacement; thereore, the local model with these packages (P15 in ront side and P33 in back side o memory module in Fig. 2) was analyzed by substituting the displacement variation along its cut boundary in order to calculate the stress on the solder joints under vibration. Fig. 10 shows the von Mises stress distribution or the P15-N6 solder joint. As shown, the maximum stress is concentrated at interace between the solder ball and pad with the PCB. 3.3 S-N curve Fig. 10. von Mises stress distribution or a P15-N6 solder joint: section view o the solder joint; solder ball and solder pads. von Mises stress (MPa) s = (2N ) R 2 = Number o cycles to ailure (cycle) The stress magnitudes rom the simulation and the number o cycles to ailure rom the experiments were obtained in order to develop the S-N curve shown in Fig. 11. A stressbased approach or high cycle atigue, called the Basquin equation and given in Eq. (4), is used because the number o cycles to ailure is over 10,000 cycles [19]. ( ) b ' s a = s 2N (4) Experiment Approximated Fig. 11. S-N curve o the solder joints in the memory device. ' where s a is the stress amplitude, s is the atigue strength coeicient, b is the atigue strength exponent, and 2N is the reversals o ailure (one reversal = ½ cycle). The von Mises stresses were calculated, and experiments were carried out or the memory devices at the 20 G, 24 G, and 28 G levels in the requency range rom 901 Hz to 1001 ' Hz. The material constants s and b can be derived rom Fig. 11 as MPa and , respectively. Regression coeicient (R 2 ) shows that there is a good agreement between experimental results and curve itting. In this research, material constants or the prediction o atigue lie o memory devices were determined rom experiment and simulation. Thereore, these constants could be applicable or same or very similar memory devices and more researches should be perormed to determine the limitation o these material constants. 4. Harmonic sweep test with the Miner s rule Memory devices are subjected to varying amplitudes o vibration over various requency ranges during transportation. The irst mode is the most dangerous among the modes up to 2 khz, and as the experiment proceeds, crack growth on the solder joints decreases the natural requency o the memory device [4]. Thereore, harmonic sweep tests were perormed at around 5% above and below the irst natural requency or each excitation level o 18 G, 22 G, and 26 G in sequence or 10 min each. The Miner s rule is one o the most widely used cumulative damage models or ailures caused by atigue. The atigue lie can be calculated using Eq. (4) at 18 G, 22 G, and 26 G levels around the irst mode. Damage or variable stress levels can then be superposed by the linear damage rule known as the Miner s rule shown in Eq. (5) [20]. D n k = å i total i= 1 N (5) i where k is the total number o various stress magnitudes applied, n i is the actual number o cycles under a speciic stress amplitude, and N i is the total number o cycles to ailure under a speciic stress amplitude. The Miner s rule states that ailure occurs when the total damage D total is equal to 1. Table 7 presents the stress level, the applied number o cycles, the number o cycles to ailure, the damage ratio, and the total damage rom the simulation. The stress levels were calculated at 18 G, 22 G, and 26 G. The number o cycles or ten minutes o excitation at each stress level can be calculated as 571,626.4 cycles by using Eqs. (1) and (3). Then the number o cycles to ailure (N i ) can be estimated by Eq. (4) using the ' calculated s and b values. The damage ratio is calculated or each excitation level as shown in Table 7. When D is equal to 1, the number o cycles to ailure is calculated as 4,508,989.1 cycles, which equals 78.9 min. Sweep sine tests were carried out on memory devices with

7 Y. Cinar and G. Jang / Journal o Mechanical Science and Technology 28 (1) (2014) 107~ Table 7. Stress level, applied number o cycles, number o cycles to ailure, damage ratio, and total damage rom simulation o the memory device. Excitation level, G i (G) Stress level, σ i (MPa) Applied number o cycles, n i (cycle) Number o cycle to ailure, N i (cycle) Damage ratio, D i Total Damage, D total , E , E , E , E , E , E , E , E Table 8. Simulated and measured time to ailure o two memory devices. Sample no. Time to ailure (min) Experiment Simulation Error (%) daisy chains in order to compare the analysis results with the experimental results. Sweep sine tests were perormed on two memory devices at excitation levels o 18 G, 22 G, and 26 G in sequence or 10 minutes each around the irst mode. The simulated and measured time to ailure values or two memory devices are shown in Table 8. The atigue lie o the memory devices matches the calculated results closely. 5. Conclusions This paper investigated the atigue lie o FBGA solder joints in memory devices due to harmonic excitation through the experiments and the inite element analysis. A global-local modeling technique was used in the inite element simulation to calculate the stress magnitude o solder joints. The atigue constants o SAC305 solder material or the atigue lie prediction were obtained at levels o 20 G, 24 G, and 28 G in the requency range rom 901 Hz to 1001 Hz, that is, 5% above and below the irst natural requency o the memory device. The atigue lie o the memory device was then predicted under harmonic excitation by using the Basquin equation and the Miner s rule. The atigue lie o the solder joints in two dierent memory devices with a daisy chain assembly was measured or experimental validation. The percentage error in the atigue lie o two memory devices varied rom 12.7% to 20.0%. It was experimentally veriied that the predicted atigue lie o the memory device matches the experimental results with reasonable accuracy under cumulative damage conditions. This research will be used to predict the atigue lie o dierent type o memory devices in various vibration conditions and to design robust memory devices. Reerences [1] J. J. Handy, What causes semiconductor cycles?, Forbes, < (2011) (accessed 1 Feb. 2012). [2] D. S. Steinberg, Vibration analysis or electronic equipment, 3rd edition, Wiley, New York, USA (2000). [3] F. X. Che, H. L. J. Pang, W. H. Zhu, Sun Wei, A. Y. S. Sun, C. K. Wang and H. B. Tan, Development and assessment o global-local modeling technique used in advanced microelectronic packaging, International Conerence on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems, EuroSime 2007, London (2007) 1-7. [4] Y. Cinar, J. Jang, G. Jang, S. Kim, J. Jang, J. Chang and Y. Jun, Failure mechanism o FBGA solder joints in memory module subjected to harmonic excitation, Microelectronics Reliability, 52 (4) (2012) [5] F. X. Che and H. L. J. Pang, Vibration reliability test and inite element analysis or lip chip solder joints, Microelectronics Reliability, 49 (7) (2009) [6] S. S. Manson, Fatigue: a complex subject some simple approximations, Experimental Mechanics, 5 (7) (1965) [7] Q. Z. Yao, J. M. Qu and S. X. Wu, Solder atigue lie in two chip scale packages, Proceedings o IEEE-IMAPS International Symposium on Microelectronics, Chicago, IL (1999) [8] Y. S. Chen, C. S. Wang and Y. J. Yang, Combining vibration test with inite element analysis or the atigue lie estimation o PBGA components, Microelectronics Reliability, 48 (4) (2008) [9] D. Yu, A. Al-Yaawi, T. T. Nguyen, S. Park and S. Chung, High-cycle atigue lie prediction or Pb-ree BGA under random vibration loading, Microelectronics Reliability, 51 (3) (2011) [10] Y. Cinar, J. Jang, G. Jang, S. Kim and J. Jang, Eect o solder pads on the atigue lie o FBGA memory modules under harmonic excitation by using a global-local modeling technique, Microelectronics Reliability, 53 (12) (2013)

8 114 Y. Cinar and G. Jang / Journal o Mechanical Science and Technology 28 (1) (2014) 107~ [11] T. E. Wong, B.A. Reed, H. M. Cohen and D. W. Chu, Development o BGA solder joint vibration atigue lie prediction model, Electronic Components and Technology Conerence, San Diego, CA (1999) [12] T. E. Wong, F. W. Palmieri, B. A. Reed, H. S. Fenger, H. M. Cohen and K. T. Teshiba, Durability/reliability o BGA solder joints under vibration environment, Proceedings o 49th Electronic Components & Technology Conerence (2000) [13] T. E. Wong, F. W. Palmieri and H. S. Fenger, Under-illed BGA solder joint vibration atigue damage, The Eighth Intersociety Conerence on Thermal and Thermomechanical Phenomena in Electronic Systems, Caliornia (2002) [14] JEDEC standard, Vibration, variable requency, JESD22- B103B, JEDEC Solid State Technology Association, Arlington, VA., USA (2002). [15] IPC, Guidelines or accelerated reliability testing o surace mount solder attachments, IPC-SM-785, IPC-Association Connecting Electronics Industries, Bannockburn, IL, USA (1992). [16] J. M. Hu, Sinusoidal vibration tests or product durability validation, European patent (1997). [17] ANSYS Version 7.0 Manual, Ansys Inc. (2002). [18] C. W. de Silva, Vibration undamentals and practice, Taylor-Francis, CRC Press, Boca Raton, FL, USA (2000). [19] O. H. Basquin, The exponential law o endurance tests, Proceedings o the American Society or Testing and Materials, West Conshohocken, PA, USA, 10 (1910) [20] M. A. Miner, Cumulative atigue damage, Journal o Ap- plied Mechanics (1945) A-159-A-164. Yusu Cinar received the B.S. degree in Mechanical Education and the M.S. degree with the best master thesis award in Energy Systems Engineering rom Marmara University, Istanbul and Gebze Institute o Technology, Kocaeli Turkey in 2003 and 2007, respectively. He is currently working toward the Ph.D. degree in Mechanical Engineering at Hanyang University, Seoul, Korea. His research interests involve the ailure analysis and reliability o electronic components. Gunhee Jang received the B.S. in Mechanical Engineering rom Hanyang University, Seoul, Korea in 1984, the M.S. in Mechanical Engineering rom Korea Advanced Institute o Science and Technology (KAIST), Seoul, Korea in 1986 and the Ph.D. in Mechanical Engineering rom University o Caliornia, Berkeley, USA in He is a proessor in the Department o Mechanical Engineering and the director o the Precision Rotating Electromechanical Machine Laboratory (PREM) in Hanyang University, Seoul, Korea. His current research is ocused on the ailure analysis and reliability o electronic components. He has authored or coauthored over 220 articles published in journals and conerences in his eld and the holder o several international patents.