HIGH-THROUGHPUT DUAL-MODE SINGLE/DOUBLE BINARY MAP PROCESSOR DESIGN FOR WIRELESS WAN

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1 HIGH-THROUGHPUT DUAL-MODE SINGLE/DOUBLE BINARY MAP PROCESSOR DESIGN FOR WIRELESS WAN Chun-Yu Chen Cheng-Hung Lin and An-Yeu (Andy) Wu Graduate Intitute of Electronic Engineering and Departent of Electrical Engineering National Taiwan Univerity Taipei 06 Taiwan R.O.C. ABSTRACT In thi paper we preent the VLSI ipleentation of a high-throughput enhanced Max-log-MAP proceor that upport both ingle-binary (SB) and double-binary (DB) convolutional turbo code. The cobined hybrid-window (HW) and parallel-window (PW) MAP decoding i introduced to upport arbitrary frae ize with high throughput. A.28 2 dual-ode (SB/DB) 2PW-HW MAP proceor i alo ipleented in TSMC 0.3 CMOS proce to verify the propoed approache. The propoed MAP proceor can be ued a hardware accelerator in ultitandard platfor for wirele WAN with low cot and low energy. Index Ter hardware accelerator turbo code axiu a-poteriori probability.. INTRODUCTION With the rapid growth of ultiedia ervice forward error correcting (FEC) code ha been a regular chee for wirele counication to have a reliable traniion over noiy channel. Single-binary convolutional turbo code (SB-CTC) propoed in 993 [] ha been the well-nown FEC code that can achieve acceptable data rate and coding gain cloe to the Shannon liit. The reduction of the CTC in bit error rate i achieved at the expene of intenive coputation involved in the iterative turbo decoding tep and with the powerful algorith called axiu a- poteriori probability (MAP) algorith. Duo to the large ipleentation coplexity the MAP algorith i approxiated a enhanced Max-log-MAP (EML-MAP) in [2] with all perforance degradation. The noticeable error correction perforance ade SB- CTC code an adopted FEC chee for WCDMA HSDPA and 3GPP-LTE [3]. In 999 the non-binary CTC [4] wa introduced to have uperior coding gain than the SB-CTC. In recent year the double-binary CTC (DB-CTC) wa adopted in advanced wirele counication tandard uch a WiMAX [5]. The detailed pecification and CTC chee of the prevalent wireletandard i lited in Table. To deal with different CTC chee the baeband architecture need to ipleent ultiple applicationpecific CTC decoder. However it reult in an intolerable increae in the nuber of application-pecific integrated circuit (ASIC) acro within the platfor. In thi paper we propoe a reconfigurable MAP proceor deign for different CTC chee. The propoed MAP proceor can be the deterinitic or reconfigurable FEC coponent of the obile device. We can either ipleent the propoed MAP proceor into a 3GPP or WiMAX baeband ASIC. Beideeveral MAP proceor can be ued in a prograable ultitandard platfor. The propoed MAP proceor ha featuretated a follow Support of dual-ode SB and DB CTC Support of high throughput parallel-window (PW) and hybrid-window (HW) MAP decoding Efficient calability and reconfigurability. To verify the propoed approache the firt dual-ode (SB/DB) 2PW-HW MAP proceor i ipleented in 0.3 CMOS proce. The propoed MAP proceor can be hardware accelerator in ultitandard platfor for wirele WAN with low cot and low energy. Table. Specification of the prevalent wirele wide area networ (WAN) Standard UMTS 3GPP [3] IEEE [5] WCDMA HSDPA 3GPP LTE Mobile WiMAX Fixed WiMAX Specification R 99/Rel.4 Rel.5 Rel e Max. data rate 2 Mbp 4.4 Mbp 00 Mbp 5 Mbp 75 Mbp Bit error rate CTC chee SB CTC DB CTC Frae ize 40 ~ ~ /08/$ IEEE 83 SiPS 2008

2 2. FUNDAMENTALS OF MAP ALGORITHMS 2.. Single-Binary (SB) MAP decoding The radix-2 SB EML-MAP algorith decide binary encoded bit u on the ign bit of the a poteriori loglielihood ratio (LLR). By the loo-ahead technique [6] SB EML-MAP algorith can wor in radix-4 trelli. Initially the branch etric are coputed a pi pi ( S2 S ) ( apr ( u ) y ) x y x i pi pi ( apr ( u ) y ) x y x i where apr i a priori LLR x x pi {- +} denote the tranitted codeword y and y pi denote the oft received value and i the nuber of each parity bit (= for UMTS 3GPP tandard). Note that x i the yteatic bit which equal to 2u - for BPSK. Then the forward recurion tate etric and bacward recurion tate etric i coputed a ( S ) MAX( ( S S ) ) S S 2 S. S () (2) ( S ) MAX( ( S S ) ). Finally the a poteriori LLR i defined a ( u ) MAX ( ( S ) ( S S ) apo S2 S u MAX ( ( S ) ( S S ). S2 S u ( u ) MAX ( ( S ) ( S S ) apo S2 S u MAX ( ( S ) ( S S ). S2 S u Then the firt ter in (3) i rewritten a (0) MAX MAX ( ( S ) ( S S ) S 2 S S2 S MAX ( ( S ) ( S S ) () 2 2 where (ij) denote the tranition fro u - = i to u = j. By defining (z) a MAX ( ( S ) ( S S ) S S (0) (0) MAX 2 S2 S2 S S2 S S (0) (0) MAX 2 S2 S2 S S2 S S () () MAX ( 2( S2) ( S2 S) S S2 S ( ( ) ( ) ( )) ( ( ) ( ) ( )) ( )) apo- (u - ) and apo (u ) are rewritten a apo ( u ) MAX( (0) () ) MAX( (0) ) (6) apo ( u ) MAX( (0) () ) MAX( (0) ). The ign bit of the a poteriori LLR value decide whether u = 0 or u =. The extrinic inforation i defined a apo ( u ) ex ( u ) apr ( u ) y 2 (7) apo ( u ) ex ( u ) apr ( u ) y 2 (3) (4) (5) where i a caling factor (0 < < ) for EML-MAP decoding Double-Binary (DB) MAP decoding The radix-4 DB EML-MAP algorith decide binary inforation bit u = (u a u b ) at tie on the value of the a poteriori inforation. Initially the branch etric are 2 ( z) ( z) i i pi pi S S apr u z y x y x i i (8) ( ) ( ) 2 2 where (z) apr i a priori inforation and z { } x i pi x {- +}denote the tranitted codeword i pi y and y denote the oft received value and i the nuber of each parity bit (=2 for IEEE 802.6e tandard). Note that x and x 2 are the yteatic bit which equal to 2u a - and 2u b - for BPSK repectively. The forward and bacward tate etric are ( S ) MAX( ( S S ) ( z) S ( S ) MAX( ( S S ). S ( z) The a poteriori inforation (z) apo i defined a ( u ) MAX ( ( S ) ( S S ) ( z) ( z) apo S- S uz MAX S S- S u00 S S S ( ( ) ( ) ( )). (9) (0) A in the radix-4 SB decoding we define the ybol reliability etric d(z) a. MAX ( ( S ) ( S S ) d S S d(0) (0) MAX S S S S S S d(0) (0) MAX S S S S S S d() () MAX ( ( S ) ( S S S S S ( ( ) ( ) ( )) ( ( ) ( ) ( )) ) ( )). Then we can copute (z) apo a follow: apo (0) apo (0) apo () apo ( u ) 0 ( u ) ( u ) ( u ) d (0) d (0) d () Deciion u = z are baed on d d. d zarg MAX( ( u ) ( u ) ( u ) ( u )). z (0) (0) () apo apo apo apo () (2) (3) The extrinic inforation (z) ex i defined a (z) ( ) ( ) ( ) ( u ) z ( u ) z ( u ) z ( u ) (4) ex apo apr in where the intrinic inforation (z) in i defined a in (0) in (0) in () in ( u ) 00 ( u ) 4y 2 ( u ) 4y ( u ) 4( y y 3. ARCHITECTRUE OF HIGH-THROUGHPUT DUAL-MODE 2PW-HW MAP PROCESSOR 2 ). (5) 84

3 3.. 2PW-HW MAP Decoding To achieve high throughput parallel window (PW) and hybrid window (HW) decoding wa introduced in [8] and [9] repectively. Fig. how the baic tiing chart of the PW and HW MAP decoding. The vertical axi denote the decoding ybol and the horizontal axi denote decoding tie axi. L refer to the window ize. Fro the tiing chart the decoding latency of PW MAP decoding i L. However the area cot and power conuption of PW MAP decoding i intolerably increaing for large CTC frae. HW MAP decoding can proce a large CTC frae under reaonable hardware cot becaue of the parallel proceing in equential tie. However the decoding latency of the HW MAP decoding i 4L and an additional recurion proceing eleent (RP) called a duy bacward RP (DRP B ) i required to provide the reliable initial tate of to RP B. We propoe 2PW-HW MAP decoding to have the advantage of both PW and HW MAP decoding. By the analyi of PW and HW tiing chart in Fig. the propoed architecture of MAP proceor can run in either PW or HW MAP decoding. With the effective control unit deign the MAP proceor can perfor 2 PW or HW MAP decoding baed on the uer requireent. Fig.2 how the overall architecture of the propoed 2PW-HW MAP proceor. The proceor i copoed of 4 branch etric unit (BMU) 8 branch etric cache (BMC) 2 bacward recurion proceing eleent (RP B ) 2 forward recurion proceing eleent (RP A ) 4 tate etric cache (SMC) and 4 loglielihood ratio unit (LLR). Fig.. Tiing chart of (a) PW (b) HW Fig.2. Architecture of the propoed 2PW-HW MAP decoding in (a) HW ode (b) PW ode 3.2. Dual-ode branch etric unit (BMU) Both the SB and DB MAP decoding in radix-4 trelli require toring 6 branch etric into BMC according to () and (8) (= for 3GPP SB CTC =2 for WiMAX DB CTC). The deign challenge for dual ode BMU i to reduce the torage aount of branch etric and coputational logic for both SB and DB branch etric. In [0] a decopoed branch etric of the radix-2 SB MAP decoding wa propoed. We can further extend it for radix-4 DB MAP decoding. Firt the 6 branch etric in (8) i defined a (g) d where g = [(x +)/2 (x 2 +)/2 (x p +)/2 (x p2 +)/2] 2 and d denote the DB MAP decoding. Then the branch etric i decopoed into 0 2 d apr ( u ) 2y 2 y (0) 2 d apr ( u ) 2y 2 y 2 (0) 2 d apr ( u ) 2y 2 y (6) 3 () 2 d apr ( u ) 2y 2 y 0 p p2 d 2y 2 y p p2 d 2y 2 y. Now we only tore 0 d d 2 d 3 d 0 d and d into the BMC. Finally by the pot-coputing the 6 branch etric (g) d can be recovered by ( g ) i h j (7) d d d d where h d {- +} i {0 2 3} j {0 } and g = [(i/2) floor (i) od2 (h d +)/2 ((h d +)/2+j) od2 ] 2. (x) floor denote the larget nuber no bigger than x. And the a priori ter can be coputed by (0) apr (0) apr () apr ( u ) 4y ( u ) 4y ( u ) 4y y (8) The decopoition of branch etric for radix-4 SB MAP decoding i in the iilar way. We define the 6 branch etric in () a (g) where g = [(x - +)/2 (x p - +)/2 (x +)/2 (x p +)/2] 2 and denote the SB MAP decoding. The branch etric of radix-4 SB MAP decoding can be decopoed into 0 apr ( u ) apr ( u ) y y apr ( u ) apr ( u ) y y 2 apr ( u ) apr ( u) y y (9) 3 apr ( u ) apr ( u ) y y 0 p p y y p p y y Then the 6 branch etric (g) can be coputed by ( g ) i h j (20) where h {- +} i j {0 } and g = [(i/2) floor (i) od2 (h +)/2 ((h +)/2+j) od2 ] 2. The a priori ter can be coputed by 85

4 2 3 apr ( u ) y ( )/2 2 3 apr ( u ) y ( )/2. (2) Baed on the obervation of the branch etric decopoition in (6) and (9) the architecture of dualode BMU pre-coputation logic bloc ihown in Fig. 3. All the ultiplexer are controlled by the SB/DB (0/) ode ignal. For the recovery of branch etric in (7) and (20) the pot-coputation logic bloc i the ae in SB ode and DB ode. Fig.4. Trelli diagra of (a) WiMAX (b) 3GPP Fig.3. Pre-coputation logic bloc of BMU 3.3. Dual-ode radix-4 trellitructure Becaue of the different generator polynoial of WiMAX and 3GPP CTC the radix-4 trellitructure for add-copare-elect unit (ACSU) connection are different to each other. Baed on the obervation of the trelli tructure we realize that both tandard have two radix-4 butterflie. We can eparate the two butterflie (indicate by dahed line in Fig.4). Fro Fig.4 the two trellitructure are the ae if we regard the tate 2 of 3GPP a the tate 7 of WiMAX the tate 3 of 3GPP a the tate 6 of WiMAX the tate 6 of 3GPP a the tate 3 of WiMAX and the tate 7 of 3GPP a the tate 2 of WiMAX. Fro the eparation only the tate index nuber changeo there i no hardware overhead for ACSU connection. However becaue of different branch path for 3GPP LTE and WiMAX we need to inert everal ultiplexer in front of ACSU to chooe the appropriate branch etric Dual-ode Log-lielihood ratio unit (LLR) Baed on the obervation in (5)-(6) and ()-(2) the MAX operator of d(z) are the ae a that of (z) and the coputational hardware can be hared. Fig.5 how the architecture of the LLR odule for the radix-4 dual-ode (SB/DB) MAP decoding. We let the path LL (z) be the output of the hared MAX operator of d(z) and (z). The MAX (z) operator chooe the larget LL (z) value fro 8 poible cobination. Then the Lapo calculator perfor three ubtraction for (z) apo in (2) to obtain DB LLR and two ubtraction and four MAX operation for apo and apo- in (6) to obtain SB LLR. The hared hardware deign of the dual-ode Lapo calculator ihown in Fig.6. Fig.5. LLR odule for the radix-4 dual-ode MAP proceor Fig.6. Lapo calculator for the dual-ode MAP proceor 4. EXPERIMENTAL RESULTS We firt analyze the throughput and copare the required hardware to HW MAP decoding. To eet the pecification of wirele WAN in Table the expected throughput i 00 Mbp when CTC frae ize are 240 and The PW MAP decoding i ignored becaue of unacceptable hardware cot. In Fig.7 the 0 HW and 5 2PW-HW proceor can eet the throughput in frae ize of 240. However the throughput of 0 HW MAP proceor in frae ize of 2400 i far beyond the expected 00 MHz throughput with extra hardware reource. A fat and accurate hardware evaluation of the propoed high-throughput SB/DB MAP proceor i obtained by uing Verilog HDL codeyntheized with the tandard cell library of TSMC 0.3 CMOS Proce uing Synopy 86

5 Deign Coplier. Under the hardware evaluation the area of 0 HW MAP proceor require.37 tie area of 5 2PW-HW MAP proceor to eet the throughput requireent of wirele WAN. In Table 2 the total hardware overhead of one dual-ode (SB/DB) 2PW-HW MAP proceor i le than 0% (8.9%) copared to the DB 2PW-HW MAP proceor. Fig.7.Throughput coparion of the propoed 2PW-HW MAP decoding with HW MAP decoding The propoed dual-ode (SB/DB) 2PW-HW MAP proceor i alo ipleented by TSMC 0.3 CMOS proce. The ipleented MAP proceor occupie core area of.28 2 and achieve the axiu operating frequency of 25 MHz. The throughput rate are reported without conidering the latency and iteration of CTC decoding. The power conuption on 2-dB SNR noiy data are etiated by Synopi PriePower. In PW (HW) ode the propoed MAP proceor achieve throughput rate of 500 Mbp (250 MHz with power of W (74.95 W). The wor in [7] and [] perfor the radix-2 and radix-6 SW MAP decoding repectively and can only upport SB CTC. Our propoed highthroughput MAP proceor can upport both SB and DB CTC and achieve decoding throughput with low energy conuption in ter of the noralized decoding energy (noralized-power/throughput) copared to [7] and []. In addition the propoed MAP proceor cobine PW and HW decoding o that deigner can duplicate the proceor to achieve high throughput rate. 5. CONCLUSION In thi paper the high-throughput dual-ode (SB/DB) EML-MAP proceor for wirele WAN ha been preented and ipleented. For variou CTC frae the propoed 2PW-HW MAP decoding eet the expected throughput with low area cot. Beide the odule deign of dualode SB/DB MAP decoding wa preented and the overall hardware overhead copared with the individual DB MAP decoder i le than 0%. The propoed MAP proceor ha been ipleented in core ize of.28 2 by 0.3 CMOS proce and achieved axiu throughput rate of 500 Mbp@25 MHz with decoding energy of 0.9 nj/bit. Table 2. Area coparion of the individual DB and dual-ode MAP proceor (TSMC 0.3 Module DB only (u 2 ) Dual-Mode Hardware (SB/DB) (u 2 ) Overhead BMU % RP % LLR % One 2PW-HW MAP Proceor % Table 3. Coparion of the MAP proceor MAP Decoder [7] []* Propoed* Technology SB/DB ode Radix-2 SB Radix-6 SB Radix-4 SB/DB MAP Decoding SW L-MAP SW ML-MAP 2PW-HW EML-MAP Supply Voltage.8 V.2V.2 V Max. Frequency 285 MHz 238 MHz 25 MHz Core Size Throughput Rate 500 Mbp (2PW) 285 Mbp 952 Mbp (Hard Bit) 250 Mbp (HW) Power Conuption Noralized Decoding 330 W 528 W (@.32V) 0.27 nj/bit 0.46 nj/bit * The evaluation i reported by pot-layout iulation W (2PW) W (HW) 0.9 nj/bit (2PW) 0.30 nj/bit (HW) REFERENCES [] C. Berrou A. Glavieux and P. Thitiajhia Near Shannon liit error-correcting coding and decoding: Turbo Code in Proc. ICC. 993 pp [2] J. Vogt and A. Finger Iproving the ax-log-map turbo decoder Electron. Lett. vol. 36 no. 23 pp Nov [3] (Online) [4] C. Berrou and M Jezequel Non binary convolutional code for turbo coding Electron. Lett. vol. 35 no. pp Jan [5] (Online) [6] S.-J. Lee N.R. Shanbhag and A.C. Singer Area-efficient high-throughput MAP decoder architecture IEEE TVLSI vol. 3 no. 8 pp Aug [7] A 285-MHz pipelined MAP decoder in 0.8u CMOS IEEE JSSC no. 8 pp Aug [8] A. Wor H. La N. Wehn A high-peed MAP architecure with optiized eory and power conuption in Prof. IEEE SiPS 2000 pp [9] M.M. Manour N.R. Shanbhag VLSI architecture for SISO-APP decoder IEEE TVLSI. vol. no. 4 pp Aug [0] T.-H. Tai C.-H. Lin and A.-Y. Wu A eory-reduced log-map ernel for turbo decoder in Prof. IEEE ISCAS 2005 pp [] C.-H. Tang et al. A 952MS/ Max-Log MAP Decoder Chip uing Radix-4x4 ACS Architecture in Proc. IEEE A-SSCC 2006 pp