Low complexity state metric compression technique in turbo decoder

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1 LETTER IEICE Electronics Express, Vol.10, No.15, 1 7 Low complexity state metric compression technique in turbo decoder Qingqing Yang 1, Xiaofang Zhou 1a), Gerald E. Sobelman 2, and Xinxin Li 1, 3 1 State Key Laboratory of ASIC & System, Fudan university, Handan road 220, , Shanghai, China 2 Dept. of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN USA 3 State Key Lab of Transducer Technology, Shanghai Institute of microsystem and Information Technology, Chinese Academy of Science, Shanghai , China a) xiaofangzhou@fudan.edu.cn Abstract: A novel compression technique for modulo-normalized state metrics in turbo decoder is presented. This technique performs the compression dynamically according to the range of state metrics. The framework of the compression circuit is given. BER performances for several turbo decoders are simulated. Implementation results show that the proposed technique needs only 25.2% logic gates and 77.5% memory bits of the existing method with same BER performance loss and much shorter critical path for eight state turbo codes. For four state turbo codes, 30.1% logic gates and 75% memory bits are required. Keywords: turbo decoder, data compression, state metrics Classification: Integrated circuits References [1] C. Studer, C. Benkeser, S. Belfanti and Q. Huang: IEEE J. Solid-State Circuits 46 [1] (2011) 8. [2] Y. Wu, B. D. Woerner and T. K. Blankenship: IEEE Trans. Commun. 49 [11] (2001) [3] M. Martina and G. Masera: IEEE Trans. Circuits Syst. I, Reg. Papers 58 [5] (2011) [4] S.-J. Lee, N. R. Shanbhag and A. C. Singer: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 13 [8] (2005) 921. [5] J.-H. Kim and I.-C. Park: IEEE Trans. Circuits Syst. II, Exp. Briefs 56 [1] (2009) Introduction It has been shown that modulo-normalization [2] is one of the best candidates for normalization of the state metrics (SMs) in high-throughput turbo decoder because of its short critical path [1]. However, this normalization method usually requires more bits to represent SMs than 1

2 actually needed in case that the differences of SMs overflow, leading to more memory bits for SM storage. Existing published compression techniques for SMs are saturation method (SAM), non-uniform quantization (QM) and Walsh-Hadamard transform followed by non-uniform quantization (WM) [3]. However, SAM is not as efficient as QM and WM for reducing memory bits; QM degrades BER performance heavily; WM improves BER performance by complex transformations outside QM, but with the cost of much higher complexity. In this paper, we propose a novel compression technique with lower hardware complexity compared with WM, based on the idea of quantizing the SM according to the range of SM differences adaptively. 2 Turbo decoder Turbo decoder has been extensively investigated since the appearance of turbo code [4, 5]. We just briefly review the turbo decoder structure in this section. Fig. 1 shows the trellis and a radix-2 decoder for a traditional turbo code of 1/3 code rate and Ns states, on which our study is based. We use k i Fig. 1. (a) trellis of SISO decoder (b) turbo decoder architecture 2

3 and k r as notations for LLRs (log-likelihood-ratio) of the k-th information and redundancy bit, k e for the k-th extrinsic information, k x;y =rk x;y for the k-th branch metrics on the trellis with x/y referring to the information/ redundancy bit, and k = k for the k-th forward/backward state metrics. The SISO decoder implements the Log-MAP algorithm described as follows: 1) Branch metric calculation: x;y k ¼ x k i þ k e;old þ y k r ; rk x;y ¼ y k r 2) Forward SM calculation: k s ¼ s1!s:1;y1 max s0!s:0;y0 k 1 s0 þ 0;y0 k 1;k 1 s1 þ 1;y1 k 1 3) Backward SM calculation: s k 1 s!s1:1;z1 ¼ max s!s0:0;z0 k s0 þ k 1 0;z0 ;k s1 þ k 1 1;z1 4) New extrinsic information and LLR calculation: k e;new ¼ max s17!s:1;y k s1 þ rk 1;y þ kþ1 s max s07!s:0;y k s0 þ rk 0;y þ kþ1 s k o ¼ k i þ k e;old þ k e;new For more information about turbo decoders, readers are referred to [4] and [5]. 3 Compression of state metrics In this paper, our focus is the compression of SMs for memory reduction. Since k is stored into LIFO (Last-In-First-Out) as in Fig. 1 (b), in later chapters k is used instead of SMs, which consists of Ns k s s(0sns 1). Fig. 2 (a) shows the basic idea of modulo-normalization for 10-bit k case. In this figure, the thick arc on the circle is the region of k, and the positive direction is anti-clockwise. Since the effective information of k is the differences between k ss other than their absolute value, the arc in Fig. 2 (a) can be anywhere as long as the differences are kept. Generally speaking, the wider the region of k is, the more confidence the decoder has about the trellis. When the region of k is wide enough, even some noise is introduced to k ss, the decoder can still decode with negligible BER loss as the major information of k is kept; on the contrary, the decoder will need finer description about the differences of k and is more sensitive to noise. Based Fig. 2. (a) Modulo-normalization before rotation (b) Modulo-normalization after rotation 3

4 on the above observations, our idea is to quantize k non-uniformly according to how wide the region of k is. In the proposed scheme, TBW (target bit width) is defined as the bit width of the compressed SMs. The proposed compression technique is described as follows: Step 1: Get ~ k by rotating the arc of k to the nearby of 0 as shown in Fig. 2 (b). Since the arc of k can be anywhere on the circle as in Fig. 2 (a), it will not be easy to evaluate the width of the k region directly. By this rotation, we can constrain the scope from the whole circle to an arc that crosses 0. This rotation can be implemented in a lot of ways; in our scheme we implement this rotation by subtracting k 0 from k s. Step 2: Evaluate the width of ~ k region. We define BW as the minimum number of bits that are required to represent ~ k ss. It s obvious that 2 BW 1 ~ k s 2BW 1 1. So we get the upper bound of ~ k region. For simplicity, we use BW as notation for the width of ~ k region. Step 3: Quantize ~ k s to TBW width. The quantization process is implemented as follows: 8 < ~ k s k ¼ s BW TBW ~ k : (1) : s BW > TBW 2BW TBW Step 4: Restore the SMs. This is the inverse operation of quantization, the process is as follows: ( ^ k s ¼ s k BW TBW s k : (2) 2BW TBW BW > TBW From (1) and (2), we can see that when BW TBW, there will be no Fig. 3. Hardware architecture of the compressing logic 4

5 quantization noise; when BW > TBW, the quantization noise will be less than 2 BW TBW. The framework of the compression logic is shown in Fig. 3. MBW (metric bit width) is the bit-width of k s s. For step 1, we subtract k s sbyk 0 ; for step 2, we get BW by finding the position of the first most significant neighboring bits that are different all over ~ k ss; for step 3, we implement division in (1) by logic-shifting-right (LSHR) bbw TBWc bits ( bxc is x when x0 and 0 when x<0) and dropping most-significant-bits; for step 4, we implement multiplication in (2) by first extending the most significant bits and then logic-shifting-left (LSHL) bbw TBWc bits. 4 Simulation results We simulated the BER performance for three turbo codes with the proposed compression technique (since TBW is the coefficient for this proposed method, we call this technique TM for abbreviation in later chapters) and WM method in [3]. Fig. 4 plots the BER curve for turbo code in 3GPP-LTE with information length of Fig. 5 shows the WIMAX case with 1920 information bits. And Fig. 6 is for a turbo code (7, 5, 1024) with four states, where 7 and 5 stands for the code generator of the encoder, and 1024 is the length of information bits. For all these cases, we used BPSK modulation with AGWN channel. The maximum iteration number is 8. For 3GPP-LTE the bit width is 5 for input LLRs, 7 for extrinsic information, and 10 for un-compressed SMs. For the other two cases, we use 6 bits for input LLRS, 8 bits for extrinsic information, and 10 bits for uncompressed SMs. Fig. 4. BER performance for 3GPP-LTE of length 1024 From Fig. 4 we can see that both TM with TBW=4 and WM have a similar BER performance with an error floor of about while the uncompressed scheme has a floor about TM with TBW=5 has a better performance than TBW=4 and TM with TBW=3 has a higher floor. In Fig. 5 and Fig. 6, we can also find that TM with TBW=4 and WM 5

6 Fig. 5. BER performance for WIMAX of length 1920 Fig. 6. BER performance for turbo code (7,5,1024) have nearly the same BER performance for both WIMAX and the 4-state turbo code. 5 Complexity For the estimation of the hardware cost, we synthesized the circuit in Fig. 3 using SMIC 0.13 um process. Results for TBW=3, 4 and 5 are given in Table I and II. Since the TM with TBW=4 and WM method have a similar BER performance for all the three turbo codes, we can use these two methods for a fair comparison. Compared with WM method, the proposed method saves 6

7 Table I. Comparison of UC, WM and the proposed method for 3GPP-LTE and WIMAX Table II. Comparison of UC, WM and the proposed method for the four-state turbo code (7,5,1024) 22.5% memory bits and 74.8% logic gates for 3GPP-LTE and WIMAX. For the four-state turbo code, 25% memory bits and 69.9% logic gates are saved. Moreover, the proposed method provides more flexibility than WM method when considering tradeoff between complexity and BER performance: for lower hardware complexity, we can choose fewer TBW bits; for better BER performance, more TBW bits are required. 6 Conclusion We propose a SM compression method for modulo-normalization in turbo decoder which compresses the SMs according to the region of SMs. Compared with the existing method, the proposed method can save up to 22.5% memory bits and 75% logic gates with same BER performance loss for LTE and WIMAX turbo codes. For a four state turbo, the proposed method saves 25% memory bits and 69.9% logic gates. Acknowledgments This paper is supported by the National Science and Technology Major Project of China (No. 2011ZX ) and state key lab of ASIC & System, grant No. 11MS003 and 12GF002. 7