Analog & Digital Electronics Laboratory. Code - CS391. Lab Manual

Transcription

1 Analog & Digital Electronics Laboratory Code - CS391 Lab Manual

2 EXPERIMENT: 1 LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various ICs and their specification. COMPONENTS REQUIRED: Logic gates (IC) trainer kit. Connecting patch chords. IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486 THEORY: The basic logic gates are the building blocks of more complex logic circuits. These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR. Fig. below shows the circuit symbol, Boolean function, and truth. It is seen from the Fig that each gate has one or two binary inputs, A and B, and one binary output, C. The small circle on the output of the circuit symbols designates the logic complement. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. A gate can be extended to have multiple inputs if the binary operation it represents is commutative and associative. These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC gates are classified not only by their logic operation, but also the specific logic-circuit family to which they belong. Each logic family has its own basic electronic circuit upon which more complex digital circuits and functions are developed. The following logic families are the most frequently used. TTL Transistor-transistor logic ECL Emitter-coupled logic MOS Metal-oxide semiconductor CMOS Complementary metal-oxide semiconductor TTL and ECL are based upon bipolar transistors. TTL has a well established popularity among logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS, are based on field effect transistors. They are widely used in large scale integrated circuits because of their high component density and relatively low power consumption. CMOS logic consumes far less power than MOS logic. There are various commercial

3 Logic Design Laboratory Manual 2 integrated circuit chips available. TTL ICs are usually distinguished by numerical designation as the 5400 and 7400 series. PROCEDURE: 1. Check the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Provide the input data via the input switches and observe the output on output LEDs

4 Logic Design Laboratory Manual 3 VIVA QUESTIONS: 1. Why NAND & NOR gates are called universal gates? 2. Realize the EX OR gates using minimum number of NAND gates. 3. Give the truth table for EX-NOR and realize using NAND gates? 4. What are the logic low and High levels of TTL IC s and CMOS IC s? 5. Compare TTL logic family with CMOS family? 6. Which logic family is fastest and which has low power dissipation? EXPERIMENT: 2 REALIZATION OF A BOOLEAN FUNCTION. AIM: To simplify the given expression and to realize it using Basic gates and Universal gates LEARNING OBJECTIVE: To simplify the Boolean expression and to build the logic circuit. Given a Truth table to derive the Boolean expressions and build the logic circuit to realize it. COMPONENTS REQUIRED: IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, Patch Cords & IC Trainer Kit. THEORY: Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive normal form (sum of min-terms) or conjunctive normal form (product of max-terms). A Boolean function can be represented by a Karnaugh map in which each cell corresponds to a minterm. The cells are arranged in such a way that any two immediately adjacent cells correspond to two minterms of distance 1. There is more than one way to construct a map with this property. Karnaugh Maps For a function of two variables, say, f(x, y), For a function of three variables, say, f(x, y, z) For a function of four variables: f(w, x, y, z)

5 Logic Design Laboratory Manual 4 Realization of Boolean expression: 1) Y= A B C D A BC D ABC D A B C D A B C D A B C D A B CD AB After simplifying using K-Map method we _ Y =A B + C D _ get Realization using Basic gates Realization using NAND gates TRUTH TABLE INPUTS OUTPUT A B C D Y Realization using NOR gates

6 Logic Design Laboratory Manual 5 2) For the given Truth Table, realize a logical circuit using basic gates and NAND gates Inputs Output A B C D Y PROCEDURE: Check the components for their working. Insert the appropriate IC into the IC base. Make connections as shown in the circuit diagram. Provide the input data via the input switches and observe the output on output LEDs Verify the Truth Table RESULT: Simplified and verified the Boolean function using basic gates and universal gates VIVA QUESTIONS: 1) What are the different methods to obtain minimal expression? 2) What is a Min term and Max term 3) State the difference between SOP and POS.

7 Logic Design Laboratory Manual 6 4) What is meant by canonical representation? 5) What is K-map? Why is it used? 6) What are universal gates?

8 Experiment 3: Realization of logic functions with the help of universal gates-nand Gate. Apparatus: logic trainer kit, NAND gates (IC 7400), wires. Theory: NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate. So its output is complement of the output of an AND gate. This gate can have minimum two inputs, output is always one. By using only NAND gates, we can realize all logic functions: AND, OR, NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate. NAND gates as NOT gate A NOT produces complement of the input. It can have only one input, tie the inputs of a NAND gate together. Now it will work as a NOT gate. Its output is Y = (A.A) => Y = (A) NAND gates as AND gate A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted, overall output will be that of an AND gate. Y = ((A.B) ) => Y = (A.B) NAND gates as OR gate From DeMorgan s theorems: (A.B) = A + B => (A.B ) = A + B = A + B So, give the inverted inputs to a NAND gate, obtain OR operation at output.

9 NAND gates as X-OR gate The output of a the input X-OR gate is shown by: Y = A B + AB. This can be achieved with the logic diagram shown in the left side. Gate No. Inputs Output 1 A, B (AB) 2 A, (AB) (A (AB) ) 3 (AB), B (B (AB) ) 4 (A (AB) ), (B (AB) ) A B + AB Now the ouput from gate no. 4 is the overall output of the configuration. Y = ((A (AB) ) (B (AB) ) ) = (A(AB) ) + (B(AB) ) = (A(AB) ) + (B(AB) ) = (A(A + B) ) + (B(A + B )) = (AA + AB ) + (BA + BB ) = ( 0 + AB + BA + 0 ) = AB + BA => Y = AB + A B

10 NAND gates as X-NOR gate X-NOR gate is actually X-OR gate followed by NOT gate. So give the output of X-OR gate to a NOT gate, overall output is that of an X-NOR gate. Y = AB+ A B NAND gates as NOR gate A NOR gate is an OR gate followed by NOT gate. So connect the output of OR gate to a NOT gate, overall output is that of a NOR gate. Y = (A + B) Procedure: 1. Connect the trainer kit to ac power supply. 2. Connect the NAND gates for any of the logic functions to be realised. 3. Connect the inputs of first stage to logic sources and output of the last gate to logic indicator. 4. Apply various input combinations and observe output for each one. 5. Verify the truth table for each input/ output combination. 6. Repeat the process for all logic functions. 7. Switch off the ac power supply.

11 Experiment 4. Aim: Design and verify the logic circuit of Half adder using logic gates. Design and verify the logic circuit Full adder using of Half adder. Objective: a. To understand the principle of binary addition. b. To understand and to differentiate half & full adder concept. c. Use truth table, Karnaugh map, and Boolean Algebra theorems in simplifying a circuit design. d. To implement half adder and full adder circuit uing logic gates Apparatus Required: Prototyping board (breadboard) DC Power Supply 5V Batery Light Emitting Diode (LED) Digital ICs: 7408 :Quad 2 input AND 7486: Quad 2 input EXOR 7432 :Quad 2 input OR Connecting Wires Pin Diagram: Half Adder: Pin Diagram Of Half Adder

12 Full adder: Pin diagram of Full adder Theory: Half Adder: A half adder is a logical circuit that performs an addition operation on two binary digits. The half adder produces a sum and a carry value which are both binary digits. A B S C Fig 2.3:Circuit Diagram Of Half Adder Truth Table Boolean Expression: S= A B C=AB

13 Full Adder:Full adder is a logical circuit that performs an addition operation on three binary digits. The full adder produces a sum and carries value, which are both binary digits. It can be combined with other full adders or work on its own. Input A B Output Ci S Co Table Fig 2.4:Circuit Diagram Of Full Adder Truth Boolean Expression: S= A B Ci Co=AB+ +Ci(A B) Procedure: 1. Collect the components necessary to accomplish this experiment. 2. Plug the IC chip into the breadboard. 3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground and PIN14 = +5V. 4. According to the pin diagram of each IC mentioned above, make the connections according to circuit dsagram. 5. Connect the inputs of the gate to the input switches of the LED. 6. Connect the output of the gate to the output LEDs. 7. Once all connections have been done, turn on the power switch of the breadboard 8.. Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if LED is OFF Apply the various combination of inputs according to the truth table and observe the condition of Output LEDs.

14 Experiment 5. Aim: Design and verify the logic circuit of Half subtractor using logic gates. Design and verify the logic circuit Full subtractor using of Half subtractor. Objective: a. To understand the principle of binary subtraction. b. To understand and to differentiate half & full subtractor concept. c. Use truth table, Karnaugh map, and Boolean algebra theorems in simplifying a circuit design. d. To implement half subtractor and full subtractor circuit uing logic gates Apparatus Required: Prototyping board (breadboard) DC Power Supply 5V Batery Light Emitting Diode (LED) Digital ICs: 7408 :Quad 2 input AND 7486: Quad 2 input EXOR 7432 :Quad 2 input OR 7404: Hex invertor(not Gate) Connecting Wires Pin Diagram: Half Subtractor: Pin Diagram of Half Subtractor

15 Full Subtractor: Pin Diagram of Full Subtractor Theory : Half Subtractor: The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). Fig 3.3: Circuit Diagram of Half Subtractor

16 Full subtractor: A full Subtractor is combinational circuit that performs a subtraction between three bits, taking into account that a 1 may have been borrowed by a lower significant stage. The 3 inputs denote minuend, subtrahend and previous borrow, respectively. The 2 outputs are difference(d) and borrow(b). Procedure: Circuit Diagram of Full Subtractor 1. Collect the components necessary to accomplish this experiment. 2. Plug the IC chip into the breadboard. 3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground and PIN14 = +5V. 4. According to the pin diagram of each IC mentioned above, make the connections according to circuit diagram. 5. Connect the inputs of the gate to the input switches of the LED. 6. Connect the output of the gate to the output LEDs. 7. Once all connections have been done, turn on the power switch of the breadboard 8.. Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if LED is OFF Apply the various combination of inputs according to the truth table and observe the condition of Output LEDs.

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21 EXPERIMENT: 7 MULTIPLEXER AND DEMULTIPLEXER AIM: To design and set up the following circuit 1) To design and set up a 4:1 Multiplexer (MUX) using only NAND gates. 2) To design and set up a 1:4 Demultiplexer(DE-MUX) using only NAND gates. 3) To verify the various functions of IC 74153(MUX) and IC 74139(DEMUX). 4) To set up a Half/Full Adder and Half/Full Subtractor using IC LEARNING OBJECTIVE: To learn about various applications of multiplexer and de-multiplexer To learn and understand the working of IC and IC To learn to realize any function using Multiplexer THEORY: Multiplexers are very useful components in digital systems. They transfer a large number of information units over a smaller number of channels, (usually one channel) under the control of selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one output. By using control signals (select lines) we can select any input to the output. Multiplexer is also called as data selector because the output bit depends on the input data bit that is selected. The general multiplexer circuit has 2 n input signals, n control/select signals and 1 output signal. De-multiplexers perform the opposite function of multiplexers. They transfer a small number of information units (usually one unit) over a larger number of channels under the control of selection signals. The general de-multiplexer circuit has 1 input signal, n control/select signals and 2 n output signals. De-multiplexer circuit can also be realized using a decoder circuit with enable. COMPONENTS REQUIRED: IC 7400, IC 7410, IC 7420, IC 7404, IC 74153, IC 74139, Patch Cords & IC Trainer Kit. i) 4:1 MULTIPLEXER Inputs 4:1 MUX Y E Select inputs Output Y= E S1 S0 I0 + E S1 S0I1 + E S1S0 I2 + E S1S0I3

22 Logic Design Laboratory Manual 22 REALIZATION USING NAND GATES TRUTH TABLE Select Enable Out Inputs Inputs Input puts S 1 S 0 E I 0 I 1 I 2 I 3 Y X X 1 X X X X X X X X X X X 0 X X X 1 X X X X 0 X X X 1 X X X X X X X 1 1 VERIFY IC MUX (DUAL 4:1 MULTIPLEXER)

23 Logic Design Laboratory Manual 23 ii) DE-MUX USING NAND GATES Enable Data Select Inputs Input Inputs Outputs E D S1 S0 Y3 Y2 Y1 Y0 1 0 X X X X X X VERIFICATION OF IC (DEMUX) TRUTH TABLE Inputs Outputs Ea S 1 S 0 Y 3 Y 2 Y 1 Y 0 1 X X

24 SUM CARRY Logic Design Laboratory Manual 24 HALF ADDER USING MUX: DESIGN: SUM CARRY I0 I1 I0 I A A 0 A CIRCUIT: TRUTH TABLE Inputs Outputs A B S C FULL ADDER USING MUX: DESIGN: I0 I1 I3 I A A A A I0 I1 I3 I A A 1 TRUTH TABLE Inputs Outputs A B C S C

25 Logic Design Laboratory Manual 25 FULL ADDER CIRCUIT HALF SUBTRACTOR USING MUX: DESIGN: DIFFERENCE BORROW I0 I1 I0 I A A 0 A CIRCUIT: TRUTH TABLE Inputs Outputs A B D Br

26 Logic Design Laboratory Manual 26 FULL SUBTRACTOR USING MUX: DESIGN: DIFFERENCE I0 I1 I2 I3 BORROW I0 I1 I2 I A A A A 0 A A 1 TRUTH TABLE Inputs Outputs A B C D Br PROCEDURE: Check all the components for their working. Insert the appropriate IC into the IC base. Make connections as shown in the circuit diagram. Verify the Truth Table and observe the outputs. RESULT: Adder and subtractor circuits are realized using multiplexer IC VIVA QUESTIONS: 1) What is a multiplexer? 2) What is a de-multiplexer? 3) What are the applications of multiplexer and de-multiplexer? 4) Derive the Boolean expression for multiplexer and de-multiplexer. 5) How do you realize a given function using multiplexer 6) What is the difference between multiplexer & demultiplexer?

27 7) In 2n to 1 multiplexer how many selection lines are there? 8) How to get higher order multiplexers? 9) Implement an 8:1 mux using 4:1 muxes?

28 EXPERIMENT: 9 DECODERS AIM: To realize a decoder circuit using basic gates and to verify IC 74LS139 LEARNING OBJECTIVE: To learn about working principle of decoder To learn and understand the working of IC 74LS139 To realize using basic gates as well as universal gates COMPONENTS REQUIRED: IC74LS139, IC 7400, IC 7408, IC 7432, IC 7404, IC 7410, Patch chords, & IC Trainer Kit THEORY: A decoder is a combinational circuit that connects the binary information from n input lines to a maximum of 2 n unique output lines. Decoder is also called a min-term generator/max-term generator. A min-term generator is constructed using AND and NOT gates. The appropriate output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND gates. The appropriate output is indicated by logic 0 (Negative logic). The IC accepts two binary inputs and when enable provides 4 individual active low outputs. The device has 2 enable inputs (Two active low). CIRCUIT DIAGRAM: 2:4 DECODER (MIN TERM GENERATOR): TRUTH TABLE: INPUT OUTPUT A B Y0 Y1 Y2 Y BOOLAEN EXPRESSIONS: Y 0 AB Y1 AB Y 2 AB Y 3 AB

29 Logic Design Laboratory Manual 31 CIRCUIT DIAGRAM: 2:4 DECODER (MAX TERM GENERATOR): TRUTH TABLE: INPUT OUTPUT A B Y0 Y1 Y2 Y CIRCUIT DIAGRAM:

30 PROCEDURE: 1. Make the connections as per the circuit diagram. 2. Change the values of G1, G2A, G2B, A, B, and C, using switches. 3. Observe status of Y0, to Y7 on LED s. 4. Verify the truth table. RESULT: Verified the Operation of 3 to 8 Decoder VIVA QUESTIONS: 1. What are the applications of decoder? 2. What is the difference between decoder & encoder? 3. For n- 2 n decoder how many i/p lines & how many o/p lines? 4. What are the different codes & their applications? 5. What are code converters? 6. Using 3:8 decoder and associated logic, implement a full adder? 7. Implement a full subtractor using IC 74138? 8. What is the difference between decoder and de-mux?

31 EXPERIMENT: 10 BCD TO 7-SEGMENT DECODER/DRIVER AIM: To set up and test a 7-segment static display system to display numbers 0 to 9. LEARNING OBJECTIVE: To learn about various applications of decoder To learn and understand the working of IC 7447 To learn about types of seven-segment display COMPONENTS REQUIRED: IC7447, 7-Segment display (common anode), Patch chords, resistor (1K ) & IC Trainer Kit THEORY: The Light Emitting Diode (LED) finds its place in many applications in these modern electronic fields. One of them is the Seven Segment Display. Seven-segment displays contains the arrangement of the LEDs in Eight (8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode). The purpose of arranging it in that passion is that we can make any number out of that by switching ON and OFF the particular LED's. Here is the block diagram of the Seven Segment LED arrangement. The Light Emitting Diode (LED), finds its place in many applications in this modern electronic fields. One of them is the Seven Segment Display. Seven-segment displays contains the arrangement of the LEDs in Eight (8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode). The purpose of arranging it in that passion is that we can make any number out of that by switching ON and OFF the particular LED's. Here is the block diagram of the Seven Segment LED arrangement. LED s are basically of two types- Common Cathode (CC) -All the 8 anode legs uses only one cathode, which is common. Common Anode (CA)-The common leg for all the cathode is of Anode type. A decoder is a combinational circuit that connects the binary information from n input lines to a maximum of 2 n unique output lines. The IC7447 is a BCD to 7-segment pattern converter. The IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7 segment code.

32 Logic Design Laboratory Manual 35 CIRCUIT DIAGRAM: TRUTH TABLE: Decimal BCD Inputs Output Logic Levels from IC 7447 to 7-segments number display D C B A a b c d e f g PROCEDURE: Check all the components for their working. Insert the appropriate IC into the IC base. Make connections as shown in the circuit diagram. Verify the Truth Table and observe the outputs. VIVA QUESTIONS: 1. What are the different types of LEDs? 2. Draw the internal circuit diagram of an LED. 3. What are the applications of LEDs?

33 Logic Design Laboratory Manual 36 EXPERIMENT: 11 ENCODERS AIM: 1. To set up a circuit of Decimal-to-BCD Encoder using IC To design and set up a circuit of Hexadecimal-to-Binary Encoder using IC Encoders and IC Multiplexer LEARNING OBJECTIVE: To learn about various applications of Encoders To learn and understand the working of IC 74147, IC & IC To learn to do code conversion using encoders COMPONENTS REQUIRED: IC 74147, IC 74148, IC 74157, Patch chords & IC Trainer Kit THEORY: An encoder performs a function that is the opposite of decoder. It receives one or more signals in an encoded format and output a code that can be processed by another logic circuit. One of the advantages of encoding data, or more often data addresses in computers, is that it reduces the number of required bits to represent data or addresses. For example, if a memory has 16 different locations, in order to access these 16 different locations, 16 lines (bits) are required if the addressing signals are in 1 out of n format. However, if we code the 16 different addresses into a binary format, then only 4 lines (bits) are required. Such a reduction improves the speed of information processing in digital systems. CIRCUIT DIAGRAM: 1) DECIMAL-TO BCD ENCODER USING IC TRUTH TABLE INPUTS OUTPUTS I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A1 A X X X X X X X X X X X X X X X X X X X X X X X X X X X X

34 Logic Design Laboratory Manual 37 2) OCTAL TO BINARY ENCODER USING IC TRUTH TABLE E 1 I 0 I 1 I 2 Inputs I 3 I 4 I 5 I 6 I 7 A 2 A 1 Outputs A 0 G S 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X E 0 3) HEXADECIMAL TO BINARY ENCODER

35 Logic Design Laboratory Manual 38 TRUTH TABLE INPUTS OUTPUTS I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 Y3 Y2 Y1 Y PROCEDURE: Check all the components for their working. Insert the appropriate IC into the IC base. Make connections as shown in the circuit diagram. Verify the Truth Table and observe the outputs. VIVA QUESTIONS: 1. What is a priority encoder? 2. What is the role of an encoder in communication? 3. What is the advantage of using an encoder? 4. What are the uses of validating outputs?

36 M74HC138 3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: t PD = 13ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: I OH = I OL = 4mA (MIN) BALANCED PROPAGATION DELAYS: t PLH t PHL WIDE OPERATING VOLTAGE RANGE: V CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 DESCRIPTION The M74HC138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C 2 MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is DIP ORDER CODES SOP TSSOP PACKAGE TUBE T & R DIP M74HC138B1R SOP M74HC138M1R M74HC138RM13TR TSSOP M74HC138TTR inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July /10

37 M74HC138 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 2, 3 A, B, C Address Inputs 4, 5 G2A, G2B Enable Inputs 6 G1 Enable Input 9, 10, 11, 12, Y0 to Y7 Data Outputs 13, 14, 15, 7 8 GND Ground (0V) 16 V CC Positive Supply Voltage TRUTH TABLE ENABLE INPUTS SELECT OUTPUTS G2B G2A G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L X X X H H H H H H H H X H X X X X H H H H H H H H H X X X X X H H H H H H H H L L H L L L L H H H H H H H L L H L L H H L H H H H H H L L H L H L H H L H H H H H L L H L H H H H H L H H H H L L H H L L H H H H L H H H L L H H L H H H H H H L H H L L H H H L H H H H H H L H L L H H H H H H H H H H H L X : Don t Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10

38 M74HC138 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V CC Supply Voltage -0.5 to +7 V V I DC Input Voltage -0.5 to V CC V V O DC Output Voltage -0.5 to V CC V I IK DC Input Diode Current ± 20 ma I OK DC Output Diode Current ± 20 ma I O DC Output Current ± 25 ma I CC or I GND DC V CC or Ground Current ± 50 ma P D Power Dissipation 500(*) mw T stg Storage Temperature -65 to +150 C T L Lead Temperature (10 sec) 300 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 C; derate to 300mW by 10mW/ C from 65 C to 85 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit V CC Supply Voltage 2 to 6 V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature -55 to 125 C t r, t f V CC = 4.5V 0 to 500 ns Input Rise and Fall Time V CC = 2.0V 0 to 1000 ns V CC = 6.0V 0 to 400 ns 3/10

39 M74HC138 DC SPECIFICATIONS Test Condition Value Symbol Parameter V CC (V) T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max. Unit V IH V IL V OH V OL I I I CC High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current I O =-20 µa I O =-20 µa I O =-20 µa I O =-4.0 ma I O =-5.2 ma I O =20 µa I O =20 µa I O =20 µa I O =4.0 ma I O =5.2 ma V I = V CC or GND ± 0.1 ± 1 ± 1 µa 6.0 V I = V CC or GND µa V V V V AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = 6ns) Test Condition Value Symbol Parameter V CC (V) T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max. Unit t TLH t THL Output Transition Time ns t PLH t PHL Propagation Delay Time (A, B, C - Y) ns t PLH t PHL Propagation Delay Time (G, G - Y) ns 4/10

40 M74HC138 CAPACITIVE CHARACTERISTICS Test Condition Value Symbol Parameter V CC (V) T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max. Unit C IN Input Capacitance pf C PD Power Dissipation Capacitance (note 1) pf 1) C PD is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC TEST CIRCUIT C L = 50pF or equivalent (includes jig and probe capacitance) R T = Z OUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1mhz; 50% duty cycle) 5/10

41 M74HC138 WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f= 1MHz; 50 % duty cycle) 6/10

42 M74HC138 Plastic DIP-16 (0.25) MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. a B b b D E e e F I L Z P001C 7/10

43 M74HC138 SO-16 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A a a b b C c1 45 (typ.) D E e e F G L M S 8 (max.) PO13H 8/10

44 M74HC138 TSSOP16 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A A A b c D E E e 0.65 BSC BSC K L A A2 A1 b e c K L E D E1 PIN 1 IDENTIFICATION D 9/10

45 M74HC138 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 10/ STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom

46 Encoders

47 Encoder An encoder is a combinational logic circuit that essentially performs a reverse of decoder functions. An encoder accepts an active level on one of its inputs, representing digit, such as a decimal or octal digits, and converts it to a coded output such as BCD or binary. Encoders can also be devised to encode various symbols and alphabetic characters. The process of converting from familiar symbols or numbers to a coded format is called encoding. 2

48 Most decoders accept an input code and produce a HIGH ( or a LOW) at one and only one output line. In otherworlds, a decoder identifies, recognizes, or detects a particular code. The opposite of this decoding process is called encoding and is performed by a logic circuit called an encoder. An encoder has a number of input lines, only one of which input is activated at a given time and produces an N-bit output code,depending on which input is activated. 3

49 4 General encoder diagram

50 Logic circuit for octal-to binary encoder [8-line- 3-line ] 5

51 Truth table for octal-to binary encoder [8-line- 3-line ] A low at any single input will produce the output binary code corresponding to that input. For instance, a low at A 3 will produce O 2 =0, O 1 =1 and O 0 =1, which is binary code for 3. A o is not connected to the logic gates because the encoder outputs always be normally at 0000 when none of the inputs is LOW 6

52 Design of 4-input Priority Encoder ( 4-line-to 2 line priority encoder) (1)... A priority encoder is an encoder that includes the priority function If two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. Truth Table of a 4-input Priority Encoder: Inputs Outputs D 0 D 1 D 2 D 3 x y V X X X X X X X X

53 Design of 4-input Priority Encoder ( 4-line-to 2 line priority encoder) (2)... In addition to two outputs x, and y, the truth table has a third output designated by V, which is a valid bit indicator that is set 1 when one or more inputs are equal to 1. If all inputs are 0, there is no valid input and V is equal to 0. X s in the output column indicate don t care conditions, the X s in the input columns are useful for representing a truth table in condensed form. The higher the subscript number, the higher the priority of the input. Input D3 has the highest priority, so regardless of the values of the other inputs, when this input is 1, the output for xy is 11 (binary 3) 8

54 Design of 4-input Priority Encoder ( 4-line-to 2 line priority encoder) (3)... 9 V=D 0 +D 1 +D 2 +D 3 K-Maps for 4-input Priority Encoder

55 Design of 4-input Priority Encoder ( 4-line-to 2 line priority encoder) (4) Logic Diagram for 4-input priority encoder 10

56 Decimal-BCD priority encoder Encoder will produce a BCD output corresponding to the highest-order decimal digit input that is active and will ignore any other lower order active inputs. For instance if the input 6 and the 3 are active, the output will be 1001, which is the inverse value of BCD output 0110 (which represents decimal 6) 11

57 74147 decimal-bcd priority encoder 12 When A9 is low, the output is 0110, which is inverse of 1001 ( eq to 9 in BCD)

58 Decimal- BCD switch decoder 13 The output of the decoder are inversed to produce the normal BCD value

59 The Octal to Binary Priority Encoder- Example The 74LS148 is a priority encoder that has eight active LOW inputs and three active LOW binary outputs To enable the device, the EI (enable input) must be LOW. It also has the EO (enable output) and GS (group signal output) for expansion purposes. 14

60 15 The Octal to Binary Encoder

61 The Octal to Binary Encoder Active LOW enable input, a HIGH on the input forces all outputs to their inactive state (HIGH). Active LOW enable output, the output pin goes LOW when all inputs are inactive (HIGH) and is LOW. Active LOW group signal output, this output pin goes LOW whenever any of the inputs are active (LOW) and is LOW. 16

62 The 16 to 4 Encoder The 74LS148 can be expanded to a 16 line to 4 line encoder by connecting the EO of the higher order encoder to the EI of the lower order encoder and negative ORing the corresponding binary outputs as shown 17

63 18 The 16 to 4 Encoder

64 Application example A simplified keyboard encoder. 19

65 When one of the keys is pressed, the decimal digit is encoded to the corresponding BCD code The keys are represented by 10 push-button switches, each with a pull-up resistor to V+. The pull-up resistor ensures that the line is HIGH when a key is not depressed. When a key is depressed, the line is connected to ground, and a LOW is applied to the corresponding encoder input. The zero key is not connected because the BCD output represents zero when none of the other keys is depressed The BCD complement output of the encoder goes into a storage device, and each successive BCD code is stored until the entire number has been entered 20

66 Assignment - 19 Design a single encoder for following functions. F1 = Σm(1, 3, 7, 15) f2 = Σm(4,6,8,10)

67 Aim: To realize J-K and D-FF using 74LS73 and 74LS74 Hardware Requirement a. Equipments - Digital IC Trainer Kit b. Discrete Components - 74LS73 JK-Flip flop 74LS74 D Flip flop Theory Digital electronic circuit is classified into combinational logic and sequential logic. Combinational logic output depends on the inputs levels, whereas sequential logic output Depends on stored levels and also the input levels. The storage elements (Flip -flops) are devices capable of storing 1-bit binary info. The binary info stored in the memory elements at any given time defines the state of the Sequential circuit. The input and the present state of the memory element determine the output. Storage elements next state is also a function of external inputs and present state. Flip-Flops and their properties Flip-flops are synchronous bistable devices. The term synchronous means the output changes state only when the clock input is triggered. That is, changes in the output occur in synchronization with the clock. A flip-flop circuit has two outputs, one for the normal value and one for the complement value of the stored bit. Since memory elements in sequential circuits are usually flip-flops, it is worth summarizing the behavior of various flip-flop types before proceeding further. All flip -flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response invoked by different value of input signals.

68 CONNECTION DIAGRAM FUNCTION TABLE INPUTS OUTPUTS PR CLR CLK D Q Q L H X X H L H L X X L H L L X X H H H H H L H H H L L H H H L X Q 0 Q0 D Flip-flop connection diagram H HIGH Logic Level X Either LOW or HIGH Logic Level L LOW Logic Level Positive-going transition of the clock. Q0 The output logic level of Q before the indicated input conditions were established. IC7473-JK- Flip flop Connection Diagram with Function Table

69

70 Aim:- To study shift register using IC 7495 in all its modes i.e. SIPO/SISO, PISO/PIPO. Apparatus: - IC 7495, etc. Circuit diagram :

71 PISO: Procedure : Serial In Parallel Out(SIPO):

72 1. Connections are made as per circuit diagram. 2. Apply the data at serial i/p 3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA. 4. Apply the next data at serial i/p. 5. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the new data applied will appear at QA. 6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift register. Serial In Serial Out (SISO): 1. Connections are made as per circuit diagram. 2. Load the shift register with 4 bits of data one by one serially. 3. At the end of 4th clock pulse the first data d0 appears at QD. 4. Apply another clock pulse; the second data d1 appears at QD. 5. Apply another clock pulse; the third data appears at QD. 6. Application of next clock pulse will enable the 4th data d3 to appear at QD. Thus the data applied serially at the input comes out serially at QD Parallel In Serial Out (PISO): 1. Connections are made as per circuit diagram. 2. Apply the desired 4 bit data at A, B, C and D. 3. Keeping the mode control M=1 apply one clock pulse. The data applied at A, B, C and D will appear at QA, QB, QC and QD respectively. 4. Now mode control M=0. Apply clock pulses one by one and observe the

73 Data coming out serially at QD Parallel In Parallel Out (PIPO): 1. Connections are made as per circuit diagram. 2. Apply the 4 bit data at A, B, C and D. 3. Apply one clock pulse at Clock 2 (Note: Mode control M=1). 4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively. Precautions: All the connections should be made properly. Result: shift registers using IC 7495 in all its modes i.e.sipo/siso, PISO/PIPO are verified.

74 Aim:- To design and construct of 3-bit Asynchronous up and down counters,2-bit up/down counter. Apparatus: Circuit Diagram: 1. IC s ,7476,7400, Electronic circuit designer 3. Connecting patch chords 3-bit Asynchronous up counter: TRUTH TABLE 1

75 3-bit Asynchronous down counter: TRUTH TABLE 2

76 Two Bit up/down Counter using negative edge-triggered flip-flops WHEN M=1 WHEN M=0 CLK Q2 Q CLK Q2 Q

77 Procedure: 1. Connections are made as per the circuit diagram 2. Switch on the power supply. 3. Apply clock pulses and note the outputs after each clock pulse and note done the out puts. Precautions: 1. All the connections should be made properly. 2. IC should not be reversed. Result: 3-bit Asynchronous up and down counters,2-bit up/down counter are designed and truth tables are verified.