Reliability of probabilistic circuits

Transcription

1 Reliability of probabilistic circuits Kaikai Liu To cite this version: Kaikai Liu. Reliability of probabilistic circuits. Engineering Sciences [physics]. TELECOM ParisTech, English. <tel > HAL Id: tel Submitted on 1 Oct 2015 HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

2 2014-ENST-0065 EDITE - ED 130 Doctorat ParisTech T H È S E pour obtenir le grade de docteur délivré par TELECOM ParisTech Spécialité - Électronique et Communications présentée et soutenue publiquement par Kaikai LIU le 15 October 2014 Reliability of probabilistic circuits Directeur de thèse: Lirida NAVINER Co-encadrement de thèse: Jean-François NAVINER Jury Rapporteurs M. Walter STECHELE, Professeur de Technische Universität München M. Ivan SARAIVA SILVA, Professeur de Universidade Federal do Piauí Examinateurs M. Habib MEHREZ, Université Pierre et Marie CURIE, LIP6 M. Jean-Marc DAVEAU, Docteur de STMicroelectronics/Crolles2 Directeurs de Thèse Mrs. Lirida NAVINER, Professeur de Télécom ParisTech M. Jean-François NAVINER, Maître de conférences à Télécom ParisTech Télécom ParisTech école de l Institut Mines Télécom - membre de ParisTech 46, rue Barrault Paris Cedex 13 - Tél (0)

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4 Reliability of probabilistic circuits Kaikai LIU

5 Le Département Communications et Electronique (COMELEC) Institut Mines-Télécom, Télécom-ParisTech, LTCI-CNRS-UMR Rue Barrault, Paris CEDEX 13, 75634, France FRANCE This thesis is set in Computer Modern 11pt, with the L A TEX Documentation System Kaikai Liu 2014 July 2014

6 Remerciements All the people who helped me in the three-year thesis project should be acknowledged. Without their help and support, this thesis will never be accomplished. First and foremost, Professor Lirida NAVINER introduced me to the interesting world of reliability of probabilistic circuits. She helped me a lot from the literature review, the set-up of different models, the simulation realization and even the text of publications. I really appreciated her help, enthusiasms, patience and trust to my work. She taught me a lot not only in the academic field but also the attitude to work, which I will benefit for my whole life. I am very thankful to Professor Jean-François NAVINER and Professor Hervé PETIT who helped me a lot in my thesis. During the thesis project, they helped me with the simulation set-up and some of the details in the reliability field. Without their help, the thesis could be harder for me. And thanks to my dear colleagues who accompanied me all these years. Thank you Hao Cai, Ting An, Arwa Ben Dhia, Yi-meng Zhao, Yao Li, Yao Wu, Yunfei Wei, Wenlong Gupeng, Youlong Wu, Mengxing Li and Fengguo Zhang. Your kindnesses and support to me made these three-year of PhD more interesting. Specially, thank you Hao, Yi-meng and Wenlong, with your accompany of jogging in Parc Montsouris, I kept a healthy body. Finally, my biggest gratefulness belongs to my father and my mother, Huangong Liu and Jinhua Liu in Shandong, China. Also my sincere gratefulness and love to my dear wife, Wei Wang, in Sheffield, UK. Without their love and support, I will never finish my thesis.

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9 Abstract The Moore s Law has benefited us a lot since 1970s. As conceptualized by R. Dennard [1], one can obtain transistors with higher speed and lower energy consumption in reducing the critical dimensions and keeping the electrical field constant. This concept made the continuous trend of increase in integration density of CMOS(Complementary MetalOxide- Silicon) technology possible. Since 1970s, the number of components per chip has doubled every two years [2]. As mentioned in the ITRS (International Technology Roadmap for Semiconductors) 2007 [3], the operation frequency of a transistor will reach 12 GHz and the number of transistors contained in a single chip may be 12 billion in With the dimension shrinking to nanometer, or Deep Submicron Meter (DSM), many challenges have risen, one of which is the dramatically increasing probability of soft errors induced by Single Event Upsets(SEUs) or Single Event Transients(SETs). Normally, these kinds of soft errors often happened in the memory cells and rarely occurred in the logic circuits on the ground level. However, the increased operation frequency, the lower supply voltage and the reduced noise margin have made the transient current pulses induced by alpha particles or high-energy neutrons much easier to be captured by the filp-flops at the outputs of logic circuits. Consequently, the reliability of logic circuits (including the evaluation methodologies) in nanometer regime have been an important design criterion in ICs design [4]. Another challenge accompany with the CMOS dimension scaling to nanometer is that the thermal noise is not neglectable any more. As pointed in [2], the RMS of thermal noise will increase during miniaturization. The probability of the thermal noise crossing the voltage threshold also steadily increases with the reduction of the noise margin [2]. Thus the noise-immunity of logic circuits is also an important concern in ICs designs. Therefore, with CMOS technology scaling into DSM or nanometers, the behaviour of logic gates, the output of logic functions or even the services of systems are not deterministic but probabilistic. The reliability of probabilistic circuits, induced by the soft errors and noise, draws much more attention in modern IC designs. This thesis concentrates on the reliability evaluation methodology improvements and the general cost-effective noise-tolerant circuit designs. An efficient evaluation methodology based on Probability Transfer Matrix (PTM) is proposed to obtain the accurate reliability of a combinational circuit. Compared with the traditional PTM, the proposed PTM (denoted as ECPTM) can dramatically reduce the penalty in time consumption and memory usage. A general analytic tool has been developed to get the reliability of a circuit with its netlist file. The efficiency improvement of the proposed method is verified with practical bench circuits. This thesis also presents a general cost-effective noise-immune design structure of logic functions. This design structure is based on Markov Random Fields (MRF) and is suitable for all the basic logic gates as well as complex logic functions involving several logic gates. This structure has been verified through simulations done in SPICE using the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [5] and in Spectre based on ST 65nm CMOS models. Furthermore, this thesis proposes a model to analyze the reliability issues induced by both SETs and noise. Mathematical conditions are derived in order to improve the SETs robustness and noise-immunity at the same time.

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12 Contents Remerciements Abstract List of Tables List of Figures List of Acronyms i iv ix x xiii 1 Introduction Motivations Objectives Thesis Organization Reliability Evaluation Methodologies and Improvement Techniques Preliminaries on Reliability Basic Concepts Radiation-induced Soft Errors The Influence of Thermal Noise Reliability Evaluation Methodologies Simulation-based Methodologies Analytical Methodologies Hybrid Methods of Reliability Analysis Reliability Improvement Technologies Space Redundancy Time Redundancy Other Methodologies Conclusions Efficient Evaluation Methodology Based on PTM Probabilistic Transfer Matrix PTM Computation of Gates Connected in Series PTM Computation for Gates Connected in Parallel Efficient Computation of PTM (ECPTM) PTM Calculation of Complex Circuits Efficient Tensor Product Calculation The Efficiency of ECPTM A General Testbench Circuit The Efficiency Experimental Results

13 viii CONTENTS More Simulation Results of Testbench Circuits Conclusions CENT-MRF Preliminaries and Review Preliminaries on MRF Theory Previous Noise-immune Circuit Design Structures Proposed General Logic Gates Design Structure Noise-immunity Simulation Results of Different Design Structures Quantifying the Noise-immunity Simulation Results (SPICE) Simulation Results (SPECTRE) Discussions and Conclusions Analysis of Noise and SETs Reliability Analysis Model of CENT-MRF Modeling the Noise Analysis Modeling the Noise Analysis of CENT-MRF Structures Simulations With Hspice and Matlab Simulation Based on Hspice Simulation Based on Matlab Simulation Results Conclusions Reliability Analysis of Reed-Solomon Decoder Preliminaries on RS Decoder Probabilistic Modeling Process Modeling Probabilistic Gates Modeling Arithmetic Operations of Galois Field Simulation Results Brief of Monte Carlo Method Simulations of the Probabilistic Gates Simulations of the Arithmetic Operations in Galois Field Simulations of the Decoding Modules Conclusions Conclusions and Perspectives Conclusions Contributions Perspectives A Mathematical Derivations 65.1 The mathematical derivations Bibliography 67

14 List of Tables 2.1 Contribution ratio of neutrons to alpha particles for SER for different CMOS elements [6] The trend of supply voltage and frequency according to ITRS reports 2013 version [7] Characteristics of reliability evaluation methodologies Characteristics of reliability enhancement techniques Time consumption comparisons of PTM and ECPTM Memory usage comparisons of PTM and ECPTM All the possible input-output states of a two-input NAND gate Transistor numbers for different bench circuits Constraints of reliability improvement for CENT-MRF

15 x LIST OF TABLES

16 List of Figures 2.1 Different levels of unreliability Relationship of R(t), F(t) and f(t) Critical charge of different technology generations SERs contributed of individual elements Bit-flip rate due to thermal noise The probabilistic gate model A generic combinational logic circuit General scheme of a saboteur A generalized TMR system with MVC Process of reliability analysis Logic gate NAND with its PTM and ITM Structure of combinational circuits PTM matrices, M l k A general structure of benchcircuit Time consumption of PTM and ECPTM Memory usage of PTM and ECPTM Time consumption efficiency Memory usage efficiency Markov random field graph Lgic NAND gate and its MRF graph The two-input MRF NAND gate implementation The MAS MRF design structure The two-input MAS MRF NAND gate implementation The general proposed CENT-MRF circuit design The proposed CENT-MRF circuit design for a NAND gate The simulation process of a general logic combinational circuit The simulation result of a two-input NAND gate The KLDs of different design structures of a two-input NAND gate The KLDs of different design structures of a one-bit FA The KLDs of different design structures of a four-bit RCA The KLDs of different design structures of a two-input XOR gate The KLDs of different design structures of (8, 4) Hamming Decoder The noise model The noise model with noisy input signal The noise model of CENT-MRF The equivalent noise model of CENT-MRF

17 xii LIST OF FIGURES 5.5 Simulation scheme: Hspice Simulation scheme: Matlab The probability of noise being logic 1 of a FA and NI module The simulated RSN of FA with P The simulated RSN of FA with P The strcture of the RS Decoder The Probabilistic Gate Model The Simulation Results of Probabilistic Gates ( times) The Simulation Results of Arithmetic Operations ( times) The Simulation of the decoding process The Simulation Reliabilities of Different Modules ( times) The impact of Different Modules to the decoder ( times)

18 List of Acronyms SER soft error rate CENT-MRF Cost-Effective Noise-Tolerant Markov Random Fields CMOS Complementary Metal Oxide Semiconductor FIT Failure in Time IC Integrated Circuit IEEE Institute of Electrical and Electronics Engineers ITRS International Technology Roadmap for Semiconductors LUT Lookup Tables MAS-MRF Master-and-Slave MRF MC Monte-Carlo MOSFET Metal Oxide Semiconductor Field Effect Transistor MRF Markov Random Field MTTF Mean Time to Failure NMOS N-Channel Metal Oxide Semiconductor NMR N-tuple Modular Redundancy PMOS P-Channel Metal Oxide Semiconductor SET Single Event Transient SEU Single Event Upsets SNR Signal-to-Noise Ratio SoCs Systems-on-Chip TMR Triple Module Redundancy TTF Time to Failure W transistor Width IRPS International Reliability Physics Symposium

19 xiv List of Acronyms DRAM dynamic random access memory SRAM static random access memory PTM Probability Transfer Matrix MAS master and slave ECC error correcting codes CTMR Cascade TMR DCVS Differential Cascode Voltage Switch ECPTM efficient computation based on PTM MeV million electron volts SEE single event effect IBM International Business Machine PDF probability density function BPSG borophosphosilicate glass MeV mega-electron-volt GeV giga-electron-volt FO4 fan-out-of-4 RMS root-mean-square SPR signal probability reliability analysis PBM probability binomial model PGM probabilistic gate model BDEC Boolean Difference-based Error Calculator FIFA fault-inject-fault-analysis ADD Algebraic Decision Diagrams SPR-MP Multi Pass SPR PBR Probabilistic Binomial Reliability BDEC Boolean Difference-based Error Calculator FIFA fault-injection-fault-analysis RTL register transfer level PGM Probabilistic Gate Model PMC probabilistic model checking PDF Probability Density Function BN Bayesian Network

20 List of Acronyms xv RSN reliability induced by both SETs and noise RS Reed-Solomon

21 xvi List of Acronyms

22 Chapter 1 Introduction 1.1 Motivations Moore s Law has been the driven force of integrated circuits (ICs) industry since 1970s. The number of components (transistors or bits) per chip has increased dramatically for decades. This continuous trend of increase in integration density of CMOS (Complementary Metal-Oxide-Silicon) technology was made possible by dimension scaling technology conceptualized by R. Dennard [1]: in reducing the critical dimensions and keeping the electrical field constant, one can obtain transistors with higher speed and lower energy consumption. As mentioned in the International Technology Roadmap for Semiconductors (ITRS) 2007 [3], the operation frequency of a transistor will reach 12 GHz and the number of transistors contained in a single chip may be 12 billion in The main-stream geometric scale now is 22 nanometers in 2013 and will reach its theoretical limitation in years. With the dimension shrinking to nanometer regime, many challenges has risen, one of which is the reliability of nanometer-scale devices or circuits. The industry has benefited a lot from the trend of dimension scaling. The devices and systems attain high density, faster operation speed, lower supply voltage, etc.. However, in order to keep the energy consumption a constant or at a relatively low level, the supply voltage of the transistors should shrink linearly, which reduces the noise margin. The reduction of noise margin makes the transistors and devices more sensitive to noise perturbations and consequently makes the logic output of a single gate or a circuit no longer deterministic but probabilistic. Historically, the soft errors occurred mostly in the storage cells (e.g., flip-flops, latches and memory cells), or the devices in aerospace. The alpha particles and atmospheric neutrons existing in the earth atmosphere are able to generate a current pulse[8] which will induce a soft error if this current pulse sufficient enough in amplitude and time duration. Normally, these current pulses can not introduce soft errors for logic circuits because of the existence of masking effects: logical masking effect, electrical masking effect and latching-window masking effect [9] [10] [11] [12]. However, with the dimension scaling into nanometer domain, the drastic reduction of noise margin, the much higher operating frequency and the lower threshold voltage [13] have improved the probability of a current pulse captured by a latch and consequentially introduces a soft error in logic circuits, even on ground level [14]. As a result, the issue of reliability has become an important criterion in ICs design [15]. In order to design reliable electronic systems with unreliable transistors, we should evaluate the reliability of a circuit first. To achieve this, effective and efficient methodologies should be proposed, one of which is Probability Transfer Matrix (PTM) [16]. PTM is widely utilized as a reference methodology for its accuracy evaluate result. However, it is

23 2 Introduction not suitable for large circuits because of its high time and storage consumption. Thus we need to optimize PTM to improve its efficiency. Another issue in the ICs design is the noise-immunity. For the intrinsic random nature of noise, traditional fault-tolerant design methodologies based on hardware redundancy, e.g. Triple-Modular-Redundancy (TMR) [17] and Cascade TMR (CTMR) [18], are not capable to obtain noise-immunity. The noise interferes the input signal of each module and degrades the right judgment of the majority voter. The NAND-multiplexing methodology proposed by Von Neumann [19] can produce the reliable result using unreliable components. However, it needs an extremely high degree of redundancy [20] [21]. The reconfiguration technology is more effective to deal with manufacturing defects or permanent faults and requires enormous amounts of redundancy [22]. Therefore, the traditional approaches are not effective to attain noise-immunity for the random and dynamic nature of noise. Probabilistic-based technologies are more suitable to deal with this problem [23 25]. One of the promising noise-tolerant probabilistic-based designs is proposed in [26], which is based on Markov random field (MRF) [27]. According to Nepal et al. [26], the reliability or the noise-immunity of a circuit can be improved by maximizing the joint probability of valid input-output pairs with a cost of hardware redundancy. Furthermore, itwasoptimizedin[28]inordertoreduceitsareapenalty.in[29],amaster-and-slave MRF (MAS-MRF) design structure was proposed by Wey et al., which can obtain nearly the same noise-immune ability as structures in[26,28] but with fewer transistors. In addition to the area over-cost, another disadvantage of approaches proposed in [26,28,29] is that they did not propose a general design structure applicable to all the basic logic gates. In other words, we should design every single logic gate specially. Also another approach based on MRF was proposed in [30], which is based on Differential Cascode Voltage Switch (DCVS). However, this methodology is just desirable for an inverter. A general noise-tolerant design should be proposed with less area penalty. Moreover, in prior works, the reliability or the noise-immunity criterion is individually concerned [17 19, 26, 28, 29]. In other words, these methodologies only considered the influences of single event transients (SETs) or the noise-immunity. A model which takes account of the SETs and noise at the same time should be proposed and the trade-off between the reliability sole to SETs and noise-immunity should be obtained. 1.2 Objectives The main objectives of this thesis focus on the novel reliability evaluation methodology and the enhancement techniques for probabilistic circuits. Optimize the existing reliability analysis methodologies (PTM) for better performances (less time and storage consumption); Achieve efficient and effective methods to improve the reliability of probabilistic circuits; Set up a model to analyse the soft errors and noise-immunity at the same time. 1.3 Thesis Organization The thesis is organized as follows: Chapter 2 presents the basic definitions and concepts related to the issue of reliability in combinational logic circuits: the increasing SER (soft-error rate) on the ground-level, methods to evaluate the reliability of a combinational circuit, design structures to enhance

24 1.3 Thesis Organization 3 reliability, etc. This chapter will focus on the PTM methodology and discuss its drawbacks. It also studies the reliable circuit design with unreliable transistors, or the noise-tolerant circuit designs with noisy transistors. It reviews the basic design concept and structure based on Markov Random Fields (MRF). Also some improved design structure will be discussed. Chapter 3 proposes some efficient methods to evaluate the reliability of combinational circuits. These methods are mostly compared with PTM [31] [32] [33], and their efficiencies are mainly discussed in aspect of time consumption and memory usage. A general tool is designed for the reliability evaluation of a circuit with its corresponding netlist. A general circuit is designed for the efficiency verification. Some practical bench circuits are also utilized to describe the efficiency improvements of the proposed methods. Chapter 4 proposes a general cost-effective noise-tolerant MRF (CENT-MRF) method for a better trade-off between the area penalty and noise-immunity. It is a general design structure which can be easily applied to all the basic logic gates and functional blocks. Its noise-immunity is assessed with KLD for ST 65 nm CMOS library. Simulations are done in SPICE using the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [5] and in Spectre based on ST 65nm CMOS models. Chapter 5 introduces a model to analyze the reliability induced by both SETs and noise. It derives the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints. Chapter 6 describes the reliability evaluation of a specific application operator, the Reed Solomon (RS) decoder. It utilizes the Monte Carlo Methodology to set up a model to simulate the probabilistic gate behavior, the arithmetic operations of Galois Field GF(2 3 ) and the decoding modules of the Reed Solomon Decoder,with the gate error probability from 0 to With the simulation results, we can obtain which module(s) is the most sensitive one(s) to the gate error probability and most effective one(s) if we want to improve the reliability of the decoder. Chapter 7 shows conclusions of this work and presents perspectives and future research directions.

25 4 Introduction

26 Chapter 2 Reliability Evaluation Methodologies and Improvement Techniques Reliability becomes an important design criterion when CMOS technology scales into Deep Submicron Meter (DSM) or even nanometers [4, 8]. With higher operational frequency, lower supply voltage and steady reduction in noise margin, the transistors are more faultproneandonlyableto obtain theright outputwithaprobability. Thushowtoevaluate the reliability of a logic circuit and design reliable devices with the unreliable or probabilistic components is a continuous task during these years. This chapter firstly presents the basic preliminaries on reliability. It discusses the mechanisms of soft errors induced by alpha particles or high-energy neutrons in logic circuits. Also the impacts of thermal noise will be presented. Then it introduces the reliability evaluation methods and improvement techniques in combinational logic circuits with their corresponding merits and drawbacks. 2.1 Preliminaries on Reliability Basic Concepts An electrical system can be characterized by several properties, e.g., cost, performance and dependability [34]. In these properties, dependability has many attributes (for instance, reliability, safety, etc.). Ucla et al. defined dependability as the ability to deliver service that can justifiably be trusted, or the ability to avoid service failures that are more frequent and more severe than is acceptable to the user(s) [34]. An electrical system suffers from multiple risks which may cause different impairments to its dependability. In [35] [36], the author classified these different impairments of dependability to six levels (or states). Figure 2.1 gives a hierarchical illustration. Defect/component level: impairments of deviant atomic parts. Fault/logic level: impairments of deviant signals, paths or nodes. Error/information level: impairments of deviant information (data, internal states, etc.). Malfunction/system level: impairments of deviant functional behavior. Degradation/service level: impairments of deviant performance. Failure/result level: impairments of deviant outputs or actions.

27 6 Reliability Evaluation Methodologies and Improvement Techniques Figure 2.1: Different levels of undependability and their transition [35] [36]. These impairments can transfer among different levels. For example, a transistor may be defective with the aging effects. It can produce a wrong logic output which will be exposed as a fault. If this fault is exercised and propagates to a latch-up successfully, an erroneous information bit is generated. This error may influence or even dominate other sub-systems and introduce a malfunction impairments with imperfect error-tolerant designs. Finally, the malfunction impairments may have a catastrophic effect on the system service and eventually lead to a system failure [35]. In general, the faults can be classified into two categories: permanent and temporary faults [37]. The permanent faults are those faults normally found during the off-line testing by the manufactures. However, temporary faults are the main concern after the ICs are implemented in special application environment. Two kinds of temporary faults can be further classified: transient faults and intermittent faults [38 40]. They manifest similarly but several criteria can be used to determine the category of faults [38]. Firstly, the transient faults are induced mainly by the environmental parameters at random locations with random time duration while the intermittent faults occur at the same location from time to time. Secondly, the replacement of the defective part can fix the errors induced by intermittent faults while can not remove the transient faults. The temporary faults do not induce errors necessarily while by contrast, the permanent faults always make errors occur. While dependability is a concept hard to be defined quantitatively in a single metric, reliability is a property which can be expressed as the continuity of correct service [34], and can be measured with the probability to execute its expected function under specific environment within a given period of time [41]. Normally, reliability is denoted as R(t), or R. The given period time is often expressed as a limited time range [0,t]. Obviously, the original reliability R(0) equals to 1. The reliability of an electrical system can be evaluated. In order to measure the R(t), another two items should be defined, i.e., the unreliability F(t) and the fault rate f(t). The unreliability is the probability that a system fails to execute its specified function under given conditions within a time interval [t 0,t 1 ]. The fault rate f(t) is the probability density function (PDF) describing at which rate the failure occurs during a time interval [t 0,t 1 ]. Normally t 0 = 0. The relationship of these three items is illustrated in Figure2.2.

28 2.1 Preliminaries on Reliability 7 Figure 2.2: Relationship of R(t), F(t) and f(t). From the view of probability theory, we can obtain (2.1) and (2.2). F(t) = t 0 f(t) dt, R(t) = 1 F(t) = 1 t 0 f(t) dt (2.1) f(t) = dr(t) dt (2.2) The fault rate f(t) is often estimated by sampling efficient experiments data. For the reliability evaluation of electrical systems, the exponential f(t) is often utilized, as shown in (2.3). f(t) = λe λt, t > 0 (2.3) Thus the reliability R(t) of a system with fault rate f(t) can be expressed as R(t) = e λt (2.4) For integrated circuits, the fault rate is often characterized with failure in time (FIT), where one FIT stands for one failure in 10 9 hours [42]. Correspondingly, the reliability is often expressed by the mean time to failure, or MTTF. The MTTF is the expected time to failure of a system or, in other words, the mean of the time to failure (TTF). The relationship between them can be expressed with (2.5), with an assumption of the time interval T : [0, ]. MTTF = E(T) = tf(t) dt 0 ( ) dr(t) = t dt 0 dt = tr(t) 0 + R(t) dt = 0 R(t) dt 0 (2.5) Note that lim t tr(t) = 0. The reliability of a system, especially with respect to integrated circuits, will be 0 at the end of lifetime (t ) for the existing of aging effect,

29 8 Reliability Evaluation Methodologies and Improvement Techniques the radiation-induced soft errors, the thermal noise, etc.. With (2.4), MTTF and the reliability can be expressed as MTTF = R(t) dt = 1 0 λ (2.6) R(t) = e 1 MTTF t Two basic metrics of reliability evaluation exist according to the parameters in concern: functional reliability and signal reliability [43 45] [46]. The functional reliability concerns the probability of the continuous work without failures while on contrast, the signal reliability concerns the probability of right output of a component, e.g. a transistor, a sub-system block or a logic functional circuit.many parameters can influence the reliability of modern integrated circuits, e.g. radiation (alpha particles, neutrons, etc.), thermal noise, aging effect and process variations. This thesis focuses on the radiation-induced soft errors and the errors induced by thermal noise, which will be discussed in details in section and Radiation-induced Soft Errors Soft errors induced by radiation is now a threat to the modern ICs service time. The soft errors are events that the information datum are corrupted without a permanent device demage. In contrast, an error with a permanent device failure is called a hard error [47]. The soft errors can have different effects or influences on the system. On the one hand, it can corrupt the information bits of a system. On the other hand, these errors can induce a malfunction or even a device failure. Normally, the soft errors can be recovered by a reset, or diminished by a suitable fault-tolerant design. The rate of soft errors or soft errors rate occurrence in a given environment is denoted as SER. Usually, SER is measured in FIT units. In semiconductor industry, the FIT/Mb or FIT/device is also used to express the sensitivity of an individual element. Typical SER values for electronic systems range between a few 100 and about 100,000 FIT [47]. Historically, the radiation-induced soft errors mostly occur in aerospace applications or in military environments. The first report of soft errors in space applications was published by Binder et al. in 1975 [48]. The first paper of soft errors occurring at sea level, a new physical mechanism for soft errors in DRAMs [49], was proposed by May and Woods of Intel at the International Reliability Physics Symposium (IRPS) in In this paper, the soft errors were defined as radiation-induced single-bit errors, which are random and nonrecurring [47, 49], in memory cells. They were not caused by the electrical noise or electromagnetic interference but the radiation (or exactly, alpha particles). From then on, many researchers have investigated this issue for decades [47] [50] [51] [52]. In 1996, Ziegler et al. of IBM published a milestone paper [50]. In this paper, the authors analyzed the radiation sources, the SER induced by cosmic rays at different altitudes, the sensitivity and SER of different kinds of SRAM and DRAM, the SER of logic circuits, etc.. They concluded that the cosmic rays-induced neutrons with high-energy can also introduce a severe negative impact on the memories. Since 1970s, different mechanisms of radiation-induced soft errors have been researched. With technology dimension scaling and fabricating process or materials usage improvement, the dominant source of radiation changes. For applications at territorial level, radiation-induced soft errors are mainly the result of the following two sources [47] [51]: Alpha particles emitted by radioactive impurities (uranium and thorium) in package materials [49].ThiswasprovedtobethedominantsourceofsofterrorsinDRAM [53] in late 1970s.

30 2.1 Preliminaries on Reliability 9 Table 2.1: Contribution ratio of neutrons to alpha particles for SER for different CMOS elements [6]. Technology SRAM LATCH Combinational circuits 130 nm nm > nm High-energy neutrons (more than 1 mega-electron-volt (MeV)) generated by the highenergy cosmic rays (more than 2 GeV) interacting with the earths atmosphere [50] [47]. It was proved to be the main source of soft errors in DRAMs in mid-1990s [54]. In 1978, May and Woods of Intel discussed the soft error induced by alpha particles in DRAMs [49]. When alpha particles (emitted by the impurity in package materials) interact with silicon, electron-hole pairs are generated and collected by the depletion layers such that they can end up in the storage wells. If the number of accumulated electron-hole pairs finally exceeded the critical charge Q cirt (defined as the number of electrons that differentiates 0 and 1 in DRAMs), a soft error occurs. This kind of soft error is mostly caused by the impurities of the package materials, and the SER varies vastly in different application systems for a specific technology generation. The high-energy neutrons generated by cosmic rays interacting with the atmosphere can strike a sensitive region, deposit electron-hole pairs which can pass through the p- n junction. The combination of these electron-hole pairs can induce a short duration of current pulse in the internal node struck by the particle. If the sensitive region locates in a SRAM and the current pulse accumulates and may be sufficient enough to inverse the value stored in a memory cell, a soft error occurs. The minimum charge needed to flip the stored value is called the critical charge (Q cirt ) of SRAM cells. Many researches have pointed out that the SER of a constant area SRAM will increase with the CMOS technology scaling [55 57]. The contributions of alpha particles and the neutrons change with different technology generations. The trend is that the alpha particle plays a more important role with CMOS dimension scaling from 130nm to 65nm, which is clearly pointed out in Table 2.1 [6]. A model to estimate the SER in SRAM CMOS has been proposed recently by Hazucha & Svensson [58]. The model can be expressed as ( SER F A diff exp Q ) crit (2.7) Q s where F is the neutron flux with energy > 1 MeV, in particles/(cm 2 s) A diff is the area of sensitive region, in cm 2 Q crit is the critical charge of the SRAM CMOS, in fc Q s is the charge collect efficiency of the SRAM, in fc (2.8) The neutron flux F can be assumed to be constant in the SER estimation of different technologies. The sensitive area A diff to neutrons decreases with the CMOS dimension scaling. The critical charge Q crit depends on the characteristics of circuits, especially the supply voltage V dd and the capacitance of the drain node. Q s measures the efficiency of current charge collection of the node and decreases with the decreasing feature size. The ratio of Q crit and Q s plays an important role to SER due to the exponential impact. While both of them decrease with the CMOS geometric scaling, the critical charge approaches the efficiency charge collection with moving-forward technology generations. Shivakumar et al. tested the Q crit of SRAMs, latches, logic circuits of different technology generations and

31 10 Reliability Evaluation Methodologies and Improvement Techniques showed this approaching trend clearly in Figure 2.3 [10]. Hazucha et al. utilized this model to estimate SERs of different technologies for a constant area SRAM array and pointed out that the SER-per-chip will increase linearly with the decreasing feature size [10, 58]. Figure 2.3: Critical charge of different technology generations (figure from [10]). While the mechanisms of alpha particles and neutrons to generate soft errors are different, both of them induce soft errors by producing a transient current pulse sufficient enough [8] [59]. If this current pulse happens in a storage cell (e.g., a flip-flop, a latch or a memory cell) and is sufficiently strong, the logic state contained in the cell will be reversed, resulting in a SEU. If the transient current pulse happens in a logic circuits, it transforms to a transient voltage pulse(set). If this SET is sufficient enough in amplitude and duration, it will be captured at a logic latch or flip-flop and produces a soft error. Compared with SEU in memory cells, the SETs have different mechanisms to induce soft errors in combinational logic circuits. First, a SET is generated manifesting itself as a voltage glitch or a current disturbance. Then the SET should have the ability to propagate through sensitive paths and finally to becaptured as a soft error at the latches or flip-flops. Three masking effects are proposed to reduce the probability of a SET captured[10][9][11]: Logical masking occurs when a SET at a node whose influence will be eliminated by its corresponding gate or other subsequent gates; Electrical masking occurs when a SET does not have sufficient amplitude or time duration so that this SET will diminish with the propagation to the output of the circuit; Latching-window masking occurs when a SET propagates to the latch cell or filp-flop but fails to be captured by the synchronous clock window. With these masking effects, the SER in combinational logic circuits remains at a significantly low rate and even can be neglected [60]. However, with the feature size scaling down to DSM or even nanometer, the transistors become more susceptible to disturbances of radiation-induced current charge. The electrical masking effect is diminished because

32 2.1 Preliminaries on Reliability 11 the lower supply voltage and threshold voltage loosen the strict requirements on the amplitude and duration of SET. Also, the higher clock frequency increases the probability of a SET captured by the memory cells and reduces the effect of latch-windowing masking. With the shrinking dimension technology, these masking effects pose different impacts on the SER of logic circuits. In [10], the authors pointed out that the electrical masking has a significant effect on the SER of logic circuits of all technology generations and do not diminish with the scaling of feature size. On the contrary, the latching-window masking effect will be reduced with the dimension scaling and the speed increasing. A critical path must exist from the SET location to a latch, or the SET will belogically masked by the logic circuits. What s more, in order to propagate in logic circuits, the SET must have sufficient amplitude and duration. A model to simulate the transient fault propagation in combinational circuits was proposed in [61] [62], which also addressed the expressions of transient voltage pulse amplitude and duration sufficient enough to propagate. Many authors have pointed out that the SER in combinational circuits increase linearly with the operational frequency [63] [47] [64]. The increase of clock frequency increases the probability the SET captured and reduces the restriction on time duration of the voltage glitch or current disturbance. Mitra et al. [63] calculated the different SERs of individual elements (memory cells, combinational logic and sequential logic circuits) in the modern applications with high clock frequency(figure 2.4). Later, Gill et al.[64] compared the chip-level SER of combinational and sequential logic circuit at 32nm and pointed out that the SER of combinational logic is not a dominant contributor in chip-level 32nm technology. Figure 2.4: SERs contributed of individual elements (redrawn according to [63]) The Influence of Thermal Noise Even if soft errors induced by the radiation is a critical problem, a more serious issue is the increasing probability of thermal noise crossing the threshold voltage V th. When the thermal noise cross V th, a bit-flip occurs and may result in a soft error. The thermal noise is a stationary Gaussian stochastic process with zero as its mean value. In integrated circuits, a transistor can be described as the RC model and according to Johnson Nyquist formula, the root-mean-square (RMS) of the thermal noise voltage can be given as in (2.9), where the k is the Boltzmann constant, T is the temperature and C is the capacitance of gate. [2] kt U n = (2.9) C From (2.9), we can imply that the RMS of thermal noise voltage U n will increase steadily during miniaturization. One of the reasons is that the increased integrated density

33 12 Reliability Evaluation Methodologies and Improvement Techniques Table 2.2: The trend of supply voltage and frequency according to ITRS reports 2013 version [7]. Character Implementation Year Supply Voltage (V) On-chip Frequency (G hz ) and power consumption produce more heat which can increase the local temperature T. The other reason is that, with the CMOS dimension scaling, the capacitance of a transistor decreases. Meanwhile, the Rice formula [65,66] points out the mean frequency v of a Gaussian white noise crossing a threshold voltage V th in the integrated circuits as in (2.10), where V th is the threshold of the transistor, U n is the thermal noise voltage, and f c is assumed to be equal to the clock frequency. [2] v = 2 3 exp [ 1 2 ( Vth U n ) 2 ] f c (2.10) With (2.9) and (2.10), it can be pointed out that the increasing thermal noise voltage U n and the decreasing thermal voltage in the CMOS dimension shrinking process will make the bit-flip rate v increase rapidly. In [2], the author measured the bit-flip rate v due to thermal noise with different number of transistors under different clock frequencies. The results shown in Figure 2.5 points out that the ratio of V th U n has an experimental influence on the bit-flip rate Ghz, 1 transistor 2Ghz, 10 8 transistors Ghz, 10 9 transistors 2Ghz, transistors Ghz, transistors Figure 2.5: Bit-flip rate due to thermal noise (figure from [2]). Table 2.2 shows the main characteristics in CMOS technology as predicted in 2013 edition of ITRS report. In this section, we mainly focus on the supply voltage and the onchip local frequency. With the scaling in feature size, the reduced supply voltage and the increasing thermal noise approach to each other and make the bit-flip rate of transistors nonnegligible.

34 2.2 Reliability Evaluation Methodologies Reliability Evaluation Methodologies As mentioned above, the reliability has been an important concern in ICs designs. The transistors, gates or even circuits are no longer deterministic but probabilistic with the impacts of radiation, thermal noise or cross-talk noise, etc.. Denote the error probability of a gate as ǫ, ǫ [0,0.5]. A gate with error probability ǫ (0.5,1] is not realistic because it means this gate is more prone to faults. In this case, an addictive NOT gate at the output node can make it more reliable. Take the inverter as an example. Assume that the logic function of an ideal inverter is Y(t 2 ) = X(t 1 ), wheret 1 is thestartingtime pointofthecmosswitchingandt 2 represents the ending time point of the CMOS switching. X(t 1 ) is the input logic value at the time point t 1 and Y(t 2 ) is the output logic value at time point t 2. For an ideal inverter, if X(t 1 ) = 0 we can surely get Y(t 2 ) = 1, and vice versa. However, for a probabilistic inverter, if X(t 1 ) = 0, Y(t 2 ) has a probability to obtain a logic value of 0. And the probability is the error probability ǫ we defined before. The function of a probabilistic inverter can be expressed as (2.11) Y(t 2 ) = { X(t1 ) with probability 1 ǫ X(t 1 ) with probability ǫ (2.11) Generally, for an ideal logic gate, denote its logical function as Y = f(x 1,x 2,...,x m ), where x i (i = 1,2,...,m) are the m-inputs of the gate and Y is its ideal output. However, for a probabilistic gate, its behavior can be given as Y = { f(x1,x 2,...,x m ) with probability ǫ f(x 1,x 2,...,x m ) with probability 1 ǫ (2.12) where ǫ is the error probability of the probabilistic logic gate. Figure 2.6 presents a model to address the behavior of a probabilistic logic gate. The probabilistic gate has the same input I as an ideal gate, but the probabilistic gate may change output to its opposite (0 1, or 1 0) with a probability q = 1 p, where p is the probability of fault occurrence. In Figure 2.6, IdealGate produces the right 0 or 1. The Rand can produce a pseudorandom number m drawn from the standard uniform distribution on the open interval (0,1). If m > p, meaning that an error happens at this gate, the block Com will give out a 1 as one of the input of the exclusive or gate. The output O will be the inverse of the output of IdealGate. Otherwise the Com will produce a 0 and the output O will remain the same with the output of IdealGate. Probabilistic Logic Gate I IdealGate 0 or 1 O Rand m Com 0 or 1 Figure 2.6: The probabilistic gate model. Based on the illustrations of probabilistic gate, the definition of probabilistic circuit can be given as [67]:

35 14 Reliability Evaluation Methodologies and Improvement Techniques Definition 1 Consider a combinational circuit or component C that computes the mapping F : I O. C is called probabilistic circuit if each i I is mapped to each j O with some probabilities P(j i), and j P(j i) = 1. Figure 2.7 describes a probabilistic circuit C. Denote the input signals as x i,i = 1,2,...,M, the output signals as y j,j = 1,2,...,N and the circuit as C. X k, k = 0,1,2,...,2 M 1 represent the input vectors with each of the input signals at the logic state 0 or 1. Y t, t = 0,1,2,...,2 N 1 represent the output vectors with each of the output signals at the logic state 0 or 1. The signal reliability can be addressed as follows: R j = = 2 M 1 k=0 2 M 1 k=0 P((y j = correct),x k ) P((y j = correct) X k )P(X k ) (2.13) where R j is the signal reliability of output y j, j {1,2,...,N}. Thus the circuit reliability R C can be given as R C = N R j (2.14) j=1 Figure 2.7: A generic combinational logic circuit. Many methods have been proposed to estimate the reliability of logic circuits. Basically, these methods can be divided into three groups: simulation-based methods, analytical methods and the hybrid of them. The simulation-based methods require quite a large amountofinputvectors andthesamplesoftheoutputvectors, whichcostsalotoftimeand memory usage. Thus the simulation-based methods are not quite suitable for the realistic circuits, especially the larger ones. The analytical methods utilize mathematical models to represent the probabilistic behavior of probabilistic gates and transfer the reliability of circuits to a mathematical calculation. These methods are distinguished with each other by several characters: accuracy, scalability and penalty (time consumption, memory usage, etc.). Normally the accurate methods need more memory usage with larger time consumption. Thus a trade-off between the accuracy and the penalty is an important concern. The hybrid methods combine the simulation and the mathematical analysis to achieve a balance of the merits and drawbacks Simulation-based Methodologies The simulation-based methodologies [68 71] are actually statistical methods based on a Monte-Carlo (MC) framework. A large amount of pseudo-random vectors are generated as the inputs to the simulator of circuits. The simulator of circuits are often injected with faults or a model which can simulate the probabilistic behavior of the circuit. The output vectors of the simulator of the circuits are then sampled and reliability of the circuit can

36 2.2 Reliability Evaluation Methodologies 15 be maintained. The complexity of these methods is dependent on the scale of the circuits, especially the number of input signals. Thus these methods are not realistic for large circuits Analytical Methodologies Probabilistic Transfer Matrices (PTM) is a gate-level approach for accurately assess the reliability of a combinational circuit [16, 72] [73, 74]. Each conditional probability of every output vector given a particular input vector can be obtained accurately. Reliability calculation based on PTM involves matrices multiplications. The main drawbacks of PTM are the excessive amount of memory and computational complexity required to manipulate matrices. For a circuit with N-inputs and M-outputs, these grow exponentially with the number of inputs and outputs as O(2 M+N ), making PTM unpractical for the analysis of large circuits. Some methods have been proposed to decrease the time consumption and memory usage. In [75, 76], the authors proposed an approach to compress the memory space usage based on Algebraic Decision Diagrams (ADD). But it is effective only for square matrices, then dealing with non-square matrices requires zero-padding [75, 77]. Another improvement method is described in [78], which can effectively reduce the memory usage and time consumption by eliminating some useless but expensive inter-data. Compared with PTM, Signal Probability Reliability Analysis (SPR) [79, 80] is not based on the conditional probability of a output vector given a particular input vector but on the signal probability, which is defined as the probability of the value of the signal equals to 1. For a fault-prone logic signal, four states exist: signal=correct 0, signal=correct 1, signal=incorrect 0 and signal=incorrect 1. SPR calculates the reliability by computing the signal probability from the input to the output. In this process, the signal probability can be modified by the probabilistic logic gates and at the output, the accumulative probability of correct 0 and correct 1 is the signal reliability. The advantage of SPR is that its complexity is linear, which can reduce the time consumption and memory usage dramatically with comparison to PTM. The main drawback of this model is the signal correlations, which invalidates the straightforward computation of joint probabilities [80]. Thus it just attains an approximate result when signal correlations or fanout reconvergences exist in the circuits. Many methods has been proposed to deal with the signal correlations or reconvergent fanouts, for example, WAA [81] and DWAA [82]. Multi Pass SPR (SPR-MP) [80] is an effective method proposed to solve the problem of signal correlations by calculating the partial reliabilities (each of them is obtained at a particular single signal state) and accumulating them to attain the circuit reliability. An accurate estimate of the circuit reliability can be achieved with SPRA-MP. The main drawback of this method is that the time consumption increases exponentially with the number of fanouts. If the number of the fanouts is F, the complexity of SPR-MP is approximately O(4 F ). Another analytical method to overcome the impact of signal correlations is the Conditioned Probability Matrix (CPM) [83]. It decorrelates the correlate signals with conditional probabilities and accelerates the estimation process with direct SPR approach. Its complexity depends not on the size of the circuit but on the reconvergent sources, which are defined as the point at which signals correlates. Thus CPM can also deal with the scaliability problem with combinational circuits explosion. Han et al. presented a Probabilistic Gate Model (PGM) in [84]. This model relates the probability of output node to the probabilities of input signals and the error probability of the logic gate. Two computational algorithms are proposed with different merits. The approximate algorithm obtains an approximate evaluation of the circuit reliability without considering the signal correlations, and increases linearly with the number of gates. The accurate algorithm, with taking account of the signal dependency, can attain an accurate

37 16 Reliability Evaluation Methodologies and Improvement Techniques assessment of the reliability of a circuit but has an exponential complexity in the worst case. Sellers et al. introduced the concept of analysing errors with boolean difference first in [85], including the concept of how to use boolean difference in error-detect and error-correct logic circuits design. Mohyuddin et al. extended its application to reliability analysis in [86]. The authors presented a gate-level probabilistic error propagation model Boolean Difference-based Error Calculator (BDEC) which takes the boolean function of the gate, the signal error probabilities of the gate inputs and the gate error probability as its input parameters and produces the error probabilities of the outputs. It can achieve reliability estimation with high accuracy and scalability with a liner complexity in the number of gates of the circuits. The methodologies mentioned previously implement the Boolean logic to estimate the reliability of circuits. The probability of a signal or a node with value 0 or 1 is discrete. However, with the dimension scaling, especially with the reduction in noise margin, the thermal noise makes the discrete probability distribution unreasonable. A probabilisticbased methodology for nanoscale architecture design was proposed by Bahar et al. in [23]. The authors discussed a novel nanoscale architecture based on Markov Random Fields (MRF) [27]. Later, Lu et el. extended the concept of MRF-based design architecture and proposed a probabilistic logic to replace the Boolean logic for nanoscale devices in [87]. According to MRF, the conditional probability can be expressed in terms of a function contributed by its neighborhood. With the physical statistical physics [88], the Probability Density Function (PDF) of a node can be expressed by the energy level contributed by its neighboring nodes. Thus the probability of the output nodes can be achieved with the integration theory. Rejimon et al. proposed a probabilistic methodology based on Bayesian Network (BN) in [89]. The authors proposed a probabilistic error model based on BN and estimated the overall error probability of the output by comparing the fault-prone output to the ideal output. It was proved to be a compact and minimal framework to estimate the reliability of circuits Hybrid Methods of Reliability Analysis Different from the models based on PTM and signal probability, Probabilistic Binomial Reliability(PBR) [72,90] is based on the logic masking coefficients, which determines whether a fault of a gate or simultaneous faults of multiple gates can be propagated to the output. It poses the logical masking ability of the circuit to error(s) at different gate(s). The most important issue of this model is to find out these logical masking coefficients, which are usually obtained using simulators. Naviner et al. proposed a fault-injection-fault-analysis-based (FIFA) tool for reliability assessment at register transfer level (RTL) in [91]. The authors proposed a model to simulate the fault-free and the fault-prone gates. Figure 2.8 describes the hardware implementation. If e j = 0, the node is supposed to be fault-free. If e j = 1, the node is supposed to be fault-prone with a specific kind of faults defined by m[m 1 : m 0 ]. The specific fault can be SET or multiple transient faults, stuck-at-0 or stuck-at-1. The output of fault-free gates and fault-prone gates are compared to calculate the logic masking coefficients, with which the reliability can be attained with PBR. 2.3 Reliability Improvement Technologies In order to mitigate the impacts of soft errors, many approaches of reliability enhancement have been proposed, such as Triple-Modular-Redundancy(TMR)[17], Cascade TMR (CTMR) [18], NAND-multiplexing methodology [19]. These methodologies can effectively

38 2.3 Reliability Improvement Technologies 17 Figure 2.8: General scheme of a saboteur. improve the reliability at the cost of hardware redundancy. However, they can not deal with the impact of noise. On the other hand, many noise-immune design approaches have been proposed. Nepal et al. proposed a structure based on Markov Random Fields (MRF), in which the noiseimmunity can be improved by maximizing the joint probability of valid states at the cost of hardware redundancy [26]. Later, this solution was optimized in order to reduce the number of transistors [28, 29] Space Redundancy In 1956, John von Neumann introduced the idea of utilizing the redundancy adding of unreliable components to realize a reliable system [19]. After that, N-tuple modular redundancy (NMR) [92] was developed and widely used to improve the reliability of a generalized system. Especially, when N = 3, NMR is characterized as TMR (Triple Modular Redundancy). The degree of redundancy of a system can be denoted as D. In order to mask E soft errors, D should satisfy the following expression [93]: 2E +1 D (E +1) 2. (2.15) For a classic TMR, a voter should exist in order to determine the final output of the redundant blocks. Several voting strategies for fault-tolerant systems have been proposed such as voting mechanism of the majority, the median or plurality [94], of which the majority voting mechanism is more popular. Take the TMR system of Figure 2.9 as an example. As mentioned above, TMR can only mask one soft error. The number of combinations generated by selecting m elements out of n is given by N c = ( ) n = m n! (n m)!m! (2.16) Thusthenumberofcombinationsofselecting2elementsfrom3isN c = ( ) 3 2 = 3! (3 2)!2! = 3. Assume that the reliability of a single block is q. Then with a fault-free majority voting circuit (MVC), the reliability of the TMR system is given by [19]: R c = q 3 +3(q 2 )(1 q) = 3q 2 2q 3. (2.17) If we assume that the reliability of the MVC is R M, the reliability of the TMR-MVC system is given by R TMR MVC = R C R M = (3q 2 2q 3 )R M (2.18)

39 18 Reliability Evaluation Methodologies and Improvement Techniques I B B M V C O B Figure 2.9: A generalized TMR system with MVC. Although TMR is an effective approach to improve the reliability of a block, it still has some drawbacks. The area overhead of TMR is 3 A block, if we just take into account the block area A block. Many other efficient approaches have been proposed such as selective TMR (STMR) [95], TMR based on significance [96], progressive TMR(PTMR) [97] and progressive mixed modular redundancy (PMMR) [97]. The basic idea behind these approaches is to find out the critical or unreliable sub-blocks and improve the reliability of these sub-blocks to reduce the area overhead, given a reliability constraint. With the benefit of area overhead reduction, the different approaches mentioned have different disadvantages. The STMR just takes account of the gate property to judge the critical gates but ignores the circuit logical masking effect. The work reported in [96] proposes a more accurate approach by considering the logical masking effect of single gate. The example shown in [96] addressed that with the same area overhead, the TMR based on significance has a larger reliability improvement than STMR. The much more efficient approach is the PTMR or PMMR [97], whose objective is to minimize the area overhead with maximizing the reliability improvement Time Redundancy A hardware-based error detection system was proposed in [98]. The time redundancy can just detect the an error happening but cannot correct it. For a transient error, it can only last for a time delay of δ. So if we compare the outputs of a circuit at the time of t and t+δ, we can detect whether there is an error or not. Figure 2.10 shows the structure of a time redundancy system. I Comb Circuit Output Clk Latch 1 Comparator Error Indication Clk 2 Latch Figure 2.10: A generalized structure of time redundancy error-detection system. In Figure 2.10, two latches or flip-flops used to store the outputs at different times of CLK 1 and CLK 2, where the CLK 1 stands for the clock of of the functional latch and CLK 2 = CLK 1 + δ. As a matter of fact, this structure can detect the transient soft errors with duration time equal to or lower than δ. It also can detect some transient soft errors which can influence the output results with a duration time larger than δ, but

40 2.4 Conclusions 19 not all of them. On the other hand, not all the soft errors induced by SETs initiated at the internal gates of a circuit can be guaranteed to be detected even these SETs have duration lower than δ, especially when there are reconvergent paths in the circuit. In the propagation of the SET, the duration time may increase and when it reaches the circuit outputs, the duration may be larger than δ. The work reported in [99] also discussed the time redundancy and analyzed the scheme with different δ. Other designs combining the time and space redundancy have already been designed [100] Other Methodologies The CMOS dimension scaling technology has dramatically improved the performances of transistors and devices in the past decades. In order to keep the power dissipation constant or at a low degree, the supply voltage should scale linearly with the size [2]. In this situation, the reduction of noise margin makes the transistors and device working in a noisy signal environment. As a result, the transistors in nanometers are much more prone to soft errors, and thus the noise-immune ability of a logic gate or a circuit becomes an important design criterion [4]. For the intrinsic random nature of noise, traditional fault-tolerant design methodologies based on hardware redundancy, e.g. Triple-Modular-Redundancy (TMR) [17] and Cascade TMR (CTMR) [18], are not capable to obtain noise-immunity. The noise interferes the input signal of each module and degrades the right judgment of the majority voter. The NAND-multiplexing methodology proposed by Von Neumann [19] can produce the reliable result using unreliable components. However, it needs an extremely high degree of redundancy [20]. The reconfiguration technology is more effective to deal with manufacturing defects or permanent faults and requires enormous amounts of redundancy [22]. Therefore, the traditional approaches are not effective to attain noise-immunity for the random and dynamic nature of noise. Probabilistic-based technologies are more suitable to deal with this problem [23 25]. One of the promising noise-tolerant probabilistic-based designs is proposed in [26], which is based on Markov random field (MRF) [27]. According to Nepal et al., the reliability or the noise-immunity of a circuit can be improved by maximizing the joint probability of valid input-output pairs with a cost of hardware redundancy. Furthermore, it was optimized in [28] in order to reduce its area penalty. In [29], a Master-and-Slave MRF (MAS MRF) design structure was proposed by Wey et al., which can obtain nearly the same noise-immune ability as structures in [26, 28] but with fewer transistors. In addition to the area over-cost, another disadvantage of approaches proposed in [26,28,29] is that they did not propose a general design structure applicable to all the basic logic gates. In other words, we should design every single logic gate specially. Also another approach based on MRF was proposed in [30], which is based on Differential Cascode Voltage Switch (DCVS). However, this methodology is just desirable for an inverter. 2.4 Conclusions In this section, we reviewed the preliminaries on reliability, the methodologies of reliability evaluation and the reliability improvement techniques. Figure 2.11 illustrates the inner logic for the reliability analysis. For the evaluation methodologies of reliability, Table 2.3 presents the characteristics of them with their merits and bottlenecks, correspondingly. For the reliability enhancement techniques, Table 2.4 illustrates the characteristics of them with their advantages and drawbacks, correspondingly.

41 20 Reliability Evaluation Methodologies and Improvement Techniques Figure 2.11: The process of reliability analysis. Table 2.3: Characteristics of reliability evaluation methodologies Category Method Accuracy Speed Memory consumption Scalability Simulation-based methods Based on Monte Carlo [68 71] adaptive slow high no PTM [16, 72] exact slow high no Analytical SPR [79] low fast low yes methods SPR-MP [80] exact slow high no CPM [83] exact adaptive high no PGM (approximate [84]) low fast low yes PGM (accurate) [84] exact adaptive high no BDEC [86] high fast low yes BN [89] exact medium high no Hybrid methods PBR [90, 91] exact slow low no Table 2.4: Characteristics of reliability enhancement techniques Technique Concept Characteristics Drawbacks TMR [92 94], CTMR [18] replicate the unreliable components and select the right result with a voter easy to implement large penalty NAND-multiplexing [19, 20] a bulk of NAND gates with their outputs achieve reliable as the inputs of next bulk of NAND gates randomly system with unreliable components STMR [95], PTMR [97], PMMR [97] selective the critical components and implement reduce the area TMR to them penalty MRF [26, 28], MAS MRF [29] DCVS [30] improve the reliability or the noiseimmunity of a circuit by maximizing the joint probability of valid input-output pairs with a cost of hardware redundancy generate the complementary signal with differential cascode voltage switch probabilisticbased technique suitable for noisetolerant designs small penalty area extremely high redundancy hard to choose the critical components large area penalty with specific structures for different logic gates only implemented to inverter

42 Chapter 3 Efficient Evaluation Methodology Based on PTM Probabilistic transfer matrix (PTM) is a gate-level approach for accurately assess the reliability of a combinational circuit[16,72]. The main drawbacks of PTM are the excessive amount of memory and computational complexity required to manipulate matrices. For a circuit with N-inputs and M-outputs, these grow exponentially with the number of inputs and outputs as O(2 M+N ), then making PTM unpractical for the analysis of large circuits. In this chapter, an efficient reliability evaluation methodology based on PTM (denoted as ECPTM) will be presented. Its algorithm and complexity will be discussed mathematically. In order to express the penalty (time consumption or memory usage) comparison between traditional PTM and ECPTM, a general test bechcircuit is designed with a controllable size. At last, more simulations are implemented to specific benchcircuits and conclusions will be obtained. 3.1 Probabilistic Transfer Matrix Assume a logic circuit with input x and output y, where x {x 0,x 1,,x i,,x 2 m 1} and y {y 0,y 1,,y j,,y 2 n 1}. The corresponding PTM, denoted M, has 2 m 2 n elements and each (i,j) element is the probability of getting output y = y j given the occurrence of input x = x i, noted p(j i). In the case of an ideal (i.e. fault free) circuit, the PTM contains only zeros and ones and is named ITM (Ideal Transfer Matrix). Figure 3.1 shows the PTM for an NAND logic gate with error probability equals to 1 q, where q represents the probability of getting a correct output. It should be noted that ITM is defined for q = 1. a 1 a 0 b (a 1,a 0 ) p q p q p q q p 1 0 Figure 3.1: Logic gate NAND with its PTM and ITM. The reliability of a circuit is directly extracted from the respective PTM and ITM, according to (3.1), where p(i) denotes the probability that input x is x i. R = IT M(i,j)=1 p(j i)p(i) (3.1)

43 22 Efficient Evaluation Methodology Based on PTM The expression above gives the sum of probabilities corresponding to correct outputs. That is, the element in position (i,j) of PTM matrix will contribute to the sum only if the respective (i,j) element of the ITM has a value 1. Since the PTM gives the exact probabilities of getting correct outputs, the above expression provides accurate reliability assessment. To calculate PTM of a whole circuit, PTMs of its basic gates are combined by using matrix operations, depending on the manner as they are assembled. Let be the gates G 1 G 2, with their respective PTMs M G1 and M G2. If G 1 and G 2 are connected in series, the global PTM M T can be achieved by M G1 M G2. If G 1 and G 2 are connected in parallel, the global PTM M T can be computated with tensor product,. Thus the resulting global PTM is M G1 M G2. Assuming the input of G k is a m k -bits vector while its output is a n k -bits vector. The PTM of a logic gate G k, noted M Gk, contains 2 m k 2 n k = 2 m k+n k elements. The computational complexity C T related to obtaining the resulting matrix M T can be expressed in terms of the cost and the number of multiplications and additions between elements of the basic involved matrices M Gk PTM Computation of Gates Connected in Series If G 1 and G 2 are connected in series, n 1 must be equals to m 2. Each element in the resulting matrix can be expressed as: Z(i,j) = 2 n 1 1 u=0 M 1 (i,u) M 2 (u,j) (3.2) The matrix M T countains 2 m 1 2 n 2 elements, then the total number of arithmetic operations required to obtain it is given by (3.3), where C denotes the complexity of a multiplicationwhilec denotesthecomplexityofanaddition.thisleadstothecomplexity estimation as O(2 m 1+n 2 +n 1 ). C Z = 2 m 1 2 n 2 [2 n 1 C +(2 n 1 1) C ] (3.3) PTM Computation for Gates Connected in Parallel In the case of gates connected in parallel, each element in the resulting matrix can be expressed as (3.4), where u = i mod m 2 and v = j mod n 2. P(i,j) = M 1 ( i /m 2 +1, j /n 2 +1) M 2 (u,v) (3.4) ThematrixM T contains2 m 1+m 2 2 n 1+n 2 elements, thenthetotal numberofarithmetic operations required to obtain it is given by (3.3), where C denotes the complexity of a multiplication while C denotes the complexity of an addition. Similarly to gates in series, the complexity related to gates connected in parallel is O(2 m 1+m 2 +n 1 +n 2 ). C P = 2 m 1+m 2 2 n 1+n 2 C (3.5)

44 3.2 Efficient Computation of PTM (ECPTM) Efficient Computation of PTM (ECPTM) Let be a general combinational circuit as shown in Figure 3.4. To calculate the reliability of such a circuit as defined in (3.1), the circuit PTM calculation is required. To calculate the PTM of a complex circuit including several gates in series and in parallel, the basic idea is to divide it as a cascade of W subcircuits or levels (see Figure 3.4.a). m 1/ L1 n 1 / L2 n 2 / m l / L l n l / mk / LW n K/ (a) m l 1 / B l 1 n l 1 / m l 2 / B l 2 n l 2 / m l k / B l k n l k / m l K l / B l K l n l K l / (b) Figure 3.2: (a) Cascade of W levels (or groups) of combinational blocks. (b) Detail of the parallel sub-blocks in the l th level. Each level l has a PTM matrix, noted PK l l, that results of tensor products applied to PTMs of all K l parallel Bk l logic blocks existing in level l (see Figure 3.4.b) PTM Calculation of Complex Circuits The global PTM, noted Z W, is given by progressive calculation of inner products of the W level matrices P l K l as below, where Z l corresponds to the PTM for the cascade of first l levels: Z 2 = PK 1 1 PK 2 2 Z 3 = ( PK 1 1 PK ) P K3 = Z 2 PK 3 3 Z 4 = (( PK 1 1 PK ) P K3 ) P K4 = Z 3 PK 4 4. =. Z W = ( (( PK 1 1 PK 2 3 W 2 ) P K3 ) ) P KW = Z W 1 PK W W At each step (or level l taken into account), a new PTM Z l is obtained. Each matrix Z l has a number of elements which depends of the of number of rows in the first level (that is, P 1 K 1 ) and the number of columns in the matrix of level l (that is, P l K l ).

45 24 Efficient Evaluation Methodology Based on PTM The number of rows in PK l l comes from the number m l k of rows in the basic matrices of level l, noted Mk l. Hence, r l = K l 1 ml k. Equivalently, the number of columns in Pl K l is c l = K l 1 nl k. The total number of elements to be calculated to get Z l is given by (3.6) and the respective computational cost is given by (3.7), where r l and c l are, respectively, the number of rows and columns in PK l l. N = N = l (r 1 c u ) (3.6) u=2 l (r 1 c u )[c u 1 C +(c u 1 1) C ] (3.7) u=2 It should be noted that when PTM computation is done solely in order to assess reliability as given in (3.1), only a subset of elements Z K (i,j) in matrix Z K are required. Actually, they are those corresponding to coordinates (i, j) such that the element (i, j) in the ideal transfer matrix is 1. For a circuit with m 1 binary inputs and n K binary outputs as in Figure 3.4, it means that only 2 m 1 elements of Z K are necessary, instead of 2 m 1 2 m K.Onlythenecessaryelements Z K (i,j) arecalculated andthusthecomputational complexity to get the value R can be reduced Efficient Tensor Product Calculation Let Mk l be the PTM matrix for the block Bl k, i.e. the kth logic block in the level l. Traditional approach for calculating tensor products of such K l blocks in parallel consists in progressively get matrices Pk l with k [2,K], as seen in (3.8) to (3.11). P l 2 = M l 1 M l 2 (3.8) P l 3 = M l 1 M l 2 M l 3 = P l 2 M l 3 (3.9) P l 4 = M l 1 M l 2 M l 3 M l 4 = P l 3 M l 4 (3.10). =. P l K l = M l 1 Ml K l = P l K l 1 Ml K l (3.11) The computation of each (i,j) element of a matrix Pk l = Pl k 1 Ml k is as described in (3.4) and requires one 2-operands multiplication. The computation effort Ck l for obtaining Pk l accordingly to (3.5) is given in (3.12), where Sl k denotes the size of the matrix Pl k. It s easy to see that Sk l is as in (3.13). C l k = Sl k C (3.12) S l k = 2 k u=1 ml u 2 k u=1 nl u (3.13) Therefore, the total effort to get the PTM corresponding to K blocks in parallel at level l is given by (3.14), which means large memory requirements and amount of multiplications. K l C l = Sk l C (3.14) k=2

46 3.2 Efficient Computation of PTM (ECPTM) 25 Instead of this progressive computing, the matrix PK l can beachieved directly from Ml k matrices. This way, no intermediary memory is required and multiplications are only those related to one (the final) matrix. Indeed, each element in PK l comes from a K l-operands product, where each operand is judiciously picked in each matrix Mk l. In order to define such operands, the following definitions should be considered: r l k is the number of rows in matrix Ml k, then rl k = 2ml k c l k is the number of columns in matrix Ml k, then cl k = 2nl k α l k is the number of rows in matrix Pl k, then αl k = k u=1 2ml u β l k is the number of columns in matrix Pl k, then βl k = k u=1 2nl u Thecoordinates of M l k s elements, noted (i k,j k ), involved in the calculation of P l K l (i,j) are such as in (3.15) and (3.16). This leads to : i k = i /α l k 1 j k = j /β l k 1 [ Kl k 1 v=0 [ Kl k 1 v=0 K l PK l (i,j) = k=1 ( ( i Kl v j Kl v K l 1 v u=k K l 1 v u=k r l u c l u )] )] (3.15) (3.16) M l k (i k,j k ) (3.17) Of course, (3.17) must be implemented S Kl times, where S K = 2 K u=1 ml k 2 K u=1 nl u. Supposing computational cost for a K operands multiplication is equivalent to (K 1) multiplications of two operands, the total computational cost becomes: C l = S Kl (K l 1) C (3.18) In order to illustrate the proposed approach for tensor calculation, a group of parallel blocks as shown in Figure 3.4.b are taken into account of, where K l = 4. The blocks B1 l, B2 l, Bl 3 and Bl 4 are a 2:1 multiplexer, a xor gate, a nor gate and a not gate, respectively. The matrices Mk l of these blocks are shown in Figure 3.3. The PTM of the whole group, noted P 4, will contain 256 rows and 16 columns. Take the calculation of P 4 (211,12) as an example. According to previous section, the following calculation process can be obtained: and then: i 4 = 211 /32 = 6 i 3 = 211 /8 6 4 = 2 i 2 = 211 /2 ( ) = 1 i 1 = 211 /1 ( ) = 1 j 4 = 12 /8 = 1 j 3 = 12 /4 (1 2) = 1 j 2 = 12 /2 ( ) = 0 j 1 = 12 /1 ( ) = 0

47 26 Efficient Evaluation Methodology Based on PTM a 7 a 6 b 3 a 5 Mux a 7 a 6 a q p 001 p q 010 q p 011 p q 100 q p 101 q p 110 p q 111 p q a 4 a 3 b 2 a 2 a 1 b 1 a 4 a q p 01 p q 10 p q 11 q p a 2 a p q 01 q p 10 q p 11 q p a 0 a [ b 0 0 q p 1 p q ] Figure 3.3: PTM matrices, M l k.

48 3.3 The Efficiency of ECPTM 27 P 4 (211,12) = M 1 (6,1) M 2 (2,1) M 3 (1,0) M 4 (1,0) = q 2 p 2 It s important to note that in the case of binary inputs and outputs, (3.15) and (3.16) don t require any computation, as their results can be get directly from the (i, j) coordinates. i 4 i 2 {}}{{}}{ i = a 7 a 6 a 5 a 4 a }{{} 3 a 2 a 1 a }{{} 0 i 3 j = j 4 {}}{ b 3 b 2 }{{} j 3 j 2 {}}{ i 1 = b 1 b }{{} 0 = j The Efficiency of ECPTM A General Testbench Circuit 6 {}}{ {}}{ 1 1 }{{} 2 }{{} 1 1 {}}{ 01 1 }{{} 1 0 {}}{ 0 0 }{{} 0 In this section, a general benchcircuit is designed to compute the efficiency of our proposed method. For simplicity but with generality, a circuit with same levels and same gates in each level is constructed. Its structure can be expressed in Figure 3.4. With this assumption, what should be ensures is that m = n and m l = n l for all the levels, l = 1,2,,W. m / L1 n / L2 n / m / Ll n / m / LW n / (a) m l / G l 1 m l / G l 2 n l / n l / m l / G l k n l / m l / G l K n l / (b) Figure 3.4: (a)the structure of our testbench circuit. (b) Detail of the l th level The Efficiency Experimental Results From the benchcircuit structure above, the simpliest circuit maybe set the G l as an Inverter. In this section, the time consumption and memory usage for different W and K are simulated. In the simulations, the number of levels are set to discrete numbers of

49 28 Efficient Evaluation Methodology Based on PTM Table 3.1: Time consumption comparisons of PTM and ECPTM Bench circuits PTM(s) ECPTM(s) Improvement C % Half adder % Full adder % 2-bit RCA % 3-bit RCA % 4-bit RCA % W = 5,10,20,30,40,50,100. The number of parallel gates contained in a single level are set to discrete numbers of K = 5,6,7,8,9,10. The simulations were executed on a computer with an Intel(R) Xeon(R) E GHz CPU and 250G RAM. The results are shown in Figure 3.5 to Figure 3.6. The time consumption and memory usage reduction can be obtained in Figure 3.7 and Figure 3.8. Time consumption (s) K=5, PTM K=5, ECPTM The number of levels W Time consumption (s) K=6, PTM K=6, ECPTM The number of levels W Time consumption (s) K=7, PTM K=7, ECPTM The number of levels W Time consumption (s) K=8, PTM K=8, ECPTM The number of levels W Time consumption (s) K=9, PTM K=9, ECPTM The number of levels W Time consumption (s) K=10, PTM K=10, ECPTM The number of levels W Figure 3.5: Time consumption of PTM and ECPTM with different W and K. From Figure 3.5 and Figure 3.6, what can be pointed out for a given K is that, with the number of levels W increasing, the time consumption and memory usage also increases linearly More Simulation Results of Testbench Circuits Several benchmark test circuits have been tested to verify the efficiency of the proposed method for reliability assessment based on PTM (ECPTM). The results were obtained in a computer with a 2.0GHz AMD Athlon(tm) Dual Core Processor and 2G memory. Table 3.1 and Table 3.2 show the time consumption and memory usage for traditional PTM and proposed ECPTM. The memory usage reduction is at least 50% and the time consumption reduction varies according to the complexity of the circuits.

50 3.3 The Efficiency of ECPTM 29 Memory usage (MB) Memory usage (MB) Memory usage (MB) K=5, PTM K=5, ECPTM The number of levels W K=7, PTM K=7, ECPTM The number of levels W K=9, PTM K=9, ECPTM The number of levels W Memory usage (MB) Memory usage (MB) Memory usage (MB) K=6, PTM K=6, ECPTM The number of levels W K=8, PTM K=8, ECPTM The number of levels W K=10, PTM K=10, ECPTM The number of levels W Figure 3.6: Memory usage of PTM and ECPTM with different W and K. Time consumption efficiency K=5 K=6 K=7 K=8 K=9 K= The number of levels W Figure 3.7: Time consumption efficiency with different W and K.

51 30 Efficient Evaluation Methodology Based on PTM Memory usage efficiency K=5 K=6 K=7 K=8 K=9 K= The number of levels W Figure 3.8: Memory usage efficiency with different W and K. Table 3.2: Memory usage comparisons of PTM and ECPTM Bench circuits PTM(Mb) ECPTM(Mb) Improvement C % Half adder % Full adder % 2-bit RCA % 3-bit RCA % 4-bit RCA % 3.4 Conclusions This chapter dealt with reliability assessment of combinational circuits. It considered probability transfer matrix as this method leads to accurate reliability calculation. It focused on the reduction of computational complexity and memory requirements for traditional PTM implementation. Then, an optimization of PTM calculation was proposed by reducing computational cost of parallel and series blocks processing. Some benchmark circuits have been utilized to verify the performances of the proposed ECPTM against traditional PTM. The results showed that the proposed method can efficiently reduce the time consumption and memory usage. From Figure 3.7 to Figure 3.8, what can be pointed out is that: For all the W and K, the time efficiency is at least 1, meaning that at least 50% of time consumption can be reduced; For the time consumption efficiency, when K is lower than 9, the efficiency slows withthew increasing. When thek is10, thetime efficiency is morethan2, meaning of a benefit of more than 60% for the time consumption; For the memory usage, the efficiencies grow with the number of levels W increasing. Theefficiency is at least 1.5, or approximately at least 67% reduction for thememory

52 3.4 Conclusions 31 usage; The efficiencies of the memory usage are almost the same for different K. From Table 3.1 and Table 3.2, it can bepointed out that ECPTM approach efficiently reduces the time consumption and memory usage. The results showed that our proposed method can reduce the time consumption of at least 50%. For the memory usage, our proposed method can save at least 67% memory storage compared with the traditional PTM. Further, the efficiency obtained increases with the size of the circuit. The larger the circuit (i.e. number of logic blocks, complexity), the greater the reduction in computation and memory requirements.

53 32 Efficient Evaluation Methodology Based on PTM

54 Chapter 4 General Cost-effective Noise-tolerant Design Structure In this chapter, a general cost-effective noise-tolerant MRF(CENT-MRF) design structure of logic functions will be proposed. First, the preliminaries on MRF theory and the previous noise-immune circuit design structures will be reviewed. Then it will describe the proposed design structure with its comparisons to other MRF design structures. Some simulation results of the basic logic gates and some benchcircuits will be presented. Simulations have been done in SPICE using the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [5] and in Spectre based on ST 65nm CMOS models. Finally, discussions and conclusions are given. 4.1 Preliminaries on MRF Theory and Review of Previous Noiseimmune Circuit Design Structures Preliminaries on MRF Theory Define a set of random variables as χ = x 0,x 1,...,x k. Each variable x i can take various values from a value set Ω, which can be defined either continuous or discrete according to the model requirements. In special cases (e.g., digital circuit design), Ω = {0, 1}. Each variable x i has a neighborhood defined as Λ i, Λ i {χ x i }. Take the graph shown in Figure 4.1 as an example. In this case, x 0 has a neighborhood Λ 0 = {x 1,x 2,x 3 }, and x 1 has a neighborhood Λ 1 = {x 0 }. The combination of a variable x i and its neighborhood Λ i is called a clique from the graph view. The cliques combination is denoted as C and c is a subset of C. X1 X2 X0 X3 X4 Figure 4.1: Markov random field graph. If χ satisfies the following conditions, χ is called a Markov Random Field (MRF) [27]: P(x i = o l ) > 0, x i χ, o l Ω (4.1)

55 34 CENT-MRF P(x i = o l {χ x i }) = P(x i = o l Λ i ) (4.2) According to the definitions, positivity (4.1) and Markovianity (4.2) respectively, the conditional probability of a variable only relies on its own neighborhood. For a given MRF χ, the joint probability can be expressed as (4.3), where x i χ, i = 1,2,...,k. p(χ) = p(x 1,x 2,...,x k ) (4.3) It is difficult to calculate equation (4.3) directly, especially when χ contains a large number of variables. However, as pointed out by Hammersley-Clifford theorem [101], the joint probability can be formulated as p(χ) = p(x 1,x 2,...,x k ) = c CF c (x c ) (4.4) Here F c (x c ) is called Gibbs energy function and stands for the joint probability of a clique of variables. An explicit expression of F c (x c ) is given by the Gibbs distribution in F c (x c ) = 1 Z e U(xc) k b T (4.5) where Z is the normalization constant to make the summation of F c (x c ) equal to 1. U(x c ) is the clique energy and depends only on the variables of clique c. k b is the Boltzmann constant and T is the temperature Previous Noise-immune Circuit Design Structures From equations (4.3), (4.4) and (4.5), it can be deduced that if the temperature is set to be a constant, a higher U(x c ) will generate a smaller value of energy function F c (x c ) and consequently a lower joint probability p(χ). Thus, the noise-immune ability can be improved by minimizing the U(x c ). Before implementing the noise-immune circuit design, a logic gate or a circuit should be mapped to a MRF graph. In this mapping process, every signal of a circuit should be represented as a variable or a node. If a signal dependence exists between two signals, an edge should be added between the two corresponding nodes graphically. For example, Figure 4.2 represents the MRF graph of a two-input NAND gate. All the possible inputoutput states are described in Table 4.1, where x 0, x 1 are the two inputs, x 2 is the output andf(x 0,x 1,x 2 ) representswhethertheinput-outputstateisvalidornot.iff ( x 0,x 1,x 2 ) = 1, it is a reasonable state and, on the contrary, if f(x 0,x 1,x 2 ) = 0 describes an invalid or a false state. x x 0 1 (a) x Figure 4.2: The two-input logic NAND gate(left) and its corresponding MRF graph(right). 2 x x 0 1 (b) x 2

56 4.1 Preliminaries and Review 35 Table 4.1: All the possible input-output states of a two-input NAND gate x 0 x 1 x 2 f(x 0,x 1,x 2 ) AccordingtoTable4.1,thevalidinput-outputstatesareS(s 0 s 1 s 2 ) = {001,011,101,110}. Thustheenergyfunctionofs 0 s 1 s 2 canbeexpressedastheminussummationoverminterms of the valid states [26]: U(s 0,s 1,s 2 ) = f i (s 0,s 1,s 2 ) i = (s 0 s 1 s 2 +s 0 s 1 s 2 +s 0 s 1 s 2 +s 0 s 1 s 2 ) (4.6) InordertomaptheMRFto anoise-immunecircuit, threesteps [26] shouldbefollowed: Step 1: for each variable x i, a bistable storage element should exist with the value of 0 and 1 ; Step 2: each valid state in equations (4.6) should be generated; Step 3: a feedback loop should exist for each valid state to enhance its stability, consequently maximizing the joint probability of correct logical values. Take the mapping of a logic NAND gate as an example. Three variables exist here: x 0, x 1 and x 2, each of them taking two values 0 or 1. Then each valid state should be generated by a combinational sub-circuit and finally the feedback loops enhances the valid states. The circuit diagram of a noise-immune NAND is presented in Figure 4.3. According to the Boolean simplification and valid minterms reduction, an optimized expression of equation (4.6) is given as: U(s 0,s 1,s 2 ) = f i (s 0,s 1,s 2 ) i = (s 0 s 1 s 2 +s 0 s 1 s 2 +s 0 s 1 s 2 +s 0 s 1 s 2 ) = ((s 0 +s 1 )s 2 +(s 0 s 1 )s 2 ) (4.7) According to equation (4.7), Nepal et al. optimized the generation of the valid states and thus reduced the transistor numbers, as proposed in [28]. Another design structure is MAS MRF [29]. Its structure is shown in Figure 4.4. The Master subset generates the valid states and the Slave subset is the feedback loop. The Master subset divides the valid states into the valid groups 0 and 1. All the valid states with the output value 1 compose the 1 group and those with output value 0

57 36 CENT-MRF X0 X0 X1 X1 X2 X2 NAND NAND NAND NAND NAND NAND NAND NAND NAND NOT NOT NOT NOT NOT NOT NOT Figure 4.3: The two-input MRF NAND gate implementation. The two inputs are x 0 and x 1, the output is x 2. compose 0 group. Compared with [26], another advantage of MAS MRF is the redesign of the feedback loop, which reduces the transistor number and the hardware complexity. For example, for a MAS MRF NAND logic gate, the minterms with s 2 belong to group 1 and the minterms with s 2 belong to group 0. It reduces the valid states generator from four NAND gates in Figure 4.3 to one NAND gate, one NOR gate plus two inverters. As for the feedback loop, it contains only two NAND gates and two inverters while in Figure 4.3, five NAND gates and seven inverters are required. The MAS MRF NAND gate is presented in Figure 4.5. Master Slave X0... Xn-1 Valid States 1 Xn X0... Xn-1 Valid States 0 Feedback Connector Xn Figure 4.4: The MAS MRF design structure.

58 4.2 Proposed General Logic Gates Design Structure 37 S X NO NOT NAND NOT X NAND NOT NAND NOT Figure 4.5: The two-input MAS MRF NAND gate implementation. 4.2 Proposed General Logic Gates Design Structure We propose a general Cost-Effective Noise-Tolerant circuit design structure based on Markov Random Field, named CENT-MRF. In order to illustrate the proposed approach, take account of the NAND gate. Its corresponding energy function is given in equation (4.7). We know that Thus, equation (4.7) can be formulated to: s 0 +s 1 = s 0 s 1 (4.8) U(s 0,s 1,s 2 ) = ((s 0 +s 1 )s 2 +s 0 s 1 s 2 ) = (s 0 s 1 s 2 +s 0 s 1 s 2 ) = (F NAND (s 0,s 1 )s 2 +F NAND (s 0,s 1 )s 2 ) (4.9) where F NAND (s 0,s 1 ) is the logic function of a NAND gate. Its input signals are s 0, s 1 and its output signal is s 2. We propose to proceed in the same way to obtain the energy function of any logic gate. Especially, this produces the energy function for the basic logic gates as shown bellow. For an inverter: U(s 0,s 1 ) = (s 0 s 1 +s 0 s 1 ) = (F INV (s 0 )s 1 +F INV (s 0 )s 1 ) (4.10) For a NOR gate: U(s 0,s 1,s 2 ) = (s 0 s 1 s 2 +(s 0 s 1 +s 0 s 1 +s 0 s 1 )s 2 ) = ((s 0 s 1 )s 2 +(s 0 +s 1 )s 2 ) = (F NOR (s 0,s 1 )s 2 +F NOR (s 0,s 1 )s 2 ) (4.11) For a XOR (exclusive-or) gate: U(s 0,s 1,s 2 ) = ((s 0 s 1 +s 0 s 1 )s 2 +(s 0 s 1 +s 0 s 1 )s 2 ) = (F XOR (s 0,s 1 )s 2 +F XOR (s 0,s 1 )s 2 ) (4.12)

59 38 CENT-MRF The expression of the energy function for a general logic combinational function can be straightforwardly given as U comb (s 0,s 1,...,s n 1,s n ) = (F comb (s 0,s 1,...,s n 1 )s n +F comb (s 0,s 1,...,s n 1 )s n ) where: F comb (s 0,s 1,...,s n 1 ) describes the logic combinational function, (4.13) s 0,s 1,...,s n 1 present the input signals, and s n is the output signal of the gate. Based on expression(4.13), the general CENT-MRF structure for a logic combinational function is obtained as Figure 4.6, where: T comb stands for the target logic combinational circuit, Inv represents a logic inverter, x 0,...,x n 1 are the input signals, and x n,x n are the complementary output signals. The proposed CENT-MRF structure implementation for a NAND gate is presented in Figure 4.7. Supposing that an inverter requires 2 transistors and a NAND gate requires 4 transistors, the area overhead of the proposed structure is only 10 transistors. Compared withmrfnandgate (Figure4.3) andmas MRFNANDgate (Figure 4.5), theproposed noise-tolerant NAND gate reduces the number of transistors from 60 to 14 (a 76.67% reduction) and from 28 to 14 (a 50% reduction), respectively. Note that this overhead is constant and independent of the target logical function T comb. Xn X0... Xn-1 Tcomb Inv Feedback Connector Xn Figure 4.6: The proposed CENT-MRF circuit design for a general logic combinational function. 4.3 Noise-immunity Simulation Results of Different Design Structures Quantifying the Noise-immunity In order to quantify the noise-immunity of different design circuits, the Kullback-Leibler distance(kld)[102] is adopted. It quantifies the similarity of two different signals through

60 4.3 Noise-immunity Simulation Results of Different Design Structures 39 NAND X NAND NOT NAND Figure 4.7: The proposed CENT-MRF circuit design for a two-input NAND gate. The two inputs are x 0, x 1 and the output is x 2. comparing the discrepancy between the signal probabilities P real and P ideal. Here P real is the signal probability of the actual output, and P ideal is the signal probability of an ideal output. KLD is defined as (4.14), where states specify the logic states of a signal. KLD(S ideal,s real ) = ( ) Pideal P ideal log 2 (4.14) P real states For a output signal of a logic gate or a circuit with two states 0 and 1, KLD can be given in (4.15), where P ideal0, P real0 are the probabilities of signal 0 and P ideal1, P real1 are the probabilities of signal 1. ( ) Pideal0 KLD(S ideal,s real ) = P ideal0 log 2 P real0 +P ideal1 log 2 ( Pideal1 P real1 ) (4.15) It is easy to calculate the ideal signal probabilities of a logic gate or a circuit from its truth table. For the actual circuit, with its output signal probability contaminated by the noise, the output signal at discrete points are sampled and evaluate its signal probabilities. According to the Nyquist Shannon sampling theorem [103] [104], the Nyquist rate should be at least two times higher than the highest signal frequency. In ours simulations, the smallest time period of input signals is 0.5 us and the discrete points are sampled every 1 ns. This means the sampling rate is = 500 times higher than the highest signal 10 9 frequency. Thus these sampled discrete points can accurately represent the original signal. The smaller the KLD is, the more similar these two signals are. When KLD equals to 0, the actual output is treated as ideal Simulation Results (SPICE) In this work, several logic gates using the proposed CENT-MRF structure have been simulated. The simulations were realized in SPICE using the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [5] at 100 C. The supply voltage was set to V dd = 0.15V, and the threshold voltage was set to 0.2V for NMOS and 0.22V for PMOS. A Gaussian white noise with the 60mV root mean square (RMS) standard deviation was generated and added to the input signal, just the same as [26] and [28]. Figure 4.8 illustrates the simulation process. Because of the limited space, only the simulation results of a two-input NAND gate is presented in Figure 4.9.

61 40 CENT-MRF Traditional CMOS gate Output signal Input signal + MAS_MRF CMOS gate Output signal' Gaussian white noise Proposed_MRF CMOS gate Output signal'' Figure 4.8: The simulation process of a general logic combinational circuit. IN 1 (V) IN 2 (V) Traditional(V) MAS_MRF(v) CENT_MRF(V) Time(ns) Figure 4.9: The simulation result of a two-input NAND gate (from top to the bottom): the two noisy input signals, the output signal of traditional logic NAND, the output signal of MAS MRF NAND and the output signal of our proposed MRF NAND Simulation Results (SPECTRE) Spectre simulator has been used for simulations of basic logic gates as well as more complex logic combinational functions such as a one-bit full-adder (FA), a four-bit Ripple Carry Adder (RCA) and a (8, 4) Hamming Decoder to compare the noise-immunity of different design structures. We used the low threshold voltage and low power PMOS (plvtlp) and NMOS (nlvtlp) transistors of ST 65nm library. The supply voltage of the gates is 1.2V and the temperature is 25 C. Different input signals with different signal-noise-ratio (SNR)

62 4.3 Noise-immunity Simulation Results of Different Design Structures 41 Table 4.2: Transistor numbers for different bench circuits Bench circuits MRF Master and Slave MRF Proposed CENT-MRF Transistor Number Reduction [26] [29] [26] [29] 2-input NAND % 50% 3-input NAND % 52.9% 4-input NAND % 55% 5-input NAND % 56.5% (8, 4) Hamming Decoder % 33.3% 1-bit full-adder % 50% 4-bit RCA % 50% were simulated and KLDs of output signal were quantified. If there were more than one output in the circuit, the output signal of deepest-path was treated as the representation. The simulation results are shown in Figure 4.10 to Figure Table 4.2 shows the comparison of the transistor number for different bench circuits KLD(log) Traditional MAS_MRF CENT_MRF SNR(dB) Figure 4.10: The KLDs of different design structures of a two-input NAND gate KLD(log) Traditional MAS_MRF CENT_MRF SNR(dB) Figure 4.11: The KLDs of different design structures of a one-bit FA.

63 42 CENT-MRF KLD(log) Traditional MAS_MRF CENT_MRF SNR(dB) Figure 4.12: The KLDs of different design structures of a four-bit RCA KLD(log) Traditional MAS_MRF CENT_MRF SNR(dB) Figure 4.13: The KLDs of different design structures of a two-input XOR gate. 4.4 Discussions and Conclusions This chapter proposed a general cost-effective noise-tolerant circuit structure based on Markov Random Field. It is a general design approach easy to implement for all logic combinational functions. Simulations were realized with the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [5] and ST 65nm CMOS models. From Figure 4.9 to Figure 4.14 and Table 4.2, it can be concluded that proposed CENT-MRF design structure can obtain nearly the same or even better noise-immunity but with less area penalty. Compared with original MAS MRF, the area cost can be reduced 50% for a single two-input NAND gate, 50% for a RCA and 33.3% for a (8, 4) Hamming Decoder.

64 4.4 Discussions and Conclusions KLD(log) Traditional MAS_MRF CENT_MRF SNR(dB) Figure 4.14: The KLDs of different design structures of (8, 4) Hamming Decoder.

65 44 CENT-MRF

66 Chapter 5 Reliability Analysis of Combinational Circuits with the Influences of Noise and Single-Event Transients Traditionally, the reliability analysis of combinational circuits only takes account of the influence of SETs or thermal noise while the soft error in combinational circuits is a combination of both SETs and thermal noise. In this chapter, a model to analyze the reliability induced by both SETs and noise of CENT-MRF is set up. The mathematical conditions are derived, on which SET robustness and noise-immunity of CENT-MRF can be improved at the same time. Simulation methods and results are also presented to verify these mathematical restrictions. Finally, conclusions are outlined. 5.1 Reliability Analysis Model of CENT-MRF Modeling the Noise Analysis Many noise sources exist in electronic circuits, e.g. thermal noise, interconnect noise and crosstalk noise. These noise sources could be aggregated at the output or the input of a logic gate or circuit [105] [106]. Some authors have proposed a model as shown in Figure 5.1 [107,108]. In this model, the noise added to the output of the signal is assumed to estimate the impact of the noise of all the transistors in the module. If the noise is logic 1, the operation exclusive-or forces the output of the module to be inversed (O = Noise O). However, this model just takes account of the effect of noise. With dimension scaling, the transistors are also prone to transient faults induced by radiation (α-particle, cosmic rays, neutrons, and etc.). Noise Module O O ' Output Figure 5.1: The noise model. For the sake of simplicity, denote the reliability induced only by SETs as RS. And the reliability induced by both SETs and noise as RSN. Assume that the RS of the module in Figure 5.1 is q, and the probability that the noise obtains logic 1 is P(N = 1) = K. Thus

67 46 Analysis of Noise and SETs the RSN of the module is given as (5.1): R = q(1 K)+(1 q)k (5.1) We consider a module operating in a noisy environment, then suffering of the noise introduced in the input signal. The noise model of this case is described in Figure 5.2. Figure 5.2: The noise model with noisy input signal. Denote the probabilities of noise N 1 and N 2 obtaining logic 1 as P(N 1 = 1) = K 1 and P(N 2 = 1) = K 2. Assume the RS of the module is q. Thus the RSN of this module is give as (5.2), where N 3 stands to the noise as the output of N 1 N 2. P(co) = q[k 1 K 2 +(1 K 1 )(1 K 2 )] +(1 q)[k 1 (1 K 2 )+(1 K 1 )K 2 ] = q[p(n 1 N 2 = 0)] +(1 q)[p(n 1 N 2 = 1)] = q[p(n 3 = 0)]+(1 q)[p(n 3 = 1)] (5.2) Modeling the Noise Analysis of CENT-MRF Structures In a CENT-MRF structure, there are two modules: the target circuit and the noise-immune module. Figure 5.3 illustrates the noise model of CENT-MRF. N 1 and N 2 represent the noise generated by the target circuit and the noise-immune module, respectively. Denote the probabilities of N 1 and N 2 attaining logic 1 as P(N 1 = 1) = P 1 and P(N 2 = 1) = P 2. Figure 5.3: The noise model of CENT-MRF. According to equation (5.2), the model shown in Figure 5.4 can be utilized to represent the noise model of a CENT-MRF. Notice that N 3 = N 1 N 2. Denote the probability of N 3 attaining logic 1 as P(N 3 = 1) = P 3, and let be the equality (5.3). Therefore, the RSN is given as (5.4) while the RSN of the original target circuit is described as (5.5). P 3 = P 1 (1 P 2 )+P 2 (1 P 1 ) = P 1 +P 2 2P 1 P 2 (5.3) R CENT MRF = q 1 q 2 (1 P 3 )+(1 q 1 q 2 )P 3 = q 1 q 2 +P 3 (1 2q 1 q 2 ) (5.4)

68 5.2 Simulations With Hspice and Matlab 47 q1 q2 N3 Tc NI Figure 5.4: The equivalent noise model of CENT-MRF. T c represents the target circuit and NI stands for the noise-immune module. q 1 and q 2 are the reliabilities respectively. N 3 is the equivalent noise. R Tc = q 1 (1 P 1 )+(1 q 1 )P 1 (5.5) Here the R CENT MRF stands for the RSN of the CENT MRF and the R Tc is the RSN of the original target circuit. We have already certificated that our previous CENT M RF design structure can improve the noise-tolerant ability of the original circuit [109]. But the reliability improvement is not taken into account of, or the reliability improvement conditions. Thus, the aim here is to obtain the conditions satisfying R CENT MRF R Tc. The mathematical derivations are given in Appendix A.1. As a conclusion, the constraints for the reliability enhancement of CENT-MRF structures can be synthesized as shown in Table 5.1. Table 5.1: Constraints of reliability improvement for CENT-MRF Case Constraints q 1 = q 2 = 1 P q 2 = 1,q 1 < 1 2 P q 2 = 1,q P q 1 < 1 2q 2, 1 2 < q 2 < 1 and P 1 < 1 2 P 2 q 1(1 q 2 ) 1 2q 1 q 2 q 1 1,0 < q and P 1 < 1 2 P 2 q 1(1 q 2 ) 1 2q 1 q 2 q 1 < 1 2q 2, 1 2 < q 2 < 1 and P 1 > 1 2 P 2 q 1(1 q 2 ) 1 2q 1 q 2 q 1 1,0 < q and P 1 > 1 2 P 2 q 1(1 q 2 ) 1 2q 1 q 2 1 2q 2 < q 1 1, 1 2 q 2 < 1 and P 1 < 1 2 P 2 q 1(1 q 2 ) 1 2q 1 q 2 1 2q 2 < q 1 1, 1 2 q 2 < 1 and P 1 > 1 2 P 2 q 1(1 q 2 ) 1 2q 1 q Simulations With Hspice and Matlab This section focuses on the validation of the mathematical conclusions obtained in Section 6.2. For this purpose, a mixed simulation model based on Matlab and Hspice have been

69 48 Analysis of Noise and SETs set up. With Hspice, the noise sources of the target circuits can be achieved and consequently obtain the probability of the noise being logic 1. Matlab is utilized to simulate the probabilistic behavior of combinational circuits (suffering the SETs), which are designed with the probabilistic logic gates as described in [110] Simulation Based on Hspice For Hspice simulations, the CMOS devices are modeled according to Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [5]. The noise sources coupled to the output of gates can be modeled as Gaussian white noises with zero mean and standard deviation σ. It is believed that this kind of noise model can represent the inherent noise in the transistors of future technologies [107] [2]. A Gaussian white noise with zero mean and a standard deviation σ is taked to mimic the inherent noise. In order to verify our conclusions, different standard deviations σ are simulated. In a general case, gates or modules are the internal parts of a combinational circuit. Thus the noisy input(s) are required to simulate the RS and RSN. The Gussian white noise is specified with zero mean and a standard deviation 0.6v. Figure 5.5 describes the simulation process to obtain the probability of the noise being logic 1 with Hspice. Figure 5.5: Simulation scheme: Hspice Simulation Based on Matlab Based on the probabilistic logic gate model proposed in [110], the target circuit and the noise-immune (NI) module are constructed with Matlab. Thanks to the probability of noise being logic 1 supplied by Hspice experiments, the probabilistic behavior of the CENT-MRF circuit can be simulated and its probabilistic output can be obtained. Notice that Monte Carlo Methodology [111] (MCM) is utilized to calculate the statistical result of the CENT-MRF circuit. Figure 5.6 illustrates the simulation process Simulation Results For simpleness but without loss of generality, the simulation results of CENT-MRF where the target circuit is a Full Adder (FA) is only presented. Figure 5.7 illustrates the probability of noise being logic 1 of the FA and the NI module, which means that the probability of noise taking effect, or the probability of

70 5.2 Simulations With Hspice and Matlab 49 Figure 5.6: Simulation scheme: Matlab. output being reversed. It can be noticed that many standard deviations of the noise have been simulated, from 0.1V to 0.6V.Also the lowest supply voltage of 65nm BPTM CMOS, i.e. 0.8V, is set to simulate the worst case. In order to verify our derivations, two pairs of P 1 and P 2 are chosen as the input parameters for the Matlab simulation process. One pair is P 1 = ,P 2 = to simulate the case when P and the other one is P 1 = ,P 2 = to simulate the case when P For the RS of NI, the general case q 2 = 0.95 is set. Here the P 1 is the probability of noise being logic 1 for FA and P 2 is the probability of noise being logic 1 for NI. q 1 and q 2 are the probabilities sole to SETs of FA and NI correspondingly. The simulation results are illustrated in Figure 5.8 and Figure Probability of noise being logic Sum of FullAdder Cout of FullAdder NI Different rms of noise (V) Figure 5.7: The probability of noise being logic 1 of a FA and NI module. From Figure 5.7, Figure 5.8 what can be pointed out is: The larger the noise deviation is, the larger error probability a circuit will obtain. In other words, with the dimension and the supply voltage scaling, the noise will be more probable to be logic 1 and reverse the original signal. When the P 1 1 2, and 1 2q 2 < q 1 1, 1 2 q 2 < 1, the RSN of CENT-MRF FA is larger than that of FA, meaning that the noise-immunity and the reliability of both SETs and noise can be enhanced at the same time.

71 50 Analysis of Noise and SETs Reliabilities to both SETs and noise Reliabilities of CENT_MRF_FA Reliabilities of FA Different reliabilities (sole to SETs) of Full Adder Figure 5.8: The simulated RSN for different reliability (sole to SETs) of FA with P Reliabilities to both SETs and noise Reliabilities of CENT_MRF_FA Reliabilities of FA Different reliabilities (sole to SETs) of Full Adder (FA) Figure 5.9: The simulated RSN for different reliability (sole to SETs) of FA with P When P 1 1 2, and q 1 < 1 2q 2, 1 2 q 2 < 1, the RSN of CENT-MRF FA is lower than that of FA, meaning that only its noise-immunity can be improved at this case. From Figure 5.9 what can be concluded is: When q 1 < 1 2q 2, 1 2 < q 2 < 1 and P 1 < 1 2, the RSN of CENT-MRF FA is improved. When q 1 > 1 2q 2, the RSN of CENT-MRF FA will be less than that of FA. In Figure 5.8 and Figure 5.9, the reliability to both SETs and noise of FA is a straight line, or linearly to the reliability sole to SETS, which is the result of (5.5) with a given P Conclusions This chapter proposed a model to analyze the reliability concerning both the SETs and the noise of logic functions. It focused on CENT-MRF structures which have proved to

72 5.3 Conclusions 51 be a cost-effective solution for noise immunity. A series of mathematical conditions has been derived allowing the designers to achieve the reliability enhancement and the noiseimmunity improvement. A mixed simulation based on Hspice and Matlab was set up and the results validated the proposed derivations.

73 52 Analysis of Noise and SETs

74 Chapter 6 Reliability Analysis of Reed-Solomon Decoder Reed-Solomon (RS) codes [112] are a class of error-corecting codes based on Galois Field GF(2 m ) which has been applied in many fields [113], [114]. With the dimension shrinking and supply voltage decreasing, the gates in CMOS devices based on deep submicron technologies (DSM) [115] become probabilistic [116] and hence the corresponding RS decoder is no longer deterministic. Thus, the relilability of RS decoder has become an important design criterion. Generally, the basic method to improve the reliability of a CMOS device is adding redundancy, which needs us to determine the critical blocks in order to attain a tradeoff between the reliability and the cost of the device. Therefore, to find out the critical blocks which degrade the reliability of RS decoder dramatically is a key issue for the designer. This chapter establishes a model to simulate the behavior of probabilistic RS decoder. The preliminaries on RS decoder are firstly introduced. Then the model to simulate the probabilistic RS decoder is presented, which also includes the models of probabilistic gates and the arithmetic opeartions on GF(2 m ). After that, it discusses the simulation process and the corresponding results based on Monte Carlo Method [111]. Finally, conclusions are outlined. 6.1 Preliminaries on RS Decoder Let the representation of the RS code over Galois Field GF(2 m ) be RS(n,k), where n = 2 m 1 is the codeword length and k is the message length of m bit symbols. Assume that the encoded codeword is denoted as c = [c 0 c 1... c n 1 ], and the error vector is e = [e 0 e 1... e n 1 ]. Thenthereceived codeat thersdecoder is r = c+e = [r 0 r 1... r n 1 ]. The minimum distance of RS(n,k) is d = n k+1, and the number of errors the RS(n,k) can detect and erase is d 1 [117]. Figure 6.1 illustrates the decoding process of the RS decoder structure employed in this paper, as most of the RS decoders nowadays. In Figure 6.1, the SynCal(SC) is the module to calculate the syndromes and the BM represents the module to attain the error locator polynomial. The decoder employes the module Chien to find the error locations and the module Forney to get the error values. R represents the received RS codes and S i, U i, E l and E v are outputing results of each module. For the SC module, assume that α is a primitive element of GF(2 m ). The equation to find the syndromes S i of the received codes is (6.1), where S i (i = 1,...,d 1) are the

75 54 Reliability Analysis of Reed-Solomon Decoder Inputs R i SynCal S i BM Outputs Outputs E E v l S i U i Forney El Chien Figure 6.1: The strcture of the RS Decoder syndromes calculated for the received codes. S i = S(α i ) = e(α i ) = r(α i ) c(α i ) = r(α i ),i = 1,...,d 1 (6.1) The BM [118] module takes the s i as inputs and calculates the error locator polynomial, whose roots (or the roots reciprocals) are the error locations. The error locator polynomial is illustrated in (6.2), where U i,i = 0,...,d 1 are coefficients of the error locator polynomial. U(x) = u 0 +u 1 (x)+... +u d 1 (x d 1 ) (6.2) After obtaining the error locator polynomial, the module Chien uses U i,i = 0,...,d 1 as its inputs and attains the error locations E l of the codewords. The Chien search algorithm [119] is widely used to find the roots. Elements of GF(2 m ) which can make the error locator polynomial be 0 are the roots. The F orney module serves to calculate the error values at the detected locations with Forney algorithm [120]. The algorithm is described with equations (6.3) to (6.5). Y i = Ω(x i) U (x i ) (6.3) U (x i ) = V iu i x i (6.4) i=1 Ω(x i ) = (U(x i )S(x i ))mod(x d 1 ) (6.5) In above equations((6.3) to (6.5)), x i is the root of the error locator polynomial. U (x i ) is the formal derivative polynomial of the error locator polynomial U(x i ), and V is the number of error locator polynomial. After attaining the error locations and their corresponding error values, the modified or error-erasured codewords can be achieved by adding the error values to the received codes at the error locations. 6.2 Probabilistic Modeling Process To analyze the reliability of the Reed Solomon decoder, a reliability anlysis model which can simulate the behavior of probabilistic gates and the arithmetic operations of Galois Field GF(2 m ) is set up firstly.

76 6.3 Simulation Results Modeling Probabilistic Gates For simplity, the probabilistic gate modeling just takes the basic gates in the decoding process into consideration: AND, OR, XOR, NOT and MUTIPLEXER. Figure 6.2 presents the model to simulate the probabilistic gates. The models of probabilistic gates have the same inputs as the ideal gate, while the probabilistic gate may change output to its opposite (0 1, or 1 0) with a probability q = 1 p, where p is the gate reliability. In this figure, the result of Ideal gate will be modified by the module Prob Modify under the condition that whether the output of module RandInt m is larger than the gate reliability p. If m > p, the result of Ideal gate will change to its opposite, otherwise it will remain the same. Probabilistic Logic Gate I IdealGate 0 or 1 O Rand m Com 0 or 1 Figure 6.2: The Probabilistic Gate Model The simulation results of the probabilistic gate is showed in Section Modeling Arithmetic Operations of Galois Field The arithmetic operations of Galois Field are based on the operations of finite field. As the RS decoders are application-related, it is impractical to analyze every decoder s reliability. However, most of them have the same structure as shown in Figure 6.1. For a simplity but without losing generality, this paper focuses on a RS(7, 3) decoder, based on Galois Field GF(2 3 ), which can analyze seven message symbols in one time and can detect and erase at most (7 3)/2 = 2 errors. For the Galois Field based on the primitive 2, the arithmetic operations can be converted to bit-to-bit opeartions AND, OR or XOR. Thus in order to model the arithmetic operations of Galois Field GF(2 3 ), the operands are converted to bits first of all. Then the modeling of the probabilistic gates can be employed to realize the bit-to-bit operations. The simulation results of the arithmetic operations are also shown in Section Simulation Results Four parts will be discussed in this section: brief of Monte Carlo Method, simulations of the probabilistic gates, simulations of the arithmetic operation of the Galois Field and simulations of the modules of the RS decoder RS(7,3). All the simulations are based on the Monte Carlo Method Brief of Monte Carlo Method Monte Carlo Method is a statistical method proposed in paper [111], which is based on the repeated random inputs, the physical model needed to simulate and the statistical analysis oftheoutputs.theaccuracyoftheanalysisresultdependsonthenumberofrandominputs and the preciseness of physical model. For the reliability analysis of RS decoder, with the probabilistic gates and arithmetic opeartions, the result is also probabilistic with the same

77 56 Reliability Analysis of Reed-Solomon Decoder random input. But when the number of random inputs is large enough, the statistical result of rightly decoded codes can evaluate the reliability of the RS decoder Simulations of the Probabilistic Gates To simulate the probabilistic gates, the Monte Carlo Method generates operands (or operands pairs) as random inputs. Then the modeled probabilistic gate calculates the results of these operands with the gate reliability of p. The reliability of the modeled probabilistic gate is calculated by ((6.6)) R = N rpg==rig N st (6.6) where rpg represents the result of probabilistic gate, rig represents the result of ideal gate, N is the number and st represents the simulation times. The simulation result is illustrated in Figure 6.3. It showes that the reliabilities of modeled probabilistic gates are close to the ideal gate probabilities, which means the modeled probabilistic gates can be used to simulate the ideal probabilistic gates. The Simulated Gate Reliability The Simulation of the Probabilistic Gates(20000) Gate And Gate Or Gate Not Gate Xor Gate Mul The Ideal gate reliability Figure 6.3: The Simulation Results of Probabilistic Gates ( times) Simulations of the Arithmetic Operations in Galois Field In order to simulate arithmetic operations in Galois Field, the Monte Carlo Method also produced operands (or operands pairs). These operands are operated by the modeled arithmetic operations and the ideal arithemtic operations sequentially. The reliabilities of the modeled arithmetic operations are calculated in (6.7), where R pao represents the reliability of the probabilistic arithmetic opeartions, N ro represents the number of right operated results and N st is the number of simulation times. R pao = N ro N st (6.7)

78 6.3 Simulation Results 57 The simulation result is shown in Figure 6.4. Because the addition operation is the same as the subtraction operation in Galois Field and the inverse operation can be realized with the multiplication, only the addition and multiplication arithmetic operations are simulated in this paper. 1 The Simulation of Arithmetic Operations(20000) The Simulated Operations Reliability Addition Multiplication The gate reliability Figure 6.4: The Simulation Results of Arithmetic Operations ( times) From above simulation results illustrated in Figure 6.4, it can be concluded that the multiplication arithmetic operation influences the reliability of the RS decoder much more than the addition. If the number of the multiplication operations is decreased, the reliability of the decoder can be improved Simulations of the Decoding Modules For the RS(7, 3) decoder, the messages contain three 3-bit symbols and the number of codes is = 256. In the encoding process, the three message symbols are encoded with another four symbols to construct the 7-symbol codeword. So the decoder can detect and erase at most (7 3)/2 = 2 errors. The simulation process is shown in Figure 6.5. Based on the Monte Carlo Method, the random producer generates random RS codes, each of which may contain 0, 1 or 2 errors. Then each of these random RS codes with errors is decoded by the probabilistic RS decoder (represented in dashed line) and the ideal RS decoder respectively. With the gate reliability p ( p = 1 ǫ, ǫ is the gate error probability in the range of [0, 10 1 ]) in the range of [0.9, 1], the output results of each module are compared with the ideal decoded results, which can be seen in Figure 6.6. Simulation results of different modules in the RS decoder show that: In the gate reliability range of 0.9 to 0.98, the reliability of BM module and Forney module nearly do not change. So the reliabilities of these two modules can not be improved in this gate reliability range; In the gate reliability range of 0.9 to 0.965, the SC module has lowest reliability of all the four modules, while if the reliability is higher than 0.965, the BM becomes the most unreliable module;

79 58 Reliability Analysis of Reed-Solomon Decoder Random Codes insert errors RandomErrNum RandomErrValue SynCal BM Chien Forney compare compare compare compare SynCal BM Chien Forney P Decoded Codes I Decoded Codes Figure 6.5: The Simulation of the decoding process The corresponding modules Reliability Modules reliability with different gate reliabilities (20000 times) SC Module Reliability BM Module Reliability Chien Module Reliability Forney Module Reliability The gate reliability Figure 6.6: The Simulation Reliabilities of Different Modules ( times) Another simulation of the decoding process is applied to evaluate the influences of these four modules. The evaluation process of influences sets only one module to be probabilistic each time to calculate the reliability of the decoder. The results are shown in Figure 6.7. From the simulation results shown in Figure 6.7, it can be concluded that when the gate reliability is in the range of 0.9 to 0.98, the bottleneck module of the decoder is the syndromes calculation module. When the gate reliability is higher than 0.98, the BM module becomes the bottleneck module. Forthmore, in the gate reliability range of 0.9 to 0.96, with the gate more reliable, the influences of the module SC, BM and Forney are almost the same, which means that it is impossible to improve the RS decoder reliability

80 6.4 Conclusions 59 The RS Decoder Reliability The impact of modules with different gate reliability(20000 times) 1 SC probabilistic BM probabilistic Chien probabilistic Forney probabilistic The gate reliability Figure 6.7: The impact of Different Modules to the decoder ( times) during this gate range only by making these three modules more reliable. 6.4 Conclusions The simulation results illustrate that several aspects should be considered to improve the RS decoder reliability. Firstly, the number of the multiplication arithmetic operations should be decreased for higher reliability. Secondly, from the individual simulation of different modules reliability and the evaluation of influences of these modules, the syndromes calculation module plays a dominant role in the range of gate reliability from 0.9 to At last, the reliabilities of BM module and Forney module and their influences almost do not change in the range of gate reliability of 0.9 to As a result, there is no necessity to make these two modules more reliable in order to improve the decoder reliability.

81 60 Reliability Analysis of Reed-Solomon Decoder

82 Chapter 7 Conclusions and Perspectives 7.1 Conclusions With the dimension scaling of CMOS, the digital circuits are more prone to various perturbations, such as high-energy neutrons, the cosmic rays, and the increasing reduction of noise margin. The impacts of these perturbations make the devices in logic circuits not deterministic but probabilistic. The accumulative effect of the probabilistic devices results in probabilistic logic circuits. In other words, the output of a logic gate or a logic combinational circuit has a probability to maintain the complementary bit value of its expected logic one. This kind of logic circuits are denoted as probabilistic circuits, and the reliability of these circuits has become an important issue in ICs design. In particular, the evaluation methodologies and enhancement techniques of reliability have been the research interest for decades. Thus this thesis first reviewed the basic definitions and concepts related to the issue of reliability in combinational logic circuits: the increasing SER on the ground-level, methods to evaluate the reliability of a combinational circuit, design structures to enhance reliability, etc.. For reliability evaluation methodologies, many models have been proposed, e.g., PTM, SPR, CPM and PGM. These models have different characteristics, scalability, speed, accuracy, memory consumption, etc.. This thesis described the PTM methodology and its drawbacks. A novel methodology based on PTM, denoted as ECPTM, was proposed with its time complexity and memory usage theoretically. Some benchmark circuits were utilized to verify the performances of the proposed ECPTM against traditional PTM. The results showed that the proposed method can efficiently reduce the time consumption and memory usage. For reliability enhancement techniques, this work pointed out that the traditional fault-tolerant design methodologies based on hardware redundancy, e.g. Triple-Modular- Redundancy (TMR) [17] and Cascade TMR (CTMR) [18], are not capable to obtain noise-immunity because of the intrinsic random nature of noise. A general cost-effective noise-tolerant circuit structure based on Markov Random Field (denoted as CENT-MRF) was proposed. It is a general design approach easy to implement for all logic combinational functions. Simulations were realized with the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [5] and ST 65nm CMOS models. From the simulation results, it can be concluded that proposed CENT-MRF design structure can obtain nearly the same or even better noise-immunity but with less area penalty. Compared with original MAS MRF, the area cost can be reduced 50% for a single two-input NAND gate, 50% for a RCA and 33.3% for a (8, 4) Hamming Decoder. The traditional reliability techniques (TMR, CTMR, etc.) or the methodologies based on MRF, only took account of the impacts of SETs or noise while the soft error in logic

83 62 Conclusions and Perspectives circuits is a combination of both SETsand thermal noise. In this thesis, a model to analyse the reliability concerning both the SETs and the noise of logic functions was proposed. It focused on CENT-MRF structures which was proved to be a cost-effective solution for noise immunity. A series of mathematical conditions were derived allowing the designers to achieve the reliability enhancement and the noise-immunity improvement at the same time. A mixed simulation based on Hspice and Matlab was set up and the results validated the proposed derivations. The thesis furthermore studied a RS decoder as an example to describe the issue of reliability. It assumed that all the logic gates in the decoder suffered the impacts of radiation-induced and noise-induced soft error at the same time and had the same error probability. After that a model was set up to simulate the probabilistic behaviour of the logic gates, with which the whole circuit of probabilistic RS decoder was constructed. Some simulations were realized with Matlab and the simulation results illustrated that several aspects should be considered to improve the RS decoder reliability. Firstly, the number of the multiplication arithmetic operations should be decreased for higher reliability. Secondly, from the individual simulation of different modules reliability and the evaluation of influences of these modules, the syndromes calculation module played a dominant role in the range of gate reliability from 0.9 to At last, the reliabilities of BM module and Forney module and their influences almost did not change in the range of gate reliability of 0.9 to As a result, there is no necessity to make these two modules more reliable in order to improve the decoder reliability. 7.2 Contributions The main contributions of this thesis are as follows: Reliability analysis of a Reed-Solomon decoder, presented at IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Reliability analysis of combinational circuits with the influences of noise and singleevent transients, presented at Detect and Fault tolerance in VLSI and Nanotechnology Systems (DFTS) A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS circuits, presented at IEEE Eurocon A model to simulate the behavior of probabilistic gates, presented at Journées Nationales du Réseau Doctoral en Micro-nanoélectronique (JNRDM) Efficient computation of combinational circuits reliability based on probabilistic transfer matrix, presented at International Conference on IC Design and Technology (ICICDT) Perspectives For the reliability evaluation methodologies, the scalability of ECPTM has not been verified with large circuits. With the inherent limits of PTM, it is unsuitable to implement ECPTM to large circuits, which means that the ECPTM should be optimized and novel methodologies should be proposed. For the noise-tolerant circuit design CENT-MRF, the future work will focus on the structure for multiple-output gates and the mapping optimization for large circuits, especially for selective implementation. Other design criteria should be taken into account, e.g.

84 7.3 Perspectives 63 the time delay, the power consumption and the transistor threshold voltage variation. Also the bit-error-rate (BER) of some application-related circuits should be tested to quantify the noise-immunity more accurately. Furthermore, for the model proposed to cope with impacts of SETs and noise at the same time, more precise noise models should be taken into account. Meanwhile, a methodology for fast decision also needs our efforts.

85 64 Conclusions and Perspectives

86 AppendixA Mathematical Derivations.1 The mathematical derivations This following paragraphs present the mathematical derivations for expressions in Table 5.1. Notice the aim is to obtain the conditions satisfying R CENT MRF R Tc, or equivalently, satisfying (1). q 1q 2 +P 3(1 2q 1q 2) q 1(1 P 1)+(1 q 1)P 1 q 1q 2 +(P 1 +P 2 2P 1P 2)(1 2q 1q 2) q 1(1 P 1)+(1 q 1)P 1 (1) In order to do this, different cases should be taken into account. When q 1 = q 2 = 1, (1) can be simplified as (2): q 1q 2 +P 3(1 2q 1q 2) q 1(1 P 1)+(1 q 1)P 1 1 P 3 1 P 1 P 1 P 3 P 1 P 1 +P 2 2P 1P 2 (2) P When q 2 = 1 and q 1 < 1, (1) can be simplified as (3): q 1q 2 +P 3(1 2q 1q 2) q 1(1 P 1)+(1 q 1)P 1 q 1 +P 3(1 2q 1) q 1(1 P 1)+(1 q 1)P 1 P 3(1 2q 1) P 1(1 2q 1) (P 1 +P 2 2P 1P 2)(1 2q 1) P 1(1 2q 1) (3) If q 2 = 1,q 1 < 1, (3) produces (4): 2 (P 1 +P 2 2P 1P 2)(1 2q 1) P 1(1 2q 1) P 2 2P 1P 2 0 (4) P If q 2 = 1,q 1 1, (3) produces (5): 2 (P 1 +P 2 2P 1P 2)(1 2q 1) P 1(1 2q 1) P 2 2P 1P 2 0 (5) P 1 1 2

87 66 Mathematical Derivations When q 2 < 1, (1) can be simplified to (6). And when 1 2q 1q 2 > 0,q 2 < 1, i.e., q 1 < 1 2q 2,q 2 < 1, (1) can be simplified to (7). q 1q 2 +P 3(1 2q 1q 2) q 1(1 P 1)+(1 q 1)P 1 P 3(1 2q 1q 2) q 1 2q 1P 1 +P 1 q 1q 2 (P 1 +P 2 2P 1P 2)(1 2q 1q 2) q 1 2q 1P 1 +P 1 q 1q 2 (6) (P 1 +P 2 2P 1P 2)(1 2q 1q 2) q 1 2q 1P 1 +P 1 q 1q 2 P 2(1 2P 1) q1 2q1P1 +P1 q1q2 1 2q 1q 2 P 1 q1 2q1P1 q1q2 +2P1q1q2 P 2(1 2P 1) 1 2q 1q 2 P 2(1 2P 1) q1(1 2P1)(1 q2) 1 2q 1q 2 (7) If q 1 < 1 2q 2,q 2 < 1 and P 1 < 1, we can conclude (8): 2 Otherwise, if q 1 < 1 2q 2,q 2 < 1 and P 1 > 1, we can conclude (9): 2 P 2 q1(1 q2) 1 2q 1q 2 (8) P 2 q1(1 q2) 1 2q 1q 2 (9) In the same way, conclusions for the case 1 2q 2 < q 1 1,q 2 < 1 can be derived: When 1 2q 2 < q 1 1,q 2 < 1 and P 1 < 1, we get 2 When 1 2q 2 < q 1 1,q 2 < 1 and P 1 > 1, we obtain 2 P 2 q1(1 q2) 1 2q 1q 2 (10) P 2 q1(1 q2) 1 2q 1q 2 (11)

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95 Reliability of probabilistic circuits Kaikai LIU ABSTRACT: This thesis concentrates on the reliability evaluation models and the noise-tolerant circuit design for combinational circuits when CMOS dimension scales down to 65 nm. An efficient reliability analytical evaluation method based on probabilistic transfer matrix (PTM) is proposed for the reductions in time consumption and memory usage. A general noise-tolerant circuit design structure is discussed for obtaining a trade-off between the area and the noise-immunity of the circuits. A model which takes account of the impacts of single event transients and thermal noise is set up to analyse the derivations for reliability enhancement and noise-immunity. KEY-WORDS: Reliability, Probabilistic Transfer Matrix(PTM), Noise-tolerant circuit, CMOS 65nm