九州工業大学学術機関リポジトリ PROCEDURES FOR LOGIC AND ARITHMETIC OPERATIONS WITH DNA MOLECULES. Author(s) Fujiwara, Akihiro; Matsumoto, Kenic

Size: px
Start display at page:

Download "九州工業大学学術機関リポジトリ PROCEDURES FOR LOGIC AND ARITHMETIC OPERATIONS WITH DNA MOLECULES. Author(s) Fujiwara, Akihiro; Matsumoto, Kenic"

Transcription

1 九州工業大学学術機関リポジトリ Title PROCEDURES FOR LOGIC AND ARITHMETIC OPERATIONS WITH DNA MOLECULES Author(s) Fujiwara Akihiro; Matsumoto Kenic Issue Date URL RightsCopyright World Scientific Publis Kyushu Institute of Technology Academic Re

2 International Journal of Foundations of Computer Science c World Scientific Publishing Company PROCEDURES FOR LOGIC AND ARITHMETIC OPERATIONS WITH DNA MOLECULES AKIHIRO FUJIWARA KEN ICHI MATSUMOTO Department of Computer Science and Electronics Kyushu Institute of Technology Kawazu Iizuka Fukuoka JAPAN and WEI CHEN Department of Computer Science Tennessee State University 3500 John A Merrit Blvd Nashville TN37209 U.S.A. Received (received date) Revised (revised date) Communicated by Editor s name ABSTRACT In this paper we consider procedures for logic and arithmetic operations with DNA molecules. We first show a DNA representation of n binary numbers of m bits and propose a procedure to assign the same values for the representation. The representation enables addressing feature and the procedure is applicable to n binary numbers of m bits in O(1) steps in parallel. Next we propose a procedure for logic operations. The procedure enables any boolean operation whose input and output are defined by a truth table and executes different kinds of boolean operations simultaneously for any pair of n binary numbers of m bits in O(1) lab steps using O(mn) DNA strands. Finally we propose a procedure for additions of pairs of two binary numbers. The procedure executes O(n) additions of two m-bit binary numbers in O(1) steps using O(mn) DNA strands. Keywords: DNA computing logic and arithmetic operations 1. Introduction In recentworksforhighperformancecomputing computationwith DNA molecules that is DNA computing has considerable attention as one of non-silicon-based computings. The massive parallelism of DNA molecules enables us to solve combinatorial NP-complete problems which need exponential computation time on a silicon-based computer in a polynomial number of steps. As the first work for DNA computing Adleman[1] presented an idea of solving the Hamiltonian path problem of size n in O(n) steps using DNA molecules. His idea was successfully tested in a lab experiment for a small graph. Lipton[6] showed methods for solving the SAT 1

3 problem of size n in O(n) steps using DNA molecules. There are a number of other works with DNA molecules for combinatorial NP-complete problems. However procedures for primitive operations such as logic or arithmetic operations are needed to apply DNA computing on a wide range of problems. There are some works for primitive operations in DNA computing[ ]. Guarnieri et.al.[3] have proposed the first procedure for an addition of two binary numbers using DNA molecules. The procedure works in O(n) steps using O(n) different DNA molecules for an addition of two n-bit binary numbers. Recently Hug and Schuler[5] have proposed a model for representing and manipulating binary numbers on the DNA chip which allows parallel execution of primitive operations. Their procedure computes an addition of two n-bit binary numbers in O(1) steps using O(n) different DNA molecules. However their procedure allows only one single operation in parallel execution for DNA molecules. In this paper we consider procedures for the primitive operations using DNA molecules with addressing feature. The primitive operations are used on a siliconbased computer with memory addressing that is each variable is stored in a memory location whose size is a constant number of bits and an operation is executed for two memory locations indicated by the addresses. If the addressing feature is used in DNA computing we can execute different operations for different variables stored in DNA strands. We first show a DNA representation of n binary numbers of m bits and propose a procedure to assign the same values for the representation. The representation enables addressing feature and the procedure is applicable to n binary numbers of m bits in O(1) steps in parallel. Next we propose a procedure for logic operations. The procedure enables any boolean operation whose input and output are defined by a truth table and executes different kinds of boolean operations simultaneously for any pair of n binary numbers of m bits in O(1) steps using O(mn) different kinds of DNA strands. Finally we propose a procedure for additions of pairs of two binary numbers. The procedure executes O(n) additions of two m-bit binary numbers in O(1) steps using O(mn) DNA strands. This paper is organized as follows. In Section 2 we give the brief description of the model for DNA computing. In Section 3 we show the DNA representation of binary numbers and propose a basic procedure for the representation. In Section 4 and Section 5 we propose procedures for logic and arithmetic operations respectively. Section 6 concludes the paper. 2. Preliminaries 2.1. DNA strands A set of DNA strands is a key component for DNA computing like a memory module used on a silicon-based computer. A single strand of DNA is defined as a string of four different base nucleotides. Since any kind of single strands can be synthesized using biological methods[7] we assume that each single strand represents 2

4 a symbol over a finite alphabet Σ. A main concept used in DNA computing is Watson-Crick complementarity. We define the alphabet Σ = {σ 0 σ 1...σ m 1 σ 0 σ 1...σ m 1 }wherethesymbols σ i σ i (0 i m 1) are complements. A single strand is a sequence of one or more symbols in Σ. Two single strands form a double strand if and only if the single strands are complements of each other. A double strand with σ i σ i is denoted by [ σi σ i ]. Note that two single strands form a double strand if subsequences of the two single strands are complements. For example let α β be two single strands such that α = σ 0 σ 1 and β = σ 1 σ 0. Then the following two double strands are obtained with α β. [ ] [ σ0 σ 1 σ 1 σ 0 ] σ 0 σ 1 σ 1 σ 0 The strands are stored in a test tube. The following expression denotes a test tube T 1 which stores two single strands σ 0 σ 1 σ 1 σ 0. T 1 = {σ 0 σ 1 σ 1 σ 0 } Also note that we let the set of strands stored in a test tube be a k-multiset. That is each strand has k copies in the test tube where k depends on the lab error in DNA manipulations. We define each strand in a test tube as one unit. For example the following test tube T 2 contains two units of σ 0 σ 1 and three units of σ 1 σ 0. (In this paper we use one unit of a DNA strand only.) T 2 = {σ 0 σ 1 σ 0 σ 1 σ 1 σ 0 σ 1 σ 0 σ 1 σ 0 } 2.2. Computational model for DNA computing A number of theoretical or practical computational models have been proposed for DNA computing[ ]. In this paper we assume a theoretical computational model based on the RDNA model[11] which is an abstract mathematical model for the performance of parallel DNA computation. The model allows the following eight DNA manipulations which are widely used in DNA computing. (1) Merge: Given two test tubes T 1 T 2 Merge(T 1 T 2 ) stores the union T 1 T 2 in T 1. (2) Copy: Given a test tube T 1 Copy(T 1 T 2 ) produces a test tube T 2 with the same contents as T 1. (3) Detect: Given a test tube T Detect(T ) outputs yes if T contains at least one strand otherwise outputs no. (4) Separation: Given a test tube T 1 and a set of strings X Separation(T 1 XT 2 ) removes all single strands containing a string in X from T 1 and produces a test tube T 2 with the removed strands. 3

5 (5) Selection: Given a test tube T 1 andanintegerl Selection(T 1 LT 2 ) removes all strands whose length is L from T 1 and produces a test tube T 2 with the removed strands. (The length of a strand is the number of symbols in the strand.) (6) Cleavage: Given a test tube T and a string [ of two ] symbols σ 0 σ 1 Cleavage(Tσ 0 σ 1 ) σ0 σ cuts each double strand containing 1 in T into two double strands as σ 0 σ 1 follows. [ ] [ ] [ ] α0 σ 0 σ 1 β 0 α0 σ 0 σ1 β 0 α 1 σ 0 σ 1 β 1 α 1 σ 0 σ 1 β 1 It is assumed that Cleavage can only be applied to some specified symbols over the alphabet Σ. (7) Annealing a : Given a test tube T Annealing(T ) produces all feasible double strands from single strands in T. (The produced double strands are still stored in T after Annealing.) (8) Denaturation: Given a test tube T Denaturation(T ) dissociates each double strand in T into two single strands. The above eight manipulations are implemented with a constant number of biological steps for DNA strands[8]. We assume that the complexity of each manipulation is O(1) steps and consider asymptotic complexity of a sequence of the manipulations. In this paper we use all of the above manipulations except for Selection. Table 1 shows an example of the manipulations. 3. Bit representation and value assignment In this section we first describe a DNA representation of binary numbers. Then we consider a basic operation Value Assignment which assigns values to every bit Bit representation We describe the representation of n binary numbers of m bits. In the representation one single strand corresponds to one bit of a binary number. Therefore we use O(mn) single strands to denote n binary numbers. We first define the alphabet Σ used in the representation as follows. Σ = {A 0 A 1...A n 1 B 0 B 1...B m 1 C 0 C 1 D 0 D A 0 A 1...A n 1 B 0 B 1...B m 1 C 1 C 2 D 1 D } In the above alphabet A 0 A 1...A n 1 denote addresses of binary numbers and B 0 B 1...B m 1 denote bit positions in a binary number. C 0 C 1 and D 0 D 1 are the specified symbols cut by Cleavage thatiscleavage(tc 0 C 1 )andcleavage(td 0 D 1 ) a In some papers an operation Ligation is defined to concatenate single strands after Annealing. We assume that Annealing includes Ligation that is Ligation is automatically executed after Annealing inthispaper. 4

6 Table 1: An example of the manipulations manipulation test tube T test tube T test tube T {σ 0 σ 1 σ 0 σ 1 } φ φ σ0 σ Annealing(T ) 1 φ φ σ 0 σ 1 Denaturation(T ) {σ 0 σ 1 σ 0 σ 1 } φ φ Copy(TT ) {σ 0 σ 1 σ 0 σ 1 } {σ 0 σ 1 σ 0 σ 1 } φ σ0 σ Annealing(T ) 1 {σ σ 0 σ 0 σ 1 σ 0 σ 1 } φ ] [ 1 σ0 σ1 Cleavage(Tσ 0 σ 1 ) {σ σ 0 σ 0 σ 1 σ 0 σ 1 } φ 1 Denaturation(T ) {σ 0 σ 1 σ 0 σ 1 } {σ 0 σ 1 σ 0 σ 1 } φ Merge(TT ) {σ 0 σ 1 σ 0 σ 1 σ 0 σ 1 σ 0 σ 1 } Separation(T{σ 0 σ 0 }T ) {σ 1 σ 1 } φ {σ 0 σ 0 σ 1 σ 0 σ 0 σ 1 } Selection(T 1T ) {σ 1 σ 1 } {σ 0 σ 1 σ 0 σ 1 } {σ 0 σ 0 } [ ] [ ] C0 C cut all double strands containing 1 D0 D and 1 in a test tube T respectively. Symbols 0 and 1 are used to denote values of bits and is a special C 0 C 1 D 0 D 1 symbol for Separation. Using the above alphabet a value of a bit whose address and bit position are i and j is represented by a single strand S ij such that S ij = D 1 A i B j C 0 C 1 VD 0 where V = 0 if a value of the bit is 0 otherwise V= 1. We call each S ij a memory strand and use a set of O(mn) different memory strands to denote n binary numbers of m bits. (To overcome the lab error we assume that each memory strand has k copies in the test tube.) 3.2. Value assignment φ φ An input of Value Assignment is a test tube T input strands such that which contains memory T input = {D 1 A i B j C 0 C 1 V ij D 0 0 i n 1 0 j m 1} where V ij {0 1}. An output is also a test tube T output such that T output = {D 1 A i B j C 0 C 1 V D 0 0 i n 1 0 j m 1} 5

7 where V {0 1}. (Note that all memory strands are set to the same value V.) The procedure for Value Assignment consists of two steps. The first step is deletion of values from memory strands and the second step is assignment of values to the strands. In the first and second steps we use auxiliary test tubes T C and T V such that T C = {C 0 C 1 }T V = {C 1 V D 0 C 0 C 1 }. Since DNA strands in tubes T C and T V are independent of addresses or values of memory strands we can prepare them in advance. In addition we use a test tube T tmp to store the strands temporarily. A detailed description of the procedure is presented below. Procedure ValueAssignment V (TestTube T input TestTube T output ) { Step 1: Delete values from memory strands. Merge(T input T C ) Annealing(T input ) Cleavage(T input C 0 C 1 ) Denaturation(T input ) Separation(T input {C 1 C 0 C 1 }T tmp ) Step 2: Assign values to memory strands. Merge(T input T V ) Annealing(T input ) Denaturation(T input ) Separation(T input {C 0 C 1 }T output ) } We illustrate an execution of the above procedure. To simplify the illustration we assume that an input tube contains only one memory strand that is T input = {D 1 A i B j C 0 C 1 VD 0 }. After Merge and Annealing operations in Step 1 T input is given by D1 A T input = i B j C 0 C 1 VD 0 C 0 C 1 and after Step 1 T input becomesasfollows. T input = {D 1 A i B j C 0 } In Step 2 after Merge and Annealing operations T input is given by D1 A T input = i B j C 0 C 1 V D 0 C 0 C 1 then an output tube of the procedure is as follows. T output = {D 1 A i B j C 0 C 1 V D 0 } 6

8 V in1 V in2 V out1 V out2 0 0 α 00 β α 01 β α 10 β α 11 β 11 Figure 1: A truth table (where α ij β ij {0 1}.) The complexity of the above procedure is O(1) steps because only a constant number of DNA manipulations are executed for memory strands in parallel. The DNA strands used in the procedure is O(mn) memory strands and O(1) kinds of O(mn) auxiliary strands in T C and T V. Then we obtain the following lemma. Lemma 1 Value Assignment for O(mn) memory strands can be executed in O(1) steps using O(1) kinds of O(mn) additional DNA strands. 4. Procedure for logic operations In this section we show a procedure which computes logic operations for pairs of two memory strands in parallel. Let us consider a logic operation whose inputs and outputs are Boolean values V in1 V in2 and V out1 V out2 respectively and the values are defined by a truth table in Figure 1. Also let the following test tube T input contain two memory strands whose values are V ij and V gh as an input. T input = {D 1 A i B j C 0 C 1 V ij D 0 D 1 A g B h C 0 C 1 V gh D 0 } Then an output of the procedure for the logic operation defined in Figure 1 is a test tube T output given below. {D 1 A i B j C 0 C 1 α 00 D 0 D 1 A g B h C 0 C 1 β 00 D 0 } (if V ij = V gh =0) {D T output = 1 A i B j C 0 C 1 α 01 D 0 D 1 A g B h C 0 C 1 β 01 D 0 } (if V ij =0V gh =1) {D 1 A i B j C 0 C 1 α 10 D 0 D 1 A g B h C 0 C 1 β 10 D 0 } (if V ij =1V gh =0) {D 1 A i B j C 0 C 1 α 11 D 0 D 1 A g B h C 0 C 1 β 11 D 0 } (if V ij = V gh =1) In the following subsections we first describe single strands which define a logic operation and next show an overview and details of the procedure Single strands for logic operations Four single strands are used to define a logic operation. We call the four strands logic strands and each of them corresponds to each row of a truth table. We assume that S ij (V ) is a memory strand whose value is V ( {0 1}) that is S ij (V )=D 1 A i B j C 0 C 1 VD 0. Then we consider a logic operation given by the truth table in Figure 1. We define a set of logic strands L ijgh for a pair of two memory strands S ij and S gh as 7

9 V in1 V in2 V out1 V out2 logic strands D 0 S ij (0)S gh (0)D D 0 S ij (0)S gh (1)D D 0 S ij (1)S gh (0)D D 0 S ij (1)S gh (1)D 1 1 Figure 2: A truth table and logic strands for the AND operation whose input values are S ij and S gh. follows. L ijgh = { α 00 D 0 S ij (0)S gh (0)D 1 β 00 α 01 D 0 S ij (0)S gh (1)D 1 β 01 α 10 D 0 S ij (1)S gh (0)D 1 β 10 } α 11 D 0 S ij (1)S gh (1)D 1 β 11 In the above definition each single strand in L ijgh consists of a complemental chain of two input memory strands and two strands in a set of single strands {α 00 D 0 α 01 D 0 α 10 D 0 α 11 D 0 D 1 β 00 D 1 β 01 D 1 β 10 D 1 β 11 } whichisa set of auxiliary strands to separate memory strands according to their values. Figure 2 shows an example of logic strands which denote the AND operation such that V out1 = V in1 V in2 and V out2 = V in Overview of the procedure The procedure consists of the following 3 steps. 1. Divide memory strands into two test tubes T 0 and T 1 according to outputs of the operation. Memory strands whose output values are 0 are stored in T 0 and the others are stored in T Assign values to memory strands in each of test tubes T 0 and T Merge two test tubes. The second and third steps are easily executed using Value assignment and Merge respectively. We describe outline of the first step in the following. To simplify the description we assume that the input test tube T input contains two memory strands S ij (X)S gh (Y ) whose values are X Y ( {0 1}) and their corresponding logic strands. That is T input = {S ij (X)S gh (Y )} L ijgh. The first step consists of three substeps. In the first substep the two memory strands are connected according to one of complemental logic strands. Then the connected 8

10 memory strands are separated to a temporal test tube. The substep is executed using mainly Annealing Denaturation and Separation as follows. (Single or double strands which do not include a memory strand are omitted in the description.) {S ij (X)S gh (Y )} L ijgh (Annealing) S ij (X)S gh (Y ) α XY D 0 S ij (X)S gh (Y )D 1 β XY (Denaturation&Separation) {S ij (X)S gh (Y )} T tmp In the second substep two memory strands are separated according to their output of the operation. Each connected memory strand is annealed with a complemental logic strand again. Each auxiliary strand in the complemental logic strand denotes an output value of the annealed memory strand. The annealed double strand is cut into two double strand so that each double strand contains one memory strand. Then an auxiliary strand are added to each memory strand and separated into one of two test tubes according to its auxiliary strand. After this substep a memory strand whose output value is α {0 1} is stored in a test tube T α with its auxiliary strand. The substep is executed using mainly Annealing Cleavage Denaturation and Separation as follows. {S ij (X)S gh (Y )} L ijgh (Annealing) S ij (X)S gh (Y ) α XY D 0 S ij (X)S gh (Y )D 1 β XY S ij (X) α XY D 0 S ij (X) ( { αxy D + 0 D 1 β XY αxy D 0 S ij (X) α XY D 0 S ij (X) (Cleavage) ] [ Sgh (Y ) S gh (Y )D 1 β XY }) (Annealing) ] [ Sgh (Y )D 1 β XY S gh (Y )D 1 β XY (Denaturation) 9

11 {α XY D 0 S ij (X) S gh (Y )D 1 β XY } (Separation) { T0 (if α α XY D 0 S ij (X) XY =0) (otherwise) { T0 (if β S gh (Y )D 1 β XY XY =0) T 1 (otherwise) In the third substep an auxiliary strand is cut after annealing and removed from each test tube. The substep is executed using mainly Annealing Cleavage and Denaturation as follows. (In case of α XY = β XY ) T αxy =β XY = {α XY D 0 S ij (X) S gh (Y )D 1 β XY } αxy D 0 S ij (X) α XY D 0 S ij (X) T 1 (Annealing) Sij (X) S ij (X) ] [ Sgh (X)D 1 β XY S gh (Y )D 1 β XY (Cleavage) ] [ Sgh (Y ) S gh (Y ) (Denaturation) T αxy =β XY = {S ij (X) S gh (Y )} (In case of α XY β XY ) T αxy = {α XY D 0 S ij (X)} T βxy = {S gh (Y )D 1 β XY } αxy D 0 S ij (X) α XY D 0 S ij (X) Sij (X) S ij (X) (Annealing) Sgh (X)D 1 β XY S gh (Y )D 1 β XY (Cleavage) Sgh (Y ) S gh (Y ) (Denaturation) T αxy = {S ij (X)} T βxy = {S gh (Y )} 10

12 4.3. Details of the procedure We summarize details of the procedure for a logic operation in the following. T input and T output are test tubes which contains input and output memory strands respectively. We assume that O(mn) memory strands are stored in T input. In addition T L is a test tube which contains O(mn) logic strands. Test tubes T 0 T 1 T 0T 1 and T tmp are used as temporal storage. Procedure LogicOperation (TestTube T input TestTube T L TestTube T output ) { Step 1: Divide memory strands into two test tubes T 0 and T 1 according to outputs of the operation. (1-1) Connect and select each pair of memory strands using their logic strands. Merge(T input T L ) Annealing(T input ) Denaturation(T input ) Separation(T input {D 0 D 1 D 0 D 1 }T tmp ) (1-2) Separate memory strands according to outputs of the operation. Annealing(T tmp ) Cleavage(T tmp D 0 D 1 ) Merge(T tmp {0 D 0 1 D 0 D 1 0 D 1 1 }) Annealing(T tmp ) Denaturation(T tmp ) Separation(T tmp {0 0 }T 0 ) Separation(T tmp {1 1 }T 1 ) (1-3) Cut and remove auxiliary strands from each strand. Annealing(T 0 ) Annealing(T 1 ) Cleavage(T 0 D 0 D 1 ) Cleavage(T 1 D 0 D 1 ) Denaturation(T 0 ) Denaturation(T 1 ) Separation(T 0 { C 0 C 1 }T tmp ) Separation(T 1 { C 0 C 1 }T tmp ) Step 2: Assign values to memory strands in each of test tubes T 0 T 1. V alueassignment 0(T 0 T 0 ) V alueassignment 1(T 1 T 1) Step 3: Merge two output test tubes. Copy(T 0 T output) Merge(T output T 1) } The procedure consists of a constant number of DNA manipulations except for Step 2 and Step 2 can be executed in O(1) steps from Lemma 1. Since the number of kinds of DNA strands used as memory or logic strands is O(mn) we obtain the following theorem. Theorem 1 Logic operations for O(mn) memory strands can be executed in O(1) steps using O(mn) different additional DNA strands. 11

13 Since the above procedure is applicable to any pair of memory strands using a logic strand we can execute different operations for pairs of memory strands in parallel. In addition the other simple operations such as NOT SHIFT or COPY are also executed with the same complexity. 5. Procedure for arithmetic operations In this section we show a procedure to add two binary numbers represented by memory strands. Since a basic idea of the procedure is similar to [5] we give a brief explanation only. We consider addition of two binary numbers a m 1 a m 2...a 0 and b m 1 b m 2...b 0 which represent two numbers a b such that a = m 1 j=0 a j 2 j and b = m 1 j=0 b j 2 j. We assume that the two numbers a b are stored in two sets of memory strands {S iam 1S iam 2...S ia0} and {S ib m 1S ib m 2...S ib 0} respectively. We also assume a m 1 = b m 1 = 0 to simplify the description. Then the sum s m 1 s m 2...s 0 of two numbers a b is obtained using a procedure consisting of the following four steps. (Binary operators and are XOR and AND operations respectively.) 1. For each j (0 j m 1) compute x j = a j b j andy j = a j b j. (This step denotes behavior of a half adder. x j and y j denote a sum and a carry bit obtained from j-th bits respectively.) 2. For each j (0 j m 1) compute p j = x j y j. (p j = 1 in case that the j-th bit propagates a carry in the (j 1)-th bit to the (j + 1)-th bit.) 3. For each j (1 j m 1) set c j =1ify j 1 =1orthereexistsk (< j)such that p j 1 = p j 2 =...= p k+1 =1andy k = 1 otherwise set c j =0. 4. For each j (1 j m 1) set s j = x j c j. The first second and fourth steps of the above procedure are easily implemented using a constant number of DNA manipulations and the logic procedure described in Section 4. Thus we discuss implementation of the third step in the following. Let y j and p j be binary values stored in memory strands S iy(ab) j and S ip(ab) j for each j (0 j m 1). We first generate the following single strand C j for each j (1 j m 1). (C j includes a memory strand for c j whose value is 0 that is S ic(ab) j(0).) C j = D 1 A ic(ab) B j C 0 C 1 0 D 0 D 1 A iy(ab) B j = S ic(ab) j(0)d 1 A iy(ab) B j Next we generate the following two single strands Y j (1) and P j (1) if y j =1and p j =1foreachj (0 j m 1) respectively. Y j (1) = A iy(ab) B j 1 P j (1) = A iy(ab) B j A iy(ab) B j Finally we generate a single strand Q j j 1 for each j (1 j m 1) to propagate a carry. Q j j 1 = A iy(ab) B j A iy(ab) B j 1 12

14 The above single strands are stored in a test tube and annealed. We first consider the case that y j 1 = 1. We obtain the following double strand for c j. C j Y j 1 (1) Q j j 1 We next consider the case that p j 1 = p j 2 =... = p k+1 =1andy k =1. Single strands Q j j 1 Q j 1 j 2...Q k+1 k are used to propagate a carry stored in Y k (1) and we obtain the following double strand for c j. C j P j 1 (1) P j 2 (1) P k+1 (1) Y k (1) Q j j 1 Q j 1 j Q k+2 k+1 Q k+1 k After Denaturation for the test tube a single strand containing a string 1 is separated into another test tube T 1 using Separation. (In the above examples Y j 1 (1) and Y k (1) contain the string.) The other single strands containing a memory strand is also separated and stored in T 0. Memory strands in separated single strands are cut and extracted by a similar method to Value Assignment. Therefore we obtain two test tubes: one contains memory strands set to 0 and the other contains memory strands set to 1. Using Value Assignment and Merge the third step is completed. Since the whole procedure consists of a constant number of DNA manipulations and uses O(mn) kinds of DNA strands we obtain the following theorem. Theorem 2 Additions for O(n) pairs of m-bit binary numbers can be executed in O(1) steps using O(mn) different additional DNA strands. The procedure for additions are easily modified to be applied to subtractions. Thus we can compute subtractions with the same complexity using DNA strands. 6. Conclusions In this paper we proposed two procedures for logic and arithmetic operations using DNA strands. Both procedures work in O(1) steps using O(mn) different additional DNA strands. Our procedures can execute different logic or arithmetic operations in parallel because addresses and operations are denoted using single strands. Therefore our procedure can be used for general parallel processing with DNA molecules. Since our results are based on a theoretical model some defects are involved in the procedures for practical use. The first one is a preparation of inputs. Although we can synthesize any kinds of DNA strands using biological methods the preparative step needs a few days in practice. Thus a preparation of O(mn) additional DNA strands needs considerable lab operations. The second one is the propagation of a carry in Section 5. The length of a DNA strand has a biological limit and we have to keep DNA strands at constant length. However every DNA manipulation used in the model has been already realized in lab level and some procedures can be implemented practically. Since logic and 13

15 arithmetic operations are primitive we believe that our results play an important role in the future DNA computing. References 1. L. M. Adleman. Molecular computation of solutions to combinatorial problems. Science 266: P. Frisco. Parallel arithmetic with splicing. Romanian Journal of Information Science and Technology 2(3): F. Guarnieri M. Fliss and C. Bancroft. Making DNA add. Science 273: V. Gupta S. Parthasarathy and M. J. Zaki. Arithmetic and logic operations with DNA. In Proceedings of the 3rd DIMACS Workshop on DNA Based Computers pages H. Hug and R. Schuler. DNA-based parallel computation of simple arithmetic. In Proceedings of the 7th International Meeting on DNA Based Computers pages R. J. Liption. DNA solution of hard computational problems. Science 268: R. B. Merrifield. Solid phase peptide synthesis. I. The synthesis of a tetrapeptide. Journal of the American Chemical Society 85: G. Pǎun G. Rozeberg and A. Salomaa. DNA computing. Springer-Verlag Z. F. Qiu and M. Lu. Arithmetic and logic operations for DNA computers. In Proceedings of the Second IASTED International conference on Parallel and Distributed Computing and Networks pages Z. F. Qiu and M. Lu. Take advantage of the computing power of DNA computers. In Proceedings of the Third Workshop on Bio-Inspired Solutions to Parallel Processing Problems IPDPS 2000 Workshops pages J. H. Reif. Parallel biomolecular computation: Models and simulations. Algorithmica 25(2/3):

Procedures for multiplication and division in DNA computing

Procedures for multiplication and division in DNA computing Procedures for multiplication and division in DNA computing Hiroki Fukagawa, Akihiro Fujiwara Department of Computer Science and Electronics Kyushu Institute of Technology 680-4 Kawazu, Iizuka, Fukuoka

More information

A Procedure for Computing 0-1 Integer Programming with DNA Strands. 2 Preliminaries. 1 Introduction. 2.1 Computational model for DNA computing

A Procedure for Computing 0-1 Integer Programming with DNA Strands. 2 Preliminaries. 1 Introduction. 2.1 Computational model for DNA computing A Procedure for Computing 0-1 Integer Programming with DNA Strands Kota Atsuyama, Akihiro Fujiwara Department of Computer Science and Electronics Kyushu Institute of Technology 680-4 Kawazu, Iizuka, Fukuoka

More information

A DNA procedure for solving the shortest path problem q

A DNA procedure for solving the shortest path problem q Applied Mathematics and Computation 183 (006) 79 84 www.elsevier.com/locate/amc A DNA procedure for solving the shortest path problem q Zhaocai Wang a,c, Dongmei Xiao a,c, Wenxia Li b,c, *,1, Lin He c

More information

von Neumann Architecture

von Neumann Architecture Computing with DNA & Review and Study Suggestions 1 Wednesday, April 29, 2009 von Neumann Architecture Refers to the existing computer architectures consisting of a processing unit a single separate storage

More information

Using DNA to Solve NP-Complete Problems. Richard J. Lipton y. Princeton University. Princeton, NJ 08540

Using DNA to Solve NP-Complete Problems. Richard J. Lipton y. Princeton University. Princeton, NJ 08540 Using DNA to Solve NP-Complete Problems Richard J. Lipton y Princeton University Princeton, NJ 08540 rjl@princeton.edu Abstract: We show how to use DNA experiments to solve the famous \SAT" problem of

More information

Integer and Vector Multiplication by Using DNA

Integer and Vector Multiplication by Using DNA Int. J. Open Problems Compt. Math., Vol. 1, No. 2, September 2008 Integer and Vector Multiplication by Using DNA Essam Al-Daoud 1, Belal Zaqaibeh 2, and Feras Al-Hanandeh 3 1 Computer Science Department,

More information

Watson-Crick ω-automata. Elena Petre. Turku Centre for Computer Science. TUCS Technical Reports

Watson-Crick ω-automata. Elena Petre. Turku Centre for Computer Science. TUCS Technical Reports Watson-Crick ω-automata Elena Petre Turku Centre for Computer Science TUCS Technical Reports No 475, December 2002 Watson-Crick ω-automata Elena Petre Department of Mathematics, University of Turku and

More information

Cancer Genome Assembly and Alignment Michael Shan-Hui Ho , Kun-Yu Hung , Yu-Shiang Gen , Chaochang Chiu and Tsung-Hua Lu Abstract

Cancer Genome Assembly and Alignment Michael Shan-Hui Ho , Kun-Yu Hung , Yu-Shiang Gen , Chaochang Chiu and Tsung-Hua Lu Abstract Cancer Genome Assembly and Alignment Michael Shan-Hui Ho 1, Kun-Yu Hung 2, Yu-Shiang Gen 1, Chaochang Chiu 3 and Tsung-Hua Lu 1 1 Department of Electric Engineering, NTPU, New Taipei City, Taiwan, ROC

More information

Donald Beaver. Penn State University, State College, PA 16802, USA. Abstract. We consider molecular models for computing and derive a

Donald Beaver. Penn State University, State College, PA 16802, USA. Abstract. We consider molecular models for computing and derive a Factoring: The DNA Solution Donald Beaver Penn State University, State College, PA 16802, USA Abstract. We consider molecular models for computing and derive a DNA-based mechanism for solving intractable

More information

How Does Nature Compute?

How Does Nature Compute? How Does Nature Compute? Lila Kari Dept. of Computer Science University of Western Ontario London, ON, Canada http://www.csd.uwo.ca/~lila/ lila@csd.uwo.ca Computers: What can they accomplish? Fly spaceships

More information

Adders - Subtractors

Adders - Subtractors Adders - Subtractors Lesson Objectives: The objectives of this lesson are to learn about: 1. Half adder circuit. 2. Full adder circuit. 3. Binary parallel adder circuit. 4. Half subtractor circuit. 5.

More information

Tissue P Systems with Cell Division

Tissue P Systems with Cell Division Tissue P Systems with Cell Division Gheorghe PĂUN 1,2, Mario PÉREZ-JIMÉNEZ 2, Agustín RISCOS-NÚÑEZ 2 1 Institute of Mathematics of the Romanian Academy PO Box 1-764, 014700 Bucureşti, Romania 2 Research

More information

On P Systems with Active Membranes

On P Systems with Active Membranes On P Systems with Active Membranes Andrei Păun Department of Computer Science, University of Western Ontario London, Ontario, Canada N6A 5B7 E-mail: apaun@csd.uwo.ca Abstract. The paper deals with the

More information

Analysis and Synthesis of Weighted-Sum Functions

Analysis and Synthesis of Weighted-Sum Functions Analysis and Synthesis of Weighted-Sum Functions Tsutomu Sasao Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka 820-8502, Japan April 28, 2005 Abstract A weighted-sum

More information

Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan

Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential

More information

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL. 2017-18 XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL HALF ADDER 1. The circuit that performs addition within the Arithmetic and Logic Unit of the CPU are called adders. 2. A unit that adds two

More information

Chapter 03: Computer Arithmetic. Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design

Chapter 03: Computer Arithmetic. Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design Chapter 03: Computer Arithmetic Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design Objective To understand adder circuit Subtractor circuit Fast adder circuit 2 Adder Circuit 3 Full

More information

NP-completeness. Chapter 34. Sergey Bereg

NP-completeness. Chapter 34. Sergey Bereg NP-completeness Chapter 34 Sergey Bereg Oct 2017 Examples Some problems admit polynomial time algorithms, i.e. O(n k ) running time where n is the input size. We will study a class of NP-complete problems

More information

Binary addition by hand. Adding two bits

Binary addition by hand. Adding two bits Chapter 3 Arithmetic is the most basic thing you can do with a computer We focus on addition, subtraction, multiplication and arithmetic-logic units, or ALUs, which are the heart of CPUs. ALU design Bit

More information

Combinational Logic. By : Ali Mustafa

Combinational Logic. By : Ali Mustafa Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output

More information

Note Watson Crick D0L systems with regular triggers

Note Watson Crick D0L systems with regular triggers Theoretical Computer Science 259 (2001) 689 698 www.elsevier.com/locate/tcs Note Watson Crick D0L systems with regular triggers Juha Honkala a; ;1, Arto Salomaa b a Department of Mathematics, University

More information

Inverse HAMILTONIAN CYCLE and Inverse 3-D MATCHING Are conp-complete

Inverse HAMILTONIAN CYCLE and Inverse 3-D MATCHING Are conp-complete Inverse HAMILTONIAN CYCLE and Inverse 3-D MATCHING Are conp-complete Michael Krüger and Harald Hempel Institut für Informatik, Friedrich-Schiller-Universität Jena {krueger, hempel}@minet.uni-jena.de Abstract.

More information

Experiment 7: Magnitude comparators

Experiment 7: Magnitude comparators Module: Logic Design Lab Name:... University no:.. Group no: Lab Partner Name: Experiment 7: Magnitude comparators Mr. Mohamed El-Saied Objective: Realization of -bit comparator using logic gates. Realization

More information

Digital Systems Roberto Muscedere Images 2013 Pearson Education Inc. 1

Digital Systems Roberto Muscedere Images 2013 Pearson Education Inc. 1 Digital Systems Digital systems have such a prominent role in everyday life The digital age The technology around us is ubiquitous, that is we don t even notice it anymore Digital systems are used in:

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept

More information

XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure.

XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure. XOR - XNOR Gates Lesson Objectives: In addition to AND, OR, NOT, NAND and NOR gates, exclusive-or (XOR) and exclusive-nor (XNOR) gates are also used in the design of digital circuits. These have special

More information

CSE 555 HW 5 SAMPLE SOLUTION. Question 1.

CSE 555 HW 5 SAMPLE SOLUTION. Question 1. CSE 555 HW 5 SAMPLE SOLUTION Question 1. Show that if L is PSPACE-complete, then L is NP-hard. Show that the converse is not true. If L is PSPACE-complete, then for all A PSPACE, A P L. We know SAT PSPACE

More information

The Cook-Levin Theorem

The Cook-Levin Theorem An Exposition Sandip Sinha Anamay Chaturvedi Indian Institute of Science, Bangalore 14th November 14 Introduction Deciding a Language Let L {0, 1} be a language, and let M be a Turing machine. We say M

More information

COMBINATIONAL LOGIC FUNCTIONS

COMBINATIONAL LOGIC FUNCTIONS COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present

More information

Natural Computing Modelling of the Polynomial Space Turing Machines

Natural Computing Modelling of the Polynomial Space Turing Machines Natural Computing Modelling of the Polynomial Space Turing Machines Bogdan Aman and Gabriel Ciobanu Romanian Academy, Institute of Computer Science Blvd. Carol I no., 756 Iaşi, Romania baman@iit.tuiasi.ro,

More information

Introduction to Digital Logic Missouri S&T University CPE 2210 Subtractors

Introduction to Digital Logic Missouri S&T University CPE 2210 Subtractors Introduction to Digital Logic Missouri S&T University CPE 2210 Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology cetinkayae@mst.edu

More information

COSC 594 Final Presentation Membrane Systems/ P Systems

COSC 594 Final Presentation Membrane Systems/ P Systems COSC 594 Final Presentation Membrane Systems/ P Systems Mesbah Uddin & Gangotree Chakma November, 6 Motivation of Unconventional Computing Parallel computing-- restricted in conventional computers Deterministic

More information

Geometric Steiner Trees

Geometric Steiner Trees Geometric Steiner Trees From the book: Optimal Interconnection Trees in the Plane By Marcus Brazil and Martin Zachariasen Part 3: Computational Complexity and the Steiner Tree Problem Marcus Brazil 2015

More information

15.1 Proof of the Cook-Levin Theorem: SAT is NP-complete

15.1 Proof of the Cook-Levin Theorem: SAT is NP-complete CS125 Lecture 15 Fall 2016 15.1 Proof of the Cook-Levin Theorem: SAT is NP-complete Already know SAT NP, so only need to show SAT is NP-hard. Let L be any language in NP. Let M be a NTM that decides L

More information

Definition: Alternating time and space Game Semantics: State of machine determines who

Definition: Alternating time and space Game Semantics: State of machine determines who CMPSCI 601: Recall From Last Time Lecture Definition: Alternating time and space Game Semantics: State of machine determines who controls, White wants it to accept, Black wants it to reject. White wins

More information

NP-Completeness. NP-Completeness 1

NP-Completeness. NP-Completeness 1 NP-Completeness x x x 2 x 2 x 3 x 3 x 4 x 4 2 22 32 3 2 23 3 33 NP-Completeness Outline and Reading P and NP ( 3.) Definition of P Definition of NP Alternate definition of NP NP-completeness ( 3.2) Definition

More information

Language Recognition Power of Watson-Crick Automata

Language Recognition Power of Watson-Crick Automata 01 Third International Conference on Netorking and Computing Language Recognition Poer of Watson-Crick Automata - Multiheads and Sensing - Kunio Aizaa and Masayuki Aoyama Dept. of Mathematics and Computer

More information

EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits)

EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) September 5, 2002 John Wawrzynek Fall 2002 EECS150 Lec4-bool1 Page 1, 9/5 9am Outline Review of

More information

Carry Look Ahead Adders

Carry Look Ahead Adders Carry Look Ahead Adders Lesson Objectives: The objectives of this lesson are to learn about: 1. Carry Look Ahead Adder circuit. 2. Binary Parallel Adder/Subtractor circuit. 3. BCD adder circuit. 4. Binary

More information

2009 Spring CS211 Digital Systems & Lab CHAPTER 2: INTRODUCTION TO LOGIC CIRCUITS

2009 Spring CS211 Digital Systems & Lab CHAPTER 2: INTRODUCTION TO LOGIC CIRCUITS CHAPTER 2: INTRODUCTION TO LOGIC CIRCUITS What will we learn? 2 Logic functions and circuits Boolean Algebra Logic gates and Synthesis CAD tools and VHDL Read Section 2.9 and 2.0 Terminology 3 Digital

More information

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr. Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational

More information

Spiking Neural P Systems with Anti-Spikes as Transducers

Spiking Neural P Systems with Anti-Spikes as Transducers ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 14, Number 1, 2011, 20 30 Spiking Neural P Systems with Anti-Spikes as Transducers Venkata Padmavati METTA 1, Kamala KRITHIVASAN 2, Deepak

More information

CHAPTER1: Digital Logic Circuits Combination Circuits

CHAPTER1: Digital Logic Circuits Combination Circuits CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.

More information

Outline. EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) Combinational Logic (CL) Defined

Outline. EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) Combinational Logic (CL) Defined EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) January 30, 2003 John Wawrzynek Outline Review of three representations for combinational logic:

More information

Fundamentals of Digital Design

Fundamentals of Digital Design Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric

More information

Tecniche di Verifica. Introduction to Propositional Logic

Tecniche di Verifica. Introduction to Propositional Logic Tecniche di Verifica Introduction to Propositional Logic 1 Logic A formal logic is defined by its syntax and semantics. Syntax An alphabet is a set of symbols. A finite sequence of these symbols is called

More information

Determine the size of an instance of the minimum spanning tree problem.

Determine the size of an instance of the minimum spanning tree problem. 3.1 Algorithm complexity Consider two alternative algorithms A and B for solving a given problem. Suppose A is O(n 2 ) and B is O(2 n ), where n is the size of the instance. Let n A 0 be the size of the

More information

Structure-Based Comparison of Biomolecules

Structure-Based Comparison of Biomolecules Structure-Based Comparison of Biomolecules Benedikt Christoph Wolters Seminar Bioinformatics Algorithms RWTH AACHEN 07/17/2015 Outline 1 Introduction and Motivation Protein Structure Hierarchy Protein

More information

Computer Organization I

Computer Organization I Computer Organization I Lecture 6: Boolean Algebra /2/29 Wei Lu CS283 Overview Two Principles in Boolean Algebra () Duality Principle (2) Complement Principle Standard Form of Logic Expression () Sum of

More information

Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.

Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Combinational Circuits

More information

The DNA-Based Algorithms of Implementing Arithmetical Operations of Complex Vectors on a Biological Computer

The DNA-Based Algorithms of Implementing Arithmetical Operations of Complex Vectors on a Biological Computer IEEE TRANSACTIONS ON NANOBIOSCIENCE VOL 14 NO 8 DECEMBER 2015 907 The DNA-Based Algorithms of Implementing Arithmetical Operations of Complex Vectors on a Biological Computer Weng-Long Chang Athanasios

More information

Digital Systems and Information Part II

Digital Systems and Information Part II Digital Systems and Information Part II Overview Arithmetic Operations General Remarks Unsigned and Signed Binary Operations Number representation using Decimal Codes BCD code and Seven-Segment Code Text

More information

Theory of Computation Time Complexity

Theory of Computation Time Complexity Theory of Computation Time Complexity Bow-Yaw Wang Academia Sinica Spring 2012 Bow-Yaw Wang (Academia Sinica) Time Complexity Spring 2012 1 / 59 Time for Deciding a Language Let us consider A = {0 n 1

More information

Algorithmic Approach to Counting of Certain Types m-ary Partitions

Algorithmic Approach to Counting of Certain Types m-ary Partitions Algorithmic Approach to Counting of Certain Types m-ary Partitions Valentin P. Bakoev Abstract Partitions of integers of the type m n as a sum of powers of m (the so called m-ary partitions) and their

More information

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Signed Numbers CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative

More information

5 3 Sensing Watson-Crick Finite Automata

5 3 Sensing Watson-Crick Finite Automata Benedek Nagy Department of Computer Science, Faculty of Informatics, University of Debrecen, Hungary 1 Introduction DNA computers provide new paradigms of computing (Păun et al., 1998). They appeared at

More information

DNA computing, sticker systems, and universality

DNA computing, sticker systems, and universality Acta Informatica 35, 401 420 1998 c Springer-erlag 1998 DNA computing, sticker systems, and universality Lila Kari 1, Gheorghe Păun 2, Grzegorz Rozenberg 3, Arto Salomaa 4, Sheng Yu 1 1 Department of Computer

More information

Logic. Combinational. inputs. outputs. the result. system can

Logic. Combinational. inputs. outputs. the result. system can Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends

More information

Timed Watson-Crick Online Tessellation Automaton

Timed Watson-Crick Online Tessellation Automaton Annals of Pure and Applied Mathematics Vol. 8, No. 2, 204, 75-82 ISSN: 2279-087X (P), 2279-0888(online) Published on 7 December 204 www.researchmathsci.org Annals of Timed Watson-Cric Online Tessellation

More information

Discrete Mathematics. CS204: Spring, Jong C. Park Computer Science Department KAIST

Discrete Mathematics. CS204: Spring, Jong C. Park Computer Science Department KAIST Discrete Mathematics CS204: Spring, 2008 Jong C. Park Computer Science Department KAIST Today s Topics Combinatorial Circuits Properties of Combinatorial Circuits Boolean Algebras Boolean Functions and

More information

A Lower Bound of 2 n Conditional Jumps for Boolean Satisfiability on A Random Access Machine

A Lower Bound of 2 n Conditional Jumps for Boolean Satisfiability on A Random Access Machine A Lower Bound of 2 n Conditional Jumps for Boolean Satisfiability on A Random Access Machine Samuel C. Hsieh Computer Science Department, Ball State University July 3, 2014 Abstract We establish a lower

More information

Chapter 5 Arithmetic Circuits

Chapter 5 Arithmetic Circuits Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed

More information

CS6901: review of Theory of Computation and Algorithms

CS6901: review of Theory of Computation and Algorithms CS6901: review of Theory of Computation and Algorithms Any mechanically (automatically) discretely computation of problem solving contains at least three components: - problem description - computational

More information

CSCI 1590 Intro to Computational Complexity

CSCI 1590 Intro to Computational Complexity CSCI 59 Intro to Computational Complexity Overview of the Course John E. Savage Brown University January 2, 29 John E. Savage (Brown University) CSCI 59 Intro to Computational Complexity January 2, 29

More information

COE 202: Digital Logic Design Combinational Circuits Part 2. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

COE 202: Digital Logic Design Combinational Circuits Part 2. Dr. Ahmad Almulhem   ahmadsm AT kfupm Phone: Office: COE 202: Digital Logic Design Combinational Circuits Part 2 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Arithmetic Circuits Adder Subtractor Carry Look Ahead Adder

More information

Looking at a two binary digit sum shows what we need to extend addition to multiple binary digits.

Looking at a two binary digit sum shows what we need to extend addition to multiple binary digits. A Full Adder The half-adder is extremely useful until you want to add more that one binary digit quantities. The slow way to develop a two binary digit adders would be to make a truth table and reduce

More information

CMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned

CMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned Focus Groups CMSC 33 Lecture 7 Need good sample of all types of CS students Mon /7 & Thu /2, 2:3p-2:p & 6:p-7:3p Announcement: in-class lab Thu /3 Homework 3 Questions Circuits for Addition Midterm Exam

More information

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits Logic and Computer Design Fundamentals Chapter 5 Arithmetic Functions and Circuits Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block

More information

DIGITAL CIRCUIT LOGIC BOOLEAN ALGEBRA (CONT.)

DIGITAL CIRCUIT LOGIC BOOLEAN ALGEBRA (CONT.) DIGITAL CIRCUIT LOGIC BOOLEAN ALGEBRA (CONT.) 1 Learning Objectives 1. Apply the laws and theorems of Boolean algebra to to the manipulation of algebraic expressions to simplifying an expression, finding

More information

九州工業大学学術機関リポジトリ. Title Chain System: F5PNN in a Magnetic = 1/2 A. Author(s) Hosokoshi, Y; Inoue, K. Issue Date

九州工業大学学術機関リポジトリ. Title Chain System: F5PNN in a Magnetic = 1/2 A. Author(s) Hosokoshi, Y; Inoue, K. Issue Date 九州工業大学学術機関リポジトリ Title Specific Heat Study of an S Chain System: F5PNN in a Magnetic = 1/ A F Author(s) Yoshida, Y; Tateiwa, N; Mito, Masak Hosokoshi, Y; Inoue, K Issue Date 005 URL http://hdl.handle.net/108/67

More information

Quantum computation: a tutorial

Quantum computation: a tutorial Quantum computation: a tutorial Samuel L. Braunstein Abstract: Imagine a computer whose memory is exponentially larger than its apparent physical size; a computer that can manipulate an exponential set

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT2: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 4 Following the slides of Dr. Ahmed H. Madian محرم 439 ه Winter 28

More information

Sample Test Paper - I

Sample Test Paper - I Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:

More information

Digital Techniques. Figure 1: Block diagram of digital computer. Processor or Arithmetic logic unit ALU. Control Unit. Storage or memory unit

Digital Techniques. Figure 1: Block diagram of digital computer. Processor or Arithmetic logic unit ALU. Control Unit. Storage or memory unit Digital Techniques 1. Binary System The digital computer is the best example of a digital system. A main characteristic of digital system is its ability to manipulate discrete elements of information.

More information

Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.

Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Announcements Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Chapter 5 1 Chapter 3: Part 3 Arithmetic Functions Iterative combinational circuits

More information

where Q is a finite set of states

where Q is a finite set of states Space Complexity So far most of our theoretical investigation on the performances of the various algorithms considered has focused on time. Another important dynamic complexity measure that can be associated

More information

Adequate set of connectives, logic gates and circuits

Adequate set of connectives, logic gates and circuits Adequate set of connectives, logic gates and circuits Lila Kari University of Waterloo Adequate set of connectives, logic gates and circuits CS245, Logic and Computation 1 / 59 Connectives We have mentioned

More information

CS3719 Theory of Computation and Algorithms

CS3719 Theory of Computation and Algorithms CS3719 Theory of Computation and Algorithms Any mechanically (automatically) discretely computation of problem solving contains at least three components: - problem description - computational tool - analysis

More information

Boolean Algebra & Digital Logic

Boolean Algebra & Digital Logic Boolean Algebra & Digital Logic Boolean algebra was developed by the Englishman George Boole, who published the basic principles in the 1854 treatise An Investigation of the Laws of Thought on Which to

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Digital

More information

Chapter 2 Boolean Algebra and Logic Gates

Chapter 2 Boolean Algebra and Logic Gates Chapter 2 Boolean Algebra and Logic Gates The most common postulates used to formulate various algebraic structures are: 1. Closure. N={1,2,3,4 }, for any a,b N we obtain a unique c N by the operation

More information

GF(2 m ) arithmetic: summary

GF(2 m ) arithmetic: summary GF(2 m ) arithmetic: summary EE 387, Notes 18, Handout #32 Addition/subtraction: bitwise XOR (m gates/ops) Multiplication: bit serial (shift and add) bit parallel (combinational) subfield representation

More information

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION

More information

Logic Design II (17.342) Spring Lecture Outline

Logic Design II (17.342) Spring Lecture Outline Logic Design II (17.342) Spring 2012 Lecture Outline Class # 10 April 12, 2012 Dohn Bowden 1 Today s Lecture First half of the class Circuits for Arithmetic Operations Chapter 18 Should finish at least

More information

Building a Computer Adder

Building a Computer Adder Logic Gates are used to translate Boolean logic into circuits. In the abstract it is clear that we can build AND gates that perform the AND function and OR gates that perform the OR function and so on.

More information

Chapter 2 Basic Arithmetic Circuits

Chapter 2 Basic Arithmetic Circuits Chapter 2 Basic Arithmetic Circuits This chapter is devoted to the description of simple circuits for the implementation of some of the arithmetic operations presented in Chap. 1. Specifically, the design

More information

Floating Point Representation and Digital Logic. Lecture 11 CS301

Floating Point Representation and Digital Logic. Lecture 11 CS301 Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8

More information

PHASE TRANSITION IN A SYSTEM OF RANDOM SPARSE BOOLEAN EQUATIONS

PHASE TRANSITION IN A SYSTEM OF RANDOM SPARSE BOOLEAN EQUATIONS Tatra Mt. Math. Publ. 45 (2010), 93 105 DOI: 10.2478/v10127-010-0008-7 t m Mathematical Publications PHASE TRANSITION IN A SYSTEM OF RANDOM SPARSE BOOLEAN EQUATIONS Thorsten Schilling Pavol Zajac ABSTRACT.

More information

Implementing Approximate Regularities

Implementing Approximate Regularities Implementing Approximate Regularities Manolis Christodoulakis Costas S. Iliopoulos Department of Computer Science King s College London Kunsoo Park School of Computer Science and Engineering, Seoul National

More information

NP-Complete problems

NP-Complete problems NP-Complete problems NP-complete problems (NPC): A subset of NP. If any NP-complete problem can be solved in polynomial time, then every problem in NP has a polynomial time solution. NP-complete languages

More information

IT T35 Digital system desigm y - ii /s - iii

IT T35 Digital system desigm y - ii /s - iii UNIT - II Combinational Logic Adders subtractors code converters binary parallel adder decimal adder magnitude comparator encoders decoders multiplexers demultiplexers-binarymultiplier Parity generator

More information

Design of Sequential Circuits

Design of Sequential Circuits Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable

More information

PERFORMANCE ANALYSIS OF CLA CIRCUITS USING SAL AND REVERSIBLE LOGIC GATES FOR ULTRA LOW POWER APPLICATIONS

PERFORMANCE ANALYSIS OF CLA CIRCUITS USING SAL AND REVERSIBLE LOGIC GATES FOR ULTRA LOW POWER APPLICATIONS PERFORMANCE ANALYSIS OF CLA CIRCUITS USING SAL AND REVERSIBLE LOGIC GATES FOR ULTRA LOW POWER APPLICATIONS K. Prasanna Kumari 1, Mrs. N. Suneetha 2 1 PG student, VLSI, Dept of ECE, Sir C R Reddy College

More information

CS61c: Representations of Combinational Logic Circuits

CS61c: Representations of Combinational Logic Circuits CS61c: Representations of Combinational Logic Circuits J. Wawrzynek March 5, 2003 1 Introduction Recall that synchronous systems are composed of two basic types of circuits, combination logic circuits,

More information

Algorithms and Data S tructures Structures Complexity Complexit of Algorithms Ulf Leser

Algorithms and Data S tructures Structures Complexity Complexit of Algorithms Ulf Leser Algorithms and Data Structures Complexity of Algorithms Ulf Leser Content of this Lecture Efficiency of Algorithms Machine Model Complexity Examples Multiplication of two binary numbers (unit cost?) Exact

More information

Automata-Theoretic LTL Model-Checking

Automata-Theoretic LTL Model-Checking Automata-Theoretic LTL Model-Checking Arie Gurfinkel arie@cmu.edu SEI/CMU Automata-Theoretic LTL Model-Checking p.1 LTL - Linear Time Logic (Pn 77) Determines Patterns on Infinite Traces Atomic Propositions

More information

The Complexity of Optimization Problems

The Complexity of Optimization Problems The Complexity of Optimization Problems Summary Lecture 1 - Complexity of algorithms and problems - Complexity classes: P and NP - Reducibility - Karp reducibility - Turing reducibility Uniform and logarithmic

More information

COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture)

COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture) COSC 243 Introduction to Logic And Combinatorial Logic 1 Overview This Lecture Introduction to Digital Logic Gates Boolean algebra Combinatorial Logic Source: Chapter 11 (10 th edition) Source: J.R. Gregg,

More information

An Approach to Computational Complexity in Membrane Computing

An Approach to Computational Complexity in Membrane Computing An Approach to Computational Complexity in Membrane Computing Mario J. Pérez-Jiménez Research Group on Natural Computing, Department of Computer Science and Artificial Intelligence, University of Sevilla

More information