Selective nano-patterning of graphene using a heated atomic force microscope tip

Transcription

1 REVIEW OF SCIENTIFIC INSTRUMENTS 85, (2014) Selective nano-patterning of graphene using a heated atomic force microscope tip Young-Soo Choi, Xuan Wu, and Dong-Weon Lee a) MEMS and Nanotechnology Laboratory, School of Mechanical Engineering, Chonnam National University, Gwangju, South Korea (Received 30 October 2013; accepted 25 March 2014; published online 14 April 2014) In this study, we introduce a selective thermochemical nano-patterning method of graphene on insulating substrates. A tiny heater formed at the end of an atomic force microscope (AFM) cantilever is optimized by a finite element method. The cantilever device is fabricated using conventional micromachining processes. After preliminary tests of the cantilever device, nano-patterning experiments are conducted with various conducting and insulating samples. The results indicate that faster scanning speed and higher contact force are desirable to reduce the sizes of nano-patterns. With the experimental condition of 1 μm/s and 24 mw, the heated AFM tip generates a graphene oxide layer of 3.6 nm height and 363 nm width, on a 300 nm thick SiO 2 layer, with a tip contact force of 100 nn AIP Publishing LLC. [ I. INTRODUCTION With the increasing cost of photo masks, alternative techniques to optical lithography have been widely investigated, particularly for low-volume manufacturing and prototyping in conventional processes. One of these methods, the atomic force microscopy (AFM)-based lithography technique is often applied in nano-lithography. This technique does not require a photo mask; yet it generates a high resolution pattern in ambient and room temperature conditions. 1 Sheehan et al. proposed a nanoscale deposition method of solid inks via thermal dip pen nanolithography. 2 Fenwick et al. presented a thermochemical nano-lithography for organic semiconductors. 3 Furthermore, the technique allows quasi-simultaneous surface modification and topographical analyses of solid surfaces, in much the same way as the conventional scanning probe technique. The AFM-based lithography methods can be categorized as dip pen lithography, anodic oxidation lithography, NSOM lithography, and thermal lithography, according to their principles of patterning Graphene, a single atomic layer of graphite, has received much attention due to its excellent mechanical ( 1.0 TPa), and electrical ( cm 2 v 1 s 1 ) properties. Graphene structures with specific patterns will be very useful for nanodevice applications, Thus, nano-patterning techniques that make graphene surfaces into any desired shape have become important. A combined process of electron beam (EB) lithography and O 2 plasma etching was developed to make graphene-based nano-devices. However, this method causes damage at the roughly etched surface of graphene. Physical properties of the graphene can be affected by the scattering effect. 19 To solve these drawbacks, a local anodic oxidation (LAO) technique with AFM has been suggested as a new patterning method for graphene The advantages of the LAO method include its abilities to pattern a surface to nanometer resolution and to characterize the patterned nano-structures. a) Author to whom correspondence should be addressed. Electronic mail: mems@jnu.ac.kr. Tel.: Fax: The process is also done in an ambient environment through an electro-chemical reaction only. Thus, the method does not affect the physical properties of graphene material during the patterning process. Neubeck et al. have reported the result of scanning probe lithography on graphene. They also employed the LAO technique to avoid any contamination of graphene surface during the patterning process. An interesting point to note is the fact that applying LAO technique to graphene resulted in either etching lines or in creating a stable oxide. 23 Even though the anodic oxidation method has several advantages, in comparison with conventional photolithography, this method can be applied to pattern only conducting or semiconducting substrates. 4 This paper proposes a new graphene patterning method using a tiny heating element that is embedded at the cantilever tip area. The heating element enables localized heating with a time constant of less than 10 μs. It allows the graphene nano-patterning process to be independent of the conductivity of the substrate. The fabricated cantilever with the heating element was applied for thermal patterning on silicon substrates with various thin films. At first, the LAO technique was employed on single layer CVD graphene to study the synthesis of graphene oxide. Additionally, characterization of the heated scanning tip was carried out by generating micro/nano patterns on a 50 nm-thick AZ5214 photoresist and 10 nmthick titanium (Ti) layer. Finally, the heated tip successfully formed graphene oxide on an insulating surface. All the experiments were conducted in ambient environment. II. SYNTHESIS OF GRAPHENE OXIDE BY FIELD EMISSION LAO LITHOGRAPHY Graphene oxide (GO) is covalently functionalized graphene with oxygen-containing functional groups, and consists of a cluster of sp 2 -hybridized carbons, in an sp 3 - hybridized carbon matrix. 24 Due to its insulating characteristic and pronounced mechanical properties, achieved by integration with graphene, GO has been regarded as a /2014/85(4)/045002/9/$ , AIP Publishing LLC

2 Choi, Wu, and Lee Rev. Sci. Instrum. 85, (2014) FIG. 1. (a) FE-SEM image of the AFM probe, AFM cantilever type: NSC36/Ti-Pt-3M-C, and (b) electric field distribution of the cantilever probe versus different position and bias voltage. base material for next-generation thin and flexible electronic and optoelectronic devices. 25, 26 Wei et al. presented a tipbased thermochemical nanolithography method, to control the extent of reduction of GO, and to pattern nanoscale regions of reduced GO (rgo), within a GO sheet. 27 However, if large conductive area is desired, it is difficult to achieve large area rgo on a GO sheet, by the use of a single thermal tip. In order to study the synthesis conditions of graphene oxide, FE-AFM (field emission) local anodic lithography was conducted on a commercial graphene chemical vapor deposition (CVD) single layer graphene, on 285 nm-thickness SiO 2 substrate (Graphene Supermarket, USA). A relative humidity of 42% 45% is maintained during the LAO. When a negative DC bias voltage is applied to the AFM tip, the oxides grow on the graphene surface, which act as an anode. There is a threshold voltage for the anodic oxidation process to start. A high electric field (E > 10 7 V/m) can decompose water molecules adsorbed on graphene into ions (e.g., H +,OH, and O 2 ). Negatively charged oxygen-containing radicals (e.g., OH and O 2 ) can be attracted to the anode, and contribute to the formation of both the surface and underneath oxides. 28 The LAO lithography was performed in ambient air by contact-mode AFM (XE-100, Park systems, USA). An NSC36/Ti-Pt-3M-C cantilever was applied to conduct the experiment, with a spring constant of 0.6 N/m, and a resonant frequency of 170 khz. The FE-SEM image of the tip on the cantilever is shown in Fig. 1(a), and based on the theoretical analysis, the electric field distribution of the cantilever probe versus different position and bias voltage is drawn in Fig. 1(b). It can be seen that a higher tip bias voltage and closer position to the tip can achieve a higher electric field intensity. As shown in Fig. 2(a), in a relative humidity of 45% and bias voltage of 10 V, different scan rates were utilized, to observe the size change of graphene oxide. With the increase in scan rate, which means the decrease in reaction time, the size and friction of the graphene oxide decrease. This also increases the resolution of the nano-pattern. As can be seen in Fig. 2(b), with a relative humidity of 42% and scan rate of 0.01 μm/s, the size and friction change of the graphene oxide decrease, along with the decrease in tip bias voltage. A series of nanostructures with a minimum height of 0.8 nm and a minimum width of 49 nm were created. Based on the above experiments, a certain pattern of characters MNTL was fabricated, with a scan rate of 0.02 μm/s and 10 V tip bias voltage, as shown in Fig. 2(c). In this way, the height and width of the graphene oxide growth can be controlled, by varying the scan rate and tip bias voltage, during oxidation in the ambient conditions. The results confirmed that the nano-patterned graphene oxide can be grown well on the graphene surface, which process could be used to fabricate potential nano electric devices for various applications. One of the drawbacks of the field emission method is the limitation of substrate materials because the substrate should be conductive for the electrical emission between sample and tip. III. DESIGN OF THERMAL CANTILEVER The cantilever device consisted of doped silicon legs, and a heating element that transfers thermal energy to the sample surface. The electrical resistance of the heating area was 3 times higher than that of the two leg areas. Further increase of the ratio in electrical resistivity can be achieved by the use of doping process. Hence, most of the power will be consumed near the region of the heating element, when a pulsed current flows through the microprobe legs. 29 Several factors were considered during the designing of the heater-integrated cantilever, as follows. Soft cantilevers provided low loading forces, which eliminated or reduced tip and media wear. A high-resonant frequency allowed high speed of scanning. In addition, sufficiently wide cantilever legs provided fast cooling, and this cooling in turn resulted in a fast thermal response time. According to the above design considerations, the size of cantilever was set to a length of 350 μm, width of 50 μm, and thickness of 2 μm. It had a stiffness of about 1 N/m and a resonant frequency of 33 khz. The thermal response time of the designed heating element was a few microseconds. 30 Fig. 3(a) shows a schematic diagram of the heater-integrated cantilever, designed for thermal patterning of graphene sheets on various substrates. The principle of AFM-based thermal lithography is shown in Fig. 3(b). In order to find the position of the graphene sheet on a substrate, AFM imaging process was carried out at room temperature under ambient

3 Choi, Wu, and Lee Rev. Sci. Instrum. 85, (2014) FIG. 2. (a) The influence on the graphene oxide of different scan rate. From left to right: 0.01, 0.02, 0.04, 0.06, 0.08, 0.10, 0.12, and 0.14 μm/s, respectively (humidity: 45%, bias voltage: 10 V). (Top) 2D topography image and (bottom) 2D lateral force image. (b) The influence on the graphene oxide of different tip bias voltage. From left to right: 10, 9, 8, 7, and 6 V, respectively (humidity: 42%, scan rate: 0.01 μm/s). When the bias voltage was below 6 V, clear graphene oxide pattern cannot be achieved. (Top) 2D topography image and (bottom) 2D lateral force image. (c) Certain pattern drawing of the graphene oxide, with characters MNTL (humidity: 45%, scan rate: 0.02 μm/s, applied tip bias voltage: 10 V). (Top) 2D and 3D topography image and (bottom) 2D and 3D lateral force image. conditions, in advance of the nano-patterning process. Relative humidity was also controlled, during the experiments. First, the cantilever was placed in the modified AFM, and the heater power was then turned on, to get the desired tip temperature. Tip loading force in the range of nn was applied in a contact mode, under which there was only negligible wear of the thin-films, in room temperature. Finite element analysis (FEA) was performed, to predict the thermal characteristics of the heater-integrated cantilever, as shown in Fig. 4(a). ANSYS has the advantage of FIG. 3. (a) Schematic diagram of the proposed heater-integrated cantilever and (b) the principle of AFM-based thermal lithography process with a heated tip.

4 Choi, Wu, and Lee Rev. Sci. Instrum. 85, (2014) tion of the electrical power applied to the cantilever. Results indicate that the electrical resistance increased until 53 mw and then decreased. The temperature calibration can be carried out most easily by using the single point method. This method starts with a theoretical prediction or measurement of the intrinsic temperature, which is defined as the temperature at which the resistance of the cantilever reaches the maximum value. Initially the resistance value of the heated silicon cantilever increased with temperature. This is ascribed to the increased electron-phonon scattering at high temperature, which reduces the carrier mobility in silicon. At a temperature higher than the intrinsic temperature, the excitation of electrons into the conduction band of the silicon starts to dominate the electron resistance, decreasing the resistance value, with further increase in temperature. The cantilever resistance at the intrinsic temperature, and correlation of this resistance with the predicted intrinsic temperature, represents a single point on the calibration curve. The intrinsic temperature caused by the thermal runaway behavior was estimated as 673 C. According to literatures, 31, 32 the thermal runaway point for silicon cantilevers that are integrated with heaters appears at about 650 C. The simulation results were in good agreement with the experimental results, within a 5% error. FIG. 4. (a) Finite element analysis result of the cantilever and (b) temperature and electrical resistance changes of the heated cantilever, as a function of power applied to the cantilever. coupling analysis, in which a thermal model that describes electrical heating, conduction, and convection cooling, is coupled to a structural model. For precise thermal analysis of the cantilever, material properties that relied on temperature constraints were considered in the FEA simulation. Table I shows the temperature dependent material properties of silicon. The solid node tetrahedral coupled-field elements that were used in the analysis have degrees of freedom, with respect to voltage, temperature, and displacement. In this study, the temperature of the heat element is the leading factor to create a thermochemical reaction between the tip and substrate. However, at the thermal runaway point, a large amount of heat will be dissipated, rather than being transferred into the substrate, which is unfavorable for the thermochemical reaction. Therefore, in our simulation and experiment, various input power values were applied, to determine the optimized input power value to allow the heater to achieve its maximum temperature/resistance, meanwhile keeping it avoid the thermal runaway phenomenon. Fig. 4(b) shows the FEA analysis results of the temperature and electrical resistance changes of the heating element, as a func- IV. FABRICATION OF HEATER-INTEGRATED TIP The heater-integrated cantilevers were fabricated by using a simple micromachining process. A 30 mm 30 mm p-type SOI wafer, with 10 μm-thick device layer, 1 μm-thick buried oxide layer, and 250 μm-thick handle layer, was used as the starting material for the cantilever fabrication. The electrical resistivity of the device layer was about 5 m cm. Fig. 5 shows the fabrication process for the heater-integrated cantilevers. After the standard cleaning processes, a 300 nm thick SiO 2 thin layer was grown on both front and back sides of the wafer, in a wet ambient environment, at 1000 C, by TABLE I. Temperature dependent material properties. Temperature Silicon thermal expansion Thermal conductivity (K) coefficient α (ppm/k) k (W/mk) FIG. 5. Process flow for fabrication of the heater-integrated cantilever.

5 Choi, Wu, and Lee Rev. Sci. Instrum. 85, (2014) using a 20% TMAH solution at 80 C, with the buried oxide of the SOI wafer as the etch-stop layer. During the wet etching of the handle layer, the front side of the SOI wafer was protected with a backside wet etching jig, because it was very difficult to protect the front side with typical masking layers, such as metals or photoresist. Finally, a diluted HF solution was used to remove the buried oxide layer, and the thermal cantilever was then released from the SOI wafer. A SEM image of the fabricated heater-integrated cantilever is shown in Fig. 6. V. EXPERIMENTAL RESULTS FIG. 6. SEM images of the fabricated heater-integrated cantilever. using a furnace. The front SiO 2 layer was patterned in a square shape by photolithography process, and thereby selectively wet etching by a buffered hydrofluoric acid (BHF) solution. Therefore, the patterned SiO 2 layer on the front side of wafer could play a role as mask for wet etching the device (Si layer) in the following process. The device layer was then wet etched about 7 μm with the SiO 2 mask pattern, by using a 20% tetramethylammonium hydroxide (TMAH) solution. A low temperature oxidation process in steam at 950 C was conducted, to further refine the tip shape The low temperature oxidation was carried out for 3 h and 20 min. The patterned SiO 2 layer on the front side only was completely removed by BHF solution, when a thick photoresist layer protected the backside. A metal layer of Cr/Au (5/50 nm) for electrode fabrication was formed by a lift-off process, with AZ 5214 photoresist. A 2 μm thick cantilever was defined by deep reactive ion etching, using a 1.4 μm thick photoresist mask. The 250 μm thick handle layer was wet etched, by A. Preparation of graphene sample Graphene sheets were mechanically exfoliated from natural graphite and then transferred onto a silicon wafer with 300 nm thick SiO 2 layer. The number of graphene layers was experimentally confirmed by the use of both AFM and μraman spectroscopy, as shown in Figs. 7(a) and 7(b), respectively. Cleaving graphene from graphite is therefore a particularly easy way of producing graphene layers, compared to other methods. However, Cheng et al. indicate that graphene sheets generated by the exfoliation method can be contaminated by glue residues, during the transfer of flakes from the tape to the substrate. These contaminants may affect the electrical properties, or the precise patterning, of the graphene sheet. 23, 39 To remove these contaminants, the graphene samples were cleaned in N 2 gas atmosphere at 300 C, for one and a half hours, in a furnace. B. Characterization of heater-integrated cantilevers During the thermal nano-lithography process using the AFM, several critical parameters which influence on the size of patterns should be considered. At first, a proper heating power is required for achieving desired patterns of graphene oxide at nanoscale. In the thermochemical lithography, higher voltages allow the tiny heating element to reach the graphene oxide patterns in shorter time. In this case, the control of duty FIG. 7. Characterization of a monolayer graphene with (a) atomic force microscope and (b) μraman spectrum analyzer.

6 Choi, Wu, and Lee Rev. Sci. Instrum. 85, (2014) FIG. 8. Surface analysis results using the heated AFM tip: (a) 0 W, (b) 24W, and (c) 64 W. cycle for the heater will be one of critical issues to be considered. This is due to heated areas on the graphene surface depends on the heating time and power. A second parameter that affects the size of nano-patterns in thermal lithography process is a contact force. The contact force caused by the Van der Waals force has a nonlinear behavior at a tiny gap distance between the heated tip and the sample surface. 40 The heat generated from the tip area radiates to the sample with a cone shape and a long tip-sample distance will result in a large heating area on the graphene surface. On the contrary, narrow nano-patterns can be achieved with a short tip-sample distance. Since the distance depends on the selection of contact force, the contact force should be considered to improve the resolution of nano-patterns. The gap distance between the heated tip and the graphene surface must be a constant, for reproducible patterning of graphene. Cantilever deflection by temperature rise was observed with a laser vibrometer, and a source meter. The OFV- 534 laser vibrometer was able to measure this deflection, to an accuracy of 2 nm. The thermal runaway point of the heater-integrated cantilever occurred at 53 mw power, and the resulting displacement was about 5.2 nm. Undesired cantilever deflection caused by thermal expansion during the thermal lithography process was compensated for with the Z- axis piezo actuator. However, due to the temperature issue, different input power will cause different cantilever deflections. In order to test the performance of the heated tip when thermal-caused deformation occurs, as well as the accuracy of compensation, the surface scanning of standard sample with various input power was carried out. The surface analysis results with the heated AFM tip are shown in Figs. 8(a) 8(c). It can be seen that the measurement results have no differences, which means that even though there are different cantilever deflections when various input power are applied, the feedback control loop to keep the tip-surface distance is accurate enough to allow the heated tip to operate in a precise way. Various substrates, such as air medium, insulators, and conductors, are evaluated, to understand the relationship between applied power and resistance change in the heater, according to the material properties of the substrate. Fig. 9 shows the experimental result for the case in which the heated cantilevers are suspended in ambient conditions, and their cantilever tips touch the surfaces of slide glass, silicon dioxide, Au, Cr, and silicon layers, respectively. The resistance of the fabricated cantilever for this experiment was about 3430 in ambient, and it was increased up to a maximum 3640, when 20 mw of power was applied to the heaterintegrated cantilever. Below 20 mw applied power, the cantilever resistance increased, as the scattering effect, which is caused by the lattice vibration inside silicon, led to decrease in the mobility of the carrier. Above 20 mw, the cantilever resistance began to decrease, which is due to the thermal excitation of electrons in the conduction band of the silicon. The thermal runaway behavior seen at a temperature above 20 mw FIG. 9. Shift of thermal runaway point, when the heated tip is suspended in the ambient, and the heated tip touches various surfaces.

7 Choi, Wu, and Lee Rev. Sci. Instrum. 85, (2014) is well understood. When different materials were employed as a substrate, the thermal runaway points of the heating cantilever were changed. They were about 20 mw in the ambient, and 31 mw when the heated tip contacted the semiconducting or conducting substrates. The thermal runaway point tended to increase more, as the heated tip contacted substrates with higher thermal conductivities, than it did in the ambient, or when the heated tip made contact with insulators. As the cantilever approached the silicon substrate from afar, the cantilever power dissipation at constant temperature was increased by about 60%. C. Photoresist patterning using thermal lithography based on AFM To generate micro/nano patterns, we built an AFM-based thermal lithography system. The modified XE-100 AFM system for thermal lithography measured the cantilever displacement, to image the surface at an atomic level. At the same time, it generated patterns on a desired local area with the heated tip, and the source meter controlled the heater s temperature, by applying constant power to the heater. Preliminary experiments to evaluate nano-patterning with the heater were conducted by using a 50 nm-thick AZ5214E photoresist layer. In general, an AZ5214E photoresist generates photoacids in unmasked regions, when a substrate is exposed to UV light. A subsequent post-exposure bake (PEB) process thermally activates a crosslinking reaction, in which the previously exposed regions are catalyzed by photoacids. The cross-linked regions become insoluble in an alkali-based developer. Therefore, micro/nano patterns can be simply and easily generated by heat-based chemical reactions. 41 We used an AZ1500 thinner to decrease the photoresist thickness because it is difficult to generate nano patterns with the conventional AZ5214E. A photoresist layer of 50 nm thickness was prepared, by mixing an AZ1500 thinner with the AZ5214E at a ratio of 2:1, and was coated at 6000 rpm, on a 300 nm thick SiO 2 layer of a silicon wafer. The size of patterns that is produced with the thinned AZ5214E would be determined by the heater s scan speed, and its applied power. To evaluate the power dependence of the pattern size, the heated tip was scanned in contact, and the applied power was increased from 30.7 mw to 33.5 mw at 10 nm/s scan speed, 100 nn tip contact force, 18% ambient humidity, and room temperature. Fig. 10 shows the optical microscope images and pattern sizes, according to the applied power and scan speed. Photoresist patterns of 52.6 nm height and 225 nm width were formed, at the power of 30.7 mw. To further investigate the difference of pattern size according to scan speed, we generated various patterns, at scan speeds ranging from 10 nm/s to 50 nm/s (process condition: applied power 33.5 mw, tip contact force 100 nn, relative humidity 18%, and room temperature). A photoresist pattern of 52.6 nm height and 165 nm width was formed at 500 nm/s. The preliminary experiments indicated that the size of the pattern decreased, as the scan speed increased, which caused a time shortage for each chemical reaction. The low resolution of the diluted AZ5214 photoresist was due to its inherent limitation, in supporting a minimal pattern size. FIG. 10. Optical microscope images and photoresist patterns, depending on the applied power and scan speed. The blue line is the relationship of input power and line width (contact force: 100 nn, scan speed: 10 nm/s, applied power: mw, substrate: 300 nm thick SiO 2 layer, relative humidity: 18%). The black line is the relationship of scan speed and line width (contact force: 100 nn, scan speed: nm/s, applied power: 33.5 mw, substrate: 300 nm thick SiO 2 layer, relative humidity: 18%). D. Local oxidation process on Ti and graphene surfaces using a heated AFM tip We also carried out experiments on creating titanium dioxide (TiO 2 ) nano-patterns, using the heated AFM tip and a Ti thin film, to explore the possibility of nano-pattern generation on a graphene surface, by chemical reaction with air. The Ti film was evaporated on a 300 nm thick SiO 2 layer of a silicon wafer, by electron beam evaporation. The heated tip was scanned in contact, by increasing the scan speed from 50 nm/s to 150 nm/s, at 60 mw applied power, 55nN tip contact force, 18% ambient humidity, and room temperature. Fig. 11 shows the experimental result of the TiO 2 patterns generated on the Ti surface, according to scanning speed. The TiO 2 patterns were 1.0 nm in height and 87 nm in width, at 150 nm/s. Also, this result confirmed what we have predicted: the FIG. 11. Experimental results of TiO 2 patterns generated on Ti surface, as a function of scanning speed (contact force: 55 nn, scan speed: nm/s, applied power: 60 mw, substrate: 300 nm thick SiO 2 layer, relative humidity: 18%).

8 Choi, Wu, and Lee Rev. Sci. Instrum. 85, (2014) FIG. 12. (a) AFM images of graphene oxide generated on graphene sheet and the dependence of graphene patterns (contact force: 100 nn, scan speed: μm/s, applied power: 24 mw, substrate: 300 nm thick SiO 2 layer, relative humidity: 42%, temperature: 27 C) and (b) variation of graphene oxide thickness and width as a function of contact force (contact force: nn, scan speed: 1 μm/s, applied power: 24 mw, substrate: 300 nm thick SiO 2 layer, relative humidity: 38%, temperature: 27 C). generated TiO 2 pattern size decreases with the increase of scan speed. Next, the heated tip was scanned on a graphene surface in contact, by increasing the scan speed from 0.5 μm/s to 2μm/s (process condition: tip contact force 100 nn, relative humidity 42%, applied power 24 mw, and temperature 27 C). Fig. 12(a) shows AFM images of graphene oxide generated on the graphene sheet, and the dependence of pattern sizes on the scanning speed, from 0.5 μm/s to 2μm/s. Details of oxidation kinetics for graphene can be found in literatures; however, the temperature dependence of graphene oxide thickness remains unclear. Using the heated tip with a scan speed of 2 μm/s and power of 24 mw, we generated graphene oxide with a height of 2.0 nm and width of 394 nm, indicating that the size of the generated pattern decreases, as the scan speed increases. The noise level during the scanning process was about 0.02 nm in z-scale. In addition, graphene oxide could not be patterned at a scan speed faster than 4 μm/s, since the scan speed of the heater would be so fast, that there would not be enough time for the graphene to react with air. The contact force between the heated tip and the sample is also an impor- tant factor in thermal lithography. The heated tip was scanned in contact, by increasing the tip contact force from 1 nn to 100 nn (process condition: scan rate 1 μm/s, applied power 24 mw, relative humidity 38%, and temperature 27 C). Fig. 12(b) shows the pattern sizes of graphene oxide, according to the contact force from 1 nn to 100 nn. Graphene oxide of 3.6 nm in height and 363 nm in width was produced with a tip contact force of 100 nn and power of 24 mw. We found that the pattern width and tip contact force were inversely related. In future work, as shown in Fig. 13, anarray of micro-heaters can be employed for the parallel operation of cantilever devices, which can enhance the speed of nanopatterning on the graphene surface. VI. CONCLUSION We demonstrated a new graphene nano-patterning method of using a heater-integrated scanning cantilever. The cantilever device that was used to pattern graphene at nanometer scale was optimized by the finite element method, and was fabricated by micromachining. Preliminary nanopatterning experiments with the heated tip were carried out, using a 50 nm thick AZ5214 photoresist, and a Ti thin layer. Based on these experiments, we successfully generated graphene oxide with height of 3.64 nm and width of 363 nm, by the same method. The pattern size decreased, with increase in scan speed and contact force. The proposed thermal lithography process based on AFM can be employed on graphene sheets attached to either conductive or non-conductive substrates. ACKNOWLEDGMENTS This work was supported by the National Research Foundation of Korea (NRF) grant, funded by the Korea government (MEST) (Grant No. 2012R1A2A2A ). FIG. 13. A schematic of an array of micro-heater integrated cantilevers. 1 A. A. Tseng, A. Notargiacomo, and T. P. Chen, J. Vac. Sci. Technol. B 23, (2005).

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