Energy-Delay Space Exploration of Clocked Storage Elements Using Circuit Sizing

Transcription

1 Energy-elay Space Exploraton of locked Storage Elements Usng rcut Szng Mustafa Aktan Svakumar Paramesvaran Joosk Moon Vojn Oklobdzja Electrcal Engneerng Rchardson, TX Electrcal Engneerng Rchardson, TX Electrcal Engneerng Rchardson, TX Electrcal Engneerng Rchardson, TX Abstract Rapd energy-delay exploraton methodology based on crcut szng as appled to clocked storage elements s presented. rcut delay and energy are modeled usng mproved R delay model of a transstor. The accuracy of the model s ncreased by usng Logcal Effort setup accountng for nput sgnal slope and extracton of technology dependent parameters. The mnmal energy-delay curve s generated by optmzng transstor szes for mnmum energy at gven delay targets. Results sho to orders of magntude tme mprovement as compared to H-SPIE n order to generate such curves hle the delay accuracy of the model used remans thn 10 % as compared to H-SPIE. I. INTROUTION omparng dfferent crcut topologes n energy-delay (E-) space s necessary n order to determne optmal trade-offs n terms of performance and poer. To dfferent crcuts may behave dfferently for dfferent speed or energy targets, as llustrated n Fg.1. The E- curves for the to crcuts, shon n Fg.1, are obtaned by tunng transstor szes for the optmum delay for a gven energy budget (or vce versa), under fxed nput/output load and supply voltage assumpton. The best crcut topology of choce s determned by system specfcatons (nput/output load, delay, etc). There are other factors nfluencng the choce such as relablty and process varaton tolerance, but these are not subject of ths paper. In any case, one needs to obtan E- plots of varous crcut topologes under varous condtons and for the gven system specfcatons [13]. Ho to generate these curves thout elaborate smulaton s mportant because there are many possble szng solutons. An exhaustve search on every possble szng s tme consumng and for large crcuts, not possble. onsder as an example a crcut composed of 10 transstors here each transstor can be assgned 10 dfferent szes. Then, there are possble cases to be smulated. locked Storage Elements (SE), namely flp-flops or latches, are employed n the ppelne of hgh-performance processors. The outputs of logc operatons from the prevous stage need to be stored and ll be used as the nputs for the next stage n the next clock cycle [1]. Because of ther excessve number t s mportant to employ hgh-speed but lo-poer SEs to compensate for the hardare overhead accompaned by the ppelned archtecture. The optmal selecton of SEs s determned by the system specfcatons [1]. For fxed nput/output load and supply voltage, energy and delay can be traded aganst each other. Snce the delay and poer of a SE depends on the sze of each transstor, analyss of the Energy-elay metrc s requred []. The problem nvolves transstor/gate szng and developng a A tool for szng dgtal MOS crcuts s not a ne problem [3-5,10]. There has been much effort n szng dgtal MOS crcuts for mnmum delay, area, etc. Methods have been proposed on dfferent levels of abstracton, manly transstor [3,4] and gate-level [5,10]. Transstor-level szng formulaton depends on modelng the transstor as a stched R- netork. Each transstor s replaced by ts correspondng netork and rtng the delay equatons s merely rtng the delay of a dstrbuted R- netork. Gate-level solutons take a smlar approach. Instead of the transstor, the gate s modeled as a stched R- netork. The gate-level approach reduces the number of B has loer energy than A Fg. 1. Energy-delay space A has loer energy than B varables nvolved n the optmzaton problem. The number of varables n optmzaton problems s crtcal snce t has a drect mpact on the soluton tme. Transstor-level methods

2 d d Vout(t) g Vg= g s R s / t f h 1 h 1 h Vn Fg.. Transstor R- model. t 0 load Vout have the advantage of provdng a better soluton due to the flexblty n szng transstors ndependently as opposed to the gate-level approach here the p-n rato s fxed. In ths ork, a quck ay of generatng E- curves for SEs usng transstor szng s gven. Logcal Effort [10] s a smple szng method; hoever t s dffcult to decompose SEs nto smple gates (.e. nand, nor, etc.) hch nvolve feedback paths and dfferent crcut structures exst. Therefore, szng s done at the transstor level hch avods the need to decompose the crcut. Furthermore, transstor level szng gves the flexblty to sze each transstor ndependently (.e. there s no fxed pn rato). The R delay model used s an enhanced model. Parameters are extracted from technology characterzaton by takng nto account sgnal slope effects. The methodology s tested on dfferent structures. It allos the rght selecton of topology and s used to quckly evaluate E- space behavors of varous SE elements. II. TRANSISTOR MOEL USE FOR SIZING A transstor can be modeled as a set of resstances and capactances. Each transstor n the crcut s replaced by ts equvalent R- model. elay s modeled as the calculated R- netork delay (Elmore delay) of the crtcal paths. A transstor M of sze (sze refers to dth of the transstor e assume channel length s fxed and s the same for all transstors n the crcut) s modeled by ts gate/dran/source capactances and channel (dran-to-source) resstance as shon n Fg.. The gate and dran/source capactances for a transstor can be rtten as g = t* and d = s = p* here t and p are the gate and parastc capactances of a unt-sze transstor. If M s NMOS (PMOS), the channel resstance s RM = Rn/M (RM = Rp/M) here Rn (Rp) s the channel resstance of a unt szed NMOS (PMOS) transstor. t 0 t f = R out t (h 1)*h (h 1)*h Fg. 3. Setup for determnng τ n = Rˆ nt consderng nput slopes and varable loads (h =,3, ). onsder the fall delay of the nverter n Fg.. The delay assocated th ths operaton s tf.the unt sze transstor channel resstance hch s used to calculate R can be analytcally calculated from ˆ VTn 4( V ) ln dd V Tn L R n = + 1 V Tn V (1) dd µ ox( VTn) [7]. Equaton (1) does not account for the nput slope and other second order effects. Instead of dervng more complex equatons, technology characterzaton (.e. measurng th smulaton) can be used. The measured (and other parameters) ll reflect second order effects. Fg. 3 shos a Logcal Effort (LE) [11] characterzaton setup for determnng τ n = Rˆ nt by measurng the fall delay of the shaded nverter. Note that the nput-output slopes are made equal by proper loadng. Each nverter has a load of h nverters. By varyng the loadng factor h the parameter of nterest s extracted for dfferent nput/output slope condtons. Parameters obtaned from ths setup account for the nput slope effect on crcut delay. Hoever, equal nput-output slope assumpton of LE s not correct hen crcut s szed for mnmum energy. Hoever, n [14] t s shon that ths ll not ntroduce a sgnfcant error. A. Modelng elay h*h onsder the buffer n Fg. 4. Usng the R- models for transstors, the rse delay can be rtten as the sum of the stage delays as T = R 1+ R () Pluggng n the resstance and capactance values T = Rˆ n/ (( + + ( + ) t) + Rˆ / (( + p ) p ) p + load) (3) Factorng out tme constantτ n = Rˆ nt

3 T = τ n (4) + + load R 1 here = p / t, R = Rˆ p/ Rˆ n, and load s the transstor dth that gves load equvalent capactance. τ n,, and R are technology dependent parametrc constants and can be determned from technology characterzaton. B. Modelng Energy In determnng optmal crcut sze e consder dynamc energy because t has been shon that leakage energy s lnearly proportonal to transstor sze []. Leakage energy shfts the E- curve upards thout changng the shape of the curve. Short-crcut energy s consumed only hen both pmos and nmos are conductng at the same tme. It can be gnored for lo supply-voltage values [15]. Therefore, mnmzaton of energy over the dynamc energy s suffcent. ynamc energy n a MOS crcut s E = s V (5) here s the node capactance, s s the node stchng actvty, and V s the voltage sng (n general equal to supply voltage) at the node. Stchng actvty can be extracted by smulatng the crcut and observng actvty rates at all nodes. The node capactance s composed of the parastc and/or gate capactances of transstors connected to the node. apactance of node s = M j j Node t + p (6) Mk k Node for all transstors M j hose gate s connected to node and all transstors M k hose dran or source s connected to node. Factorng out t gves R = Rn/ 1 = d + d + g + g 1 = ( + )*p + ( + )*t 1 R = Rp/ Fg. 4. Rsng delay crtcal path of a buffer T = R 1 + R = d + d + load = ( + )*p + load load = t + M j M (7) k j Node k Node Assumng constant voltage sng for the hole crcut and re-rtng (5) yelds E = tv s M + j M (8) k j Node k Node It can be shon that (8) reduces to E (9) = r k k here r k s the approprate eghng factor for transstor k.. The optmzaton problem E- curves can be generated by settng a delay target and optmzng for energy. For a SE, the crtcal delay s the data-to-output delay: t -Q [8,1]. The fnal formulaton for mnmzng energy gven a delay target T s Mnmze tv s M + j j Node Subject to rse/fall delay constrants T() (Q) T TLH() (Q) T Mk k Node (10) here the objectve functon and delay expressons are functons of the transstor szes M. Usng the R modelng for delay equatons, the problem turns to be a geometrc programmng problem hch can be solved usng convex optmzaton [4]. Applcaton to a clocked storage element s straghtforard: The crtcal paths for data-to-output delay are dentfed. elays along these paths n terms of the transstors szes are rtten. For energy, node capactances are rtten n terms of transstor szes. Then, gven a delay target T, the problem of (11) s solved for transstor szes th a geometrc programmng solver. III. ESIGN EXAMPLES The effectveness of the methodology s demonstrated on dfferent state-of-the-art SEs taken from lterature, namely the UltraSparc edton of the sem-dynamc Flp-Flop (USPAR) [8] and the transmsson gate master-slave latch (TGMS)[9]. The to examples, USPAR and TGMS, are both used n ndustry and are representatves of hgh-performance and lo-poer desgns, respectvely. For the transstors models e used hgh-performance Predctve Technology Model (PTM) for 45nm technology node [1]. Some key features and extracted optmzaton parameters of the technology node are summarzed n Table I. The SEs are tested usng the setup shon n Fg. 7 [1]. The sze of the clock drver ( ck ) s adjusted to produce a FO

4 M8 5, 6 M5 1 5, 6 N1 7, slope at the clock nput of the SE. The output load (Ld out ) s set to 4 mnmum transstors sze (4x) equvalent capactance. Ths s equvalent to 14 mnmum szed nverters. For all experments, the nput loadng (Ldn) s less than or equal to 9x. TABLE I Technology dependent parameters of PTM technology nodes Tech. (V) mn(nm) τ n (ps) R t(ff) 45nm TABLE II. Transstor szng range for exhaustve search. USPAR = [1:3] = = = [:8] M5 = [1:1] M6 = M7 = [1:3] 4 = [1:6], 3 = *4 9, 0 7, 8 Fg. 5. Ultrasparc flpflop (USPAR) I B B M5 TGMS = [1:4] = [1:5] = [1:8] = [1:6] 4 = [1:3], 3 = *4 8 = [1:5], 7 = *8 = [1:6], 1 = * E- curves for USPAR and TGMS are generated by the szng optmzaton methodology. For USPAR the delay target range as chosen to be 5ps to 65ps th a 1ps nterval. For TGMS t as chosen to be from 60ps to 100ps. Optmzatons resulted n transstor szes for approxmately 40 E- ponts. I1 I3 I SB M6 M7 I1 I3 I4 3, 4 5, 6 M8 M6 7, 8 M7 B M9 0 1 I5 0 1, 9, 0 Fg. 6. Transmsson-gate master-slave latch (TGMS) M9 I5 I4 1, 3, 4 QB QB Fg. 7. Spce smulaton set-up for SEs Usng these szes n spce smulaton, the exact delay and energy values are obtaned for both SEs. To fnd out the correctness of our szng solutons a comparson th exhaustve search s done. The szng ranges used for transstors n exhaustve search are gven n Table II. The szes of transstors not gven n the table are assgned unt sze (.e. mn ). The comparson of results produced by the to methods s shon n Fg. 8. The ponts for TGMS obtaned by exhaustve search are the mnmum energy solutons for each delay pont selected among ~9000 ponts. Smlarly, for USPAR ~5000 ponts are smulated among hch the mnmum energy solutons are plotted n Fg. 8. Both curves are H-SPIE smulaton results. The results obtaned from exhaustve search do not sho a monotonc characterstc. There are jumps and gaps. Ths s because n order to avod excessve run-tme e have restrcted the number of szes a transstor can have. For example transstor of USPAR has a szng range of 1 to 3 mnmum transstor ( mn ) dth th a step of 1 mn. That s, t s alloed to have 3 possble values { mn,* mn,3* mn }. If the step sze as set to 0.5* mn each transstor ould have tce the number of possble szng values. Hoever, f the sze set of all transstor ould have doubled the number of ponts to be smulated ould have ncreased from ~5000 to ~ The search for optmal szes n exhaustve search s done by smulatng each possble szng combnaton of the transstors n H-SPIE. For the proposed method, transstor szes are obtaned from optmzaton and then only the optmzed szngs are smulated th H-SPIE. The optmzer fnds the optmum transstor szes based on the delay and energy models descrbed n Secton. A comparson of the E- plots th model estmates and spce smulaton results for the same transstor szes are gven n Fg. 9. For both SEs, the estmaton agreement th H-SPIE at the lo energy regon s deterorated. Ths s because at ths regon, transstors are close to mnmum sze and optmzaton s not effectve. Nevertheless, for USPAR a maxmum of 10% devaton s observed hereas t s only 5% for the TGMS. For the energy model, e expect more devaton, snce e have not accounted for short crcut and leakage energy. Therefore, the model estmates are expected to sho less energy as compared to H-SPIE as seen n Fg. 9. Furthermore, the unt sze gate capactance t s a non-lnear functon of the voltage. The measured t s an average value. Snce t s a constant factor n the model, an estmaton error n t s drectly reflected to the estmated energy value. Regardless, the optmal transstor szng s acheved and s not affected by these devatons.

5 REFERENES Fg. 8. omparson of E- plots generated by optmzaton and exhaustve search for USPAR and TGMS. 10% error n delay estmate Fg. 9. Estmaton error for the delay/energy model used n optmzaton. IV. ONLUSION A methodology for rapd transstor szng for optmal Flp-Flops confguratons s presented. It s smple, fast, and accurate. It can be appled to any Flp-Flop or crcut topology. espte the naccuraces of the energy and delay models used n optmzaton, the transstor szes found gve comparable results to tme consumng exhaustve search hch s able to fnd optmum szes hen suffcent computng tme s avalable. The total number of spce smulatons s reduced by to orders of magntude hen compared to exhaustve search. AKNOWLEGEMENTS Ths ork has been supported by SR Research Grant No. 008-HJ [1] Gacomotto,., Nedovc, N., Oklobdzja, V. G., The Effect of the System Specfcaton on the Optmal Selecton of locked Storage Elements, IEEE J. Sold State rcuts, vol. 4, no. 6, pp , June 007. [] ao, H. Q., Zeydel, B.R., Oklobdzja, V.G., Energy Optmzaton of Ppelned gtal Systems Usng rcut Szng and Supply Scalng, IEEE Transactons on VLSI Systems, vol. 14, no., pp , February 006. [3] Fshburn, J., unlop, A.: TILOS, A Posynomal Programmng Approach to Transstor Szng, In Proceedngs of the IEEE Internatonal onference on omputer-aded esgn, pp , [4] Sapatnekar, S. S., Rao, V. B., Vadya, P. M., Kang, S. M. An Exact Soluton to the Transstor Szng Problem for MOS rcuts Usng onvex Optmzaton, IEEE Trans. omputer-aded esgn, vol. 1, pp , Nov [5] Josh, S., Boyd. S., An Effcent Method for Large-Scale Gate Szng, IEEE Trans. rcuts Syst. I, vol. 55, no. 9, pp , Oct [6] Uyemura, J.P.: MOS Logc rcut esgn, 4th edton, Sprnger, [7] Stojanovc, V., Oklobdzja, V. G., omparatve Analyss of Master-Slave Latches and Flp-Flops for Hgh-Performance and Lo-Poer Systems, IEEE J. Sold State rcuts, vol. 34, pp , [8] Heald, R., et al., A Thrd-Generaton SPAR V9 64-b Mcroprocessor, IEEE J. Sold-State rcuts, vol. 35, no. 11, pp , Nov [9] Gerosa, G., et al., A. W, 80MHz Superscalar RIS Mcroprocessor, IEEE J. Sold-State rcuts, vol. 9, no. 1, pp , ec [10] Sutherland, I., Sproull, B., Harrs,., Logcal Effort: esgnng Fast MOS rcuts, San Francsco, A: Morgan Kaufmann, [11] Oklobdzja, V. G., Stojanovc, V. M., Markovc,. M., Nedovc, N. M., gtal System lockng: Hgh Performance and Lo-Poer Aspects. 1st edton Ne York: Wley/IEEE Press, 003 [1] Predctve Technology Model, [13] Zyuban, V., Strensk, P.N., Unfed Methodology for Resolvng Poer Performance Tradeoffs at the Mcroarchtectural and rcut Levels, In Proc. Int. Symp. Lo Poer Electroncs and esgn (ISLPE), 00, pp [14] Zeydel, B. R., Oklobdzja, V. G., Methodology for Energy-Effcent gtal rcut Szng: Important Issues and esgn Lmtatons, 16th nternatonal Workshop on Poer and Tmng Modelng, Optmzaton and Smulaton (PATMOS), Montpeller, France, 006. [15] Vratonjc, M., Zeydel, B. R., Oklobdzja, V. G., rcut Szng and Supply-Voltage Selecton for Lo-Poer gtal rcut esgn, 16th nternatonal Workshop on Poer and Tmng Modelng, Optmzaton and Smulaton (PATMOS), Montpeller, France, 006.