N-Channel Lateral DMOS FETs
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1 N-Channel Lateral DMOS FETs SDCY/SDCY Part Number V (BR)DS Min (V) V GS(th) Max (V) r DS(on) Max ( ) C rss Max (pf) t ON Max (ns) SDCY. V GS = V. SDCY. V GS = V. Quad SPST Switch with Zener Input Protection Low Interelectrode Capacitance and Leakage Ultra-High Speed Switching t ON : ns Ultra-Low Reverse Capacitance:. pf Low Guaranteed r V Low Turn-On Threshold Voltage High-Speed System Performance Low Insertion Loss at High Frequencies Low Transfer Signal Loss Simple Driver Requirement Single Supply Operation Fast Analog Switch Fast Sample-and-Holds Pixel-Rate Switching Video Switch Multiplexer DAC Deglitchers High-Speed Driver The SDCY/SDCY monolithic switches features four individual double-diffused enhancement-mode MOSFETs built on a common substrate. These bidirectional devices provide low on-resistance and low interelectrode capacitances to minimize insertion loss and crosstalk. Built on proprietary DMOS process, the SDCY/SDCY utilizes lateral construction to achieve low capacitance and ultra-fast switching speeds. For manufacturing reliability, these devices feature poly-silicon gates protected by Zener diodes. The SDCY is rated to handle -V analog signals, while the SDCY is rated for -V signals. For similar products packaged in TO-6AF (TO-7) and TO-3 (SOT-3) see the SDDE/SST series. Narrow Body SOIC S S SUBSTRATE 3 NC G 3 G D D D 3 G 3 S D G S Top View SDCY SDCY Applications information may also be obtained via FaxBack, request document #767. Document Number: 796 S-9 Rev. H, 3-Apr- FaxBack
2 SDCY/SDCY Gate-Drain, Gate-Source Voltage SD V/ V SD V/ V Gate-Substrate Voltage (SDCY) V/.3 V (SDCY) V/.3 V Drain-Source Voltage (SDCY) V (SDCY) V Drain-Source-Substrate Voltage (SDCY) V (SDCY) V Drain Current ma Lead Temperature ( / 6 from case for seconds) C Storage Temperature to C Operating Junction Temperature to C Power Dissipation a, b : (Package) mw (Each Device) mw Notes: a. SD/SD derate mw/ C above C Static SDCY Limits SDCY Parameter Symbol b Test Conditions b Typ c Min Max Min Max Unit Drain-Source Breakdown Voltage V (BR)DS V GS = V BS = V, I D = na 3 Source-Drain Breakdown Voltage V (BR)SD V GD = V BD = V, I S = na Drain-Substrate Breakdown Voltage V (BR)DBO V GB = V, I D = na, Source Open 3 V Source-Substrate Breakdown Voltage V (BR)SBO V GB = V, I S = A, Drain Open 3 Drain-Source Leakage I DS(off) V GS = V BS = V V DS = V.7 V DS = V. V DS = V.9 Source-Drain Leakage I SD(off) V GD = V BD = V V SD = V. V SD = V. na V SD = V Gate Leakage I GBS V DB = V SB = V, V GB = 3V. Threshold Voltage V GS(th) V DS = V GS, I D = A, V SB = V..... V V GS = V V GS = V 3 Drain-Source On-Resistance r DS(on) VSB = V V GS = V 3 I D = ma V GS = V 6 Resistance Match r DS(on) V GS = V Dynamic V Forward Transconductance g DS = V, V SB = V, I D = ma fs 9 9 ms f = khz Crosstalk f= 3 khz 7 db Switching Turn-On Time Turn-Off Time t d(on). t r VSB = V, V to V, R =.6 IN G t V d(off) DD = V, R L = 6 t f 6 ns Notes: a. unless otherwise noted. DMCA b. B is is the body (substrate) and V (BR) is breakdown. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. FaxBack Document Number: 796 S-9 Rev. H, 3-Apr-
3 SDCY/SDCY 3 On-Resistance vs. Gate-Source Voltage na Leakage Current vs. Applied Voltage ID VGS = VBG = V VGD = VBD = V VGB = V, Drain Open rds(on) On-Resistance ( ) 6 V GS = V V V Leakage na pa pa I S(off) I D(off) I SBO I GSS (Diode) 6 V SB Source-Substrate Breakdown Voltage (V) pa 6 Applied Voltage (V) rds(on) On-Resistance ( ) 6 On-Resistance vs. Temperature I D = ma, V BS = V V GS = V V V V gfs Forward Transconductance 6 Common-Source Forward Transconductance vs. Drain Current V DS = V V BS = V T A = C C C 6 6 Threshold Voltage vs. Substrate-Source Voltage Leakage Current vs. Temperature V GS(th) Gate-Source Threshold Voltage (V) 3 V GS = V DS = V TH I D = ma 6 H L Leakage (na) I V GS = V BS = V, V DS = V I V GD = V BD = V, V SD = V I V GS = V I V SB = V Drain Open I GSS (Diode) I S(off) I D(off) I SBO 7 V BS Body-Source Voltage (V) Document Number: 796 S-9 Rev. H, 3-Apr- FaxBack
4 SDCY/SDCY Capacitance vs. Gate-Source Voltage V DS = V, f = MHz V GS = V BS A A A Body Leakage Current vs. Drain-Body Voltage I D = 3 ma Capacitance (pf) 6 C (GS+SB) C (GS+GD+GB) C (GD+DB) Body Leakage I B na na na pa pa ma C (DG) 6 pa 6 V GS Gate-Source Voltage (V) V BS Body-Source Voltage (V) V DS = V I D = ma Input Admittance V DS = V I D = ma Forward Admittance g fs b is g is b fs.. V DS = V I D = ma Reverse Admittance V DS = V I D = ma Output Admittance b rs.. +g rg g rg b og g og.. FaxBack Document Number: 796 S-9 Rev. H, 3-Apr-
5 SDCY/SDCY Switching Characteristics 7 6 R L ( ) 3 3 V BS = V Output Characteristics V GS = V V 3 V V t f Fall Time (ns) V DS Drain-Source Voltage (V) gos Output Conductance Output Conductance vs. Drain Current V BS = V f = khz V V V DS = V 6 Gate-Source Threshold Voltage (V) V GS(th) 3 Threshold Voltage vs. Temperature V GS = V DS = V TH I D = ma V BS = V V V V. V 6 6 To Scope +V DD + V R L V OUT To Scope V IN V % V IN Input pulse: td, tr < ns Pulse width: ns Rep rate: MHz Sampling Scope tr < 36 ps RIN = M CIN = pf BW = MHz +V DD V OUT V t d(on) t r % % t d(off) t f 9% Document Number: 796 S-9 Rev. H, 3-Apr- FaxBack
N-Channel Lateral DMOS FETs
N-Channel Lateral DMOS FETs (Available Only In Extended Hi-Rel Flow) SDDE-/DE- Part Number V (BR)DS Min (V) V GS(th) Max (V) r DS(on) Max ( ) C rss Max (pf) t ON Max (ns) SDDE-. @ V GS = V. SDDE-. @ V
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