CHAPTER 16 ADVANCED MOS AND BIPOLAR LOGIC CIRCUITS

Transcription

1 CHAPTER 6 ADANCED MOS AND BIPOLAR LOGIC CIRCUITS Chaper Oulne 6. Implcaons of Technology Scalng 6. Dgal IC Technology, Logc Crcu Famly and Desgn Mehodologes 6.3 Pseudo NMOS Logc Crcus 6.4 Pass Transsor Logc Crcus 6.5 Dynamc MOS Logc Crcus 6.6 Bpolar and BCMOS Dgal Crcus 6

2 6. Implcaons of Technology Scalng Moore s Law A new echnology s developed for every ~3 years due o cos and speed requremen The rend was predced more han 40 years ago by Gordon Moore For every new echnology generaon: The mnmum lengh s reduced by a facor of.44 and he area s reduced by a facor of The cos s reduced by half or he crcu complexy s doubled Devce scalng generally decreases he parascs and enhances he operang speed The operang power s reduced The curren echnology node advances no deep submcron Issues n deep submcron echnologes have o be aken no accoun for crcu desgns 6

3 Scalng Implcaons 6 3

4 elocy Sauraon Long channel devces: Drf velocy: v n = n E Elecrc feld n he channel: E = v DS /L Shor channel devces: elocy sauraes a a crcal feld E cr wh v sa 07 cm/s The v DS a whch velocy sauraes s denoed by DSsa DSsa = E cr L = v sa L/ n DSsa s a devce parameer The I Characerscs Long channel devces W Sauraon curren: D ncox ( GS ) L Shor channel devces For GS < DSsa : same as long channel devces For GS > DSsa : I Dsa W ncox GS ) L WCoxvsa GS ( DSsa DSsa DSsa 6 4

5 Curren Equaon for elocy Sauraon For v GS DSsa and v DS DSsa, he dran curren s gven by D C n ox W L DSsa v GS DSsa ( DS ) The curren s reduced from he predcaon of a long channel devce The dependence on v GS s more lnear raher han quadrac Four regons of operaon: cuoff, rode, sauraon and velocy sauraon Shor channel PMOS ranssors undergo velocy sauraon a he same value of v sa The effecs on PMOS are less pronounced due o lower mobly and hgher DSsa 6 5

6 Subhreshold Conducon The devce s no complee off n deep submcron devces as v GS < The subhreshold curren s exponenally proporonal o v GS : D = I s exp(v GS /n T ) I s a problem n dgal IC desgn for wo reasons: Such curren leads o nonzero sac power dsspaon for CMOS logcs May cause undesrable dscharge of capacors n dynamc CMOS logcs The Inerconnec The wdh of he nerconnec scales down wh he CMOS echnology The meal wre s no longer an deal shor Seres parasc ressance may cause undesrable volage drop and excess delay Parasc capacance o ground may lead o speed degradaon and addonal dynamc power 6 6

7 6. Dgal IC Technology, Logc Crcu Famles, and Desgn Mehodologes Logc Crcu Famles Classfed by fabrcaon echnology: CMOS, Bpolar, BCMOS, GaAs Mos wdely logc crcu echnology s CMOS arous logc famles are mplemened n CMOS echnology Syles for Dgal Sysem Desgn Assemble he sysem usng sandard IC packages of varous levels of complexy Applcaon specfc IC (ASIC) wh cusomzed dgal desgn when large volume s requred Semcusom desgn: Gae array (unconneced logc gaes) wh fnal cusomzed meallzaon sep Feld programmable gae array (FPGA) can be programmed by he user 6 7

8 6.3 The Pseudo NMOS Logc Crcus The olage Transfer Characersc (TC) The funcon of he nverer s o nver he logc value of s npu sgnal The volage ransfer characersc s used o evaluae he qualy of nverer operaon TC parameers OH : oupu hgh level OL : oupu low level IH : he mnmum value of npu nerpreed by he nverer as a logc IL : he maxmum value of npu nerpreed by he nverer as a logc 0 Transon regon: npu level beween IL and IH 6 8

9 NMOS Inverer Crcus A smple nverer crcu s composed of a NMOS and a load The load can be realzed by a ressor or anoher NMOS devce Ressve Load NMOS Inverer Enhancemen Load NMOS Inverer Depleon Load NMOS Inverer Pseudo NMOS Inverers Use a PMOS ranssor as he load Does no suffer from body effec Drecly compable wh complemenary CMOS crcus Area and delay penales arsng from he fan n n complemenary CMOS gae s reduces Pseudo NMOS Inverer 6 9

10 Sac Characerscs Load curve represens a much lower sauraon curren k n s usually greaer han k p by a facor of 4 o 0 A raoed ype logc wh r k n /k p The logc s ypcally operaed n wo exremely cases: v I = 0: v O = OH = v I = : v O = OL > 0 (nonzero OL for pseudo NMOS) The TC can be derved based on DN and DP : DN DN kn( vi ) kn ( vi ) v O for v v O O v I for v O v (sauraon) I (rode) DP DP ( ) p k k p ( )( for v v O O ) ( (sauraon) v O ) for v O (rode) 6 0

11 Dervaon of he TC Assume n = p = for he dervaons Regon I (Segmen AB): Regon II (Segmen BC): Regon III (Segmen CD): Regon I (Segmen DE): Sac Characerscs: OH ) / )( ( n p OL k k ) / )( / ( p n p n IL k k k k ) ( / 3 p n IH k k OL IL L NM IH OH H NM / p n M k k OH O v ) ( ) ( I O v r v ) ( ) ( ) ( I I O r v v v ) ( ) )( ( ) ( O O O O I v v v v v r 6

12 Dynamc Operaon Deermne PLH : The analyss s dencal o he CMOS nverer and he oupu capacance C s charged by PMOS pc 7 where / 3 PLH k p Deermne PHL : The dscharge curren s DN DP whle DP s ypcally neglgble as r s large PHL nc k n where n p for a large value of r and PHL s much larger han PLH 4 Desgn of Pseudo NMOS Inverer p Deermne rao r = k n / k p The larger he value of r, he lower OL s and he wder he nose margns are A larger r ncreases he asymmery n he dynamc response Usually, r s seleced n he range of 4 o 0 Deermne (W/L) n and (W/L) p A smaller (W/L) o keep he gae area small and hus oban a small value for C A smaller (W/L) o keeps I sa of Q P and sac power dsspaon low Larger (W/L) raos n order o oban low P and hus fas response 3 / 3 4 r r n 6

13 Gae Crcus Idencal o PDN of CMOS gae excep for he load devce The rao r deermnes all he breakpons of he TC The larger he value of r, he lower OL s and he wder he nose margns are A larger r ncreases asymmery n he dynamc response Usually, r s seleced n he range of 4 o 0 Deermne (W/L) n and (W/L) p Smaller (W/L) for small area and capacance Smaller (W/L) for lower I sa of Q P and sac power dsspaon Larger (W/L) raos n order o oban low P and hus fas response Concludng Remarks In pseudo NMOS, NOR gaes are preferred over NAND gaes n order To use mnmum sze devces Pseudo NMOS s parcularly sued for applcaons n whch oupu remans hgh mos of he me Sac power dsspaon can be reasonably low The oupu ransons ha maer would presumably be hgh o low ones where he propagaon delay can be made as shor as necessary 6 3

14 6.4 Pass Transsor Logc Crcus Desgn of Pass Transsor Logc (PTL) Crcus Usng seres and parallel combnaons of swches The swches are conrolled by npu logc varables o connec he npu and oupu nodes Can be mplemened by a sngle NMOS ranssor or CMOS ransmsson gae Every crcu node has a all mes a low ressance pah o or ground Y ABC Y A( B C) 6 4

15 Operaon wh NMOS Transsor as he Swch Pass ranssor wh oupu hgh ( poor ) The oupu node refers o he source ermnal of he NMOS Durng he chargng process, Q s n sauraon ncreases wh v O due o body effec, resulng n a large PLH OH =, reducng he gae nose mmuny Pass ranssor wh oupu low ( good 0 ) The npu node refers o he source ermnal of he NMOS No body effec The oupu node can be dscharged compleely OL = 0 6 5

16 Resorng he Oupu Level The crcu based approach by addng a feedback loop wh Q R The PMOS Q R urns on by v O (= 0 ) o resore he sgnal loss a v O = The PMOS Q R s urn off by v O (= ) when v O = 0 Operaon s more nvolved han appears due o he posve feedback Q R has o be a weak PMOS ranssor n order no o play a major role n he crcu operaon The alernave approach by process echnology The sgnal loss s due o he hreshold volage of he NMOS devces Threshold adjusmen by on mplanaon o make zero hreshold devces Subhreshold conducon becomes sgnfcan for zero hreshold devces 6 6

17 The Use of CMOS Transmsson Gaes as Swches PMOS and NMOS are n parallel wh complemenary conrol sgnal Boh NMOS and PMOS provde chargng/dschargng curren Good logc level wh OH = and OL = 0 The complexy, slcon area and load capacance are ncreased Body effec has o be aken no accoun o evaluae DN and DP 6 7

18 The Equvalen Ressance of he Transmsson Gae The equvalen ressance of Q N : For v O n : DN k ( For v O n : DN 0 and R Neq The equvalen ressance of Q P : For v O p : DP k For v O p : DP k n p ( n p v ) O Emprcal formula for he equvalen ressance: R TG ) and and R R Peq Neq k p k ( n ( ( p )( vo ) ( vo ) p.5 ( k) ( W / L) n v v O p n O ) and v R O ) Peq k vo ( p )( vo ) ( vo ) p 6 8

19 Calculaon of Propagaon Delay n he Sgnal Pah The sgnal pah conanng mulple ransmsson gaes can be modeled by ressors and capacors The model s n a form of an RC ladder nework The propagaon delay s gven by Elmore delay formula as P 0.69[( Cou CTG) RP ( CTG Cn)( RP R TG )] * Elmore delay formula s gven by P [ CR C( R R ) C3( R R R )...] 6 9

20 Pass Transsor Logc Crcu Examples Fnal Remarks Advanages of CMOS ransmsson gae over pass ranssor logc wh NMOS devces Logc level: good and 0 No level resorng echnque needed Dsadvanages of CMOS ransmsson gae over pass ranssor logc wh NMOS devces Slcon area and complexy: an addonal npu requres one NMOS and one PMOS devces Complemenary conrol sgnal requred Propagaon delay: more capacve loadng from he MOSFETs 6 0

21 6.5 Dynamc MOS Logc Crcus Prncple of Dynamc Logc Crcus Rely on he sorage of sgnal volage on parasc capacances a ceran crcu nodes The crcus need o be perodcally refreshed Manan he low devce coun of pseudo NMOS whle reducng he sac power dsspaon o zero Operaon of Dynamc Logc Crcus Precharge phase: Q p on and Q e off charge he oupu node o Evaluaon phase: Q p off and Q e on selecvely dscharge he oupu node hrough PDN 6

22 Nondeal Effecs Nose margn: Snce IL IH n, he resulng nose margns are NM L n and NM H n Asymmerc nose mmuny (poor NM L ) Oupu volage decay due o leakage effecs: When PDN s off, leakage curren wll slowly dscharge he oupu node The leakage s from he reversed based juncons and possbly he subhreshold conducon Charge sharng: Some of he nernal nodes n PDN wll share he charge n C L even he PDN pah s off Can be solved by addng a permanenly urn on ranssor Q L a he cos of sac power dsspaon 6

23 Domno CMOS Logc Problem wh cascadng dynamc logc gaes: errors cuased by undesrable premaure dscharge Precharge Evaluaon Y M Y Premaure dscharge Domno CMOS logc: A dynamc logc wh a sac CMOS nverer conneced o s oupu The oupu o he followng sages s 0 durng he precharge phase Can allevae he premaure dscharge problem 6 3

24 A cascade of Domno CMOS logc: Each sage has o wa for he rsng edge from he precedng sage The rsng edge propagaes hrough a cascade of gaes Concludng Remarks Advanages of Domno logc: small area, hgh speed operaon, and zero sac power dsspaon Dsadvanages of Domno logc: Asymmerc nose margn Leakage ssue Charge sharng Dead me: unavalably of oupu durng precharge phase 6 4

25 Basc Prncple 6.6 Bpolar and BCMOS Logc Crcus Hgh speed s acheved by operang all ranssor ou of sauraon o avod sorage me delays By keepng he logc sgnal swngs relavely small (~0.8) o reduce chargng/dschargng me One of he npus s conneced o a reference volage R When v I s greaer han R by abou 4 T v O = CC IR C and v O = CC When v I s smaller han R by abou 4 T v O = CC and v O = CC IR C. Imporan feaures of ECL: The dfferenal naure of he crcu makes less suscepble o pcked up nose Curren drawn from he power supply remans consan durng swchng no curren spkes The oupu sgnal levels are boh referenced o CC and can be made sable wh CC = 0 Some means are needed o make he oupu sgnal levels compable wh hose a he npu The avalably of complemenary oupu consderably smplfes logc desgn wh ECL 6 5

26 The Basc Gae Crcu Bas nework: The nework generaes a reference volage R of.3 a room emperaure R s made o change wh T n a predeermned manner so as o keep nose margns consan R s also made relavely nsensve o varaons n he power supply volage EE 6 6

27 Dfferenal npu sage: Parallelng npu ranssors (Q A and Q B ) are used o mplemen OR and NOR funcons Curren n R E remans approxmaely consan over he normal range of operaon Ressors o connec each npu ermnal o negave supply can leave unused npus open Emer follower oupu sage: On chp loads are no ncluded as he gae drves a ransmsson lne ermnaed a he oher end n mos of hgh speed logc Emer followers shf he level by one v BE drop he shfed levels are cenered around R Provde low oupu ressance and large curren drvng capably Separae power supply prevens couplng of power supply spkes from oupu o gae crcu ECL Famles ECL 00K: P 0.75ns and P D 40mW PDP = 30pJ ECL 0K: P ns and P D 5mW PDP = 50pJ A varan of ECL (curren mode logc) has become popular n LSI applcaons 6 7

28 olage Transfer Characerscs Defnon of uny gan: Q A (or Q R ) s conducng % (or 99%) of I E Assumng he v BE = 0.75 a a emer curren of ma for an ECL ranssor OR Transfer Curve I I E E Q R Q A 99 BE IL IH R BE Q for v I < IL : I E R Q BE Q T ln99 5m R A E EE R 4 ma OL OH NM L IL OL.435 (.77) NM H OH IH 0.88 (.05)

29 NOR Transfer Curve I I E E Q R Q A 99 BE IL IH Q BE Q T ln99 5m R A for v I < IL : OH = 0.88 for v I = IH : IH BE Q EE A I E 4. 7mA RE v O for v I = OH : OH BE Q EE A I E 4. 58mA RE OL NM L IL OL.435 (.758) NM H OH IH 0.88 (.05)

30 Manufacurers Specfcaons ILmax =.475 IHmn =.05 OLmax =.630 OHmn = Fan Ou I IL = (.77+5.)/50 = 69 ma I IH = ( )/50 + 4/0 = 6 ma Inpu currens are small and oupu ressance s small fan ou of ECL no lmed by logc level The fan ou s lmed by consderaons of crcu speed Operang Speed Speed s measured by he delay of s basc gae and by he rse and fall mes of oupu waveforms Usng emer follower as he oupu sage, he ECL gae exhb shorer rse me han s fall me Sgnal Transmsson ECL s parcularly sensve o rngng because he sgnal levels are so small One soluon s o keep he wres very shor wh respec o he sgnal rse/fall me he reflecons reurn whle he npu s sll rsng/fallng If greaer lenghs are needed, hen ransmsson lnes mus be used he reflecon s suppressed wh proper ermnaon 6 30

31 Power Dsspaon Gae power dsspaon of unermnaed ECL reman relavely consan ndependen of he logc sae No curren spkes are nroduced on he supply lne The need for supply lne bypassng n ECL s no as grea as n TTL Thermal Effecs The reference volage R s.3 a room emperaure R s made o change wh T n a predeermned manner so as o keep he nose margns almos consan A demonsraon of he hgh degree of desgn opmzaon of hs gae crcu Wred OR Capably The emer follower oupu sage of he ECL famly allows wred OR for logc desgn The OR funcon s mplemened by wrng he oupu of several gaes n parallel 6 3

32 The BCMOS Crcus BCMOS Technology combnes Bpolar and CMOS Crcus on one IC chp CMOS (low power, hgh npu mpedance, wde nose margns) + Bpolar (hgh curren drvng capably) Parcularly useful for logc wh large fan ou (large capacve load) The Smple BCMOS Inverer Cascadng each of he Q N and Q P devces of he MCOS nverer wh an npn ranssor Inpu hgh: Q N urns on and he dran curren flows no he base of Q as he base curren The nal dscharge curren DN + b DN v O drops Q N n deep rode wh D = 0 as v O drops o BEon ( 0.7) OL = BEon Inpu low: Q P urns on and he dran curren flows no he base of Q as he base curren The nal dscharge curren (b + ) DP v O ncreases Q P n deep rode wh DP =0 as v O drops o BEon ( 0.7) OH = BEon Q and Q are operang n nonsauraon mode and wll no urn on smulaneously Reduced nose margn due o smaller logc swng No base dscharge pah o speed up he urn off of Q and Q long urn off delays. 6 3

33 BCMOS Inverer wh Bleeder Ressors Ressor R and R are added o provde base dscharge pahs for Q and Q urn off Inpu hgh: Q N urns on and Q P urns off provdes dschargng curren hrough Q N and Q v O s dscharged below BEon hrough Q N and R mproved nose margn Pullng v O from BEon o ground s raher slow due o he hgh mpedance pah (Q N and R ) Inpu low: Q N urns off and Q P urns on provdes chargng curren hrough Q P and Q A dc curren pah exs from o ground hrough Q P and R when Q s off v O can only be charged up o DS,P BEon by Q R and R ake some of he dran currens of Q P and Q N away from he bases of Q and Q and hus slghly reduce he oupu chargng/dschargng currens of he gae R and R are ypcally mplemened by MOSFET Q R and Q R Q R conducs only when v I s hgh R o dscharge Q Q R conducs only when v I s low R o dscharge Q 6 33

34 BCMOS Inverer R crcu R s conneced o he oupu node raher han reurnng o ground: The problem of sac power dsspaon s now solved R now funcons as a pull up ressor, pullng he oupu node volage up o 6 34

35 Dynamc Operaon The dealed analyss of he dynamc operaon s raher complex Propagaon delay s esmaed by he me requred o charge and dscharge a load capacance C Such an approxmaon s jusfed n cases where C s relavely large Usually he case for applcaon of BCMOS nverers C R L W k PLH R B R D B BEon R P P p D / ) ( / C R L W k PHL D B R D B BEon R n BEon N n D / / 6 35

36 BCMOS Logc Gaes BCMOS logc gaes can be mplemened followng he same approach as he nverers The bpolar poron smply funcons as an oupu sage Q N and Q P are replaced by pull down nework and pull up nework 6 36