Tolerance Band Controller for a Three-Level Four-Quadrant Converter Including DC Link Balancing

Transcription

1 4 35h Annual I Power lecroncs Specalss Conference Aachen, Germany, 4 Tolerance Band Conroller for a ThreeLevel FourQuadran Converer Includng DC Lnk Balancng Joachm Böcker Insue of Power lecroncs and lecrcal Drves Unversy of Paderborn, Germany boecker@lea.upb.de Absrac Tolerance band or hyseress conrol s usually appled only for smple converers wh one swchng elemen. The paper shows how o generalze he approach for more complex converer sysems lke a hreelevel fourquadran converer and o benef from he hgh effecve loop gan of he conrol approach. Sae graphs are used for he desgn of he conroller. For he hreelevel converer, he sae graph s able o manage boh asks of curren conrol and DC lnk balancng. The conroller can be realzed usng a FPGA. A processor or a mcroconroller s obsolee. v c1 c I. INTRODUCTION Tolerance band or hyseress conrol s a very powerful approach because of he hgh effecve loop gan, whch resuls n an excellen dynamc response and good robusness. The orgnal hyseress approach can easly be appled o converer conrol problem, f here exss one conrol objecve, e.g. he curren, and only one swchng command, e.g. as wh smple buck or boos converers. More complex converers as parallel, seres or mullevel opologes requre he coordnaon of several swchng commands. Ths s usually done by convenonal conrols and phaseshfed (nerleaved) pulse wdh modulaed (PWM) command sgnals. The socalled peak curren mode conrol [1] s a combnaon of PWM and a one sde hreshold swchng ha s also able o manage nerleafed swchng of parallel converers, bu whch nvolves problems of nsably regons. However, hough no obvous, s possble o apply a generalzed olerance band conrol approach also o such complex converer srucures and rean he advanages of a hgh conrol loop gan, cf. [] [3] [4] [5] [6]. Ths paper shows how o desgn a olerance band conroller for he curren conrol of a hreelevel fourquadran converer. The concern of hs paper s no only o presen he parcular conroller as a resul, whch may be also found by a more adhoc approach, bu o clearly descrbe he desgn process makng use of sae graphs. Desgnng conrollers by means of sae graphs seems o be a promsng mehod also for oher converer opologes. II. v v L L S 1 S THRLL FOURQUADRANT CONRTR The crcu dagram of a hreelevel fourquadran converer s shown n Fg. 1. From he vewpon of conrol desgn, he converer can be replaced by deal swches. ach converer leg s represened by a swch wh hree possble swchng saes ha are denoed as, and. Ths resuls n oal n nne dfferen converer saes as shown n Table I. Supposng equal DC lnk volages as durng normal operaon, v 1 v v /, fve dfferen converer volages can be realzed, whch are v v v,,,, v. v 1 v v Fg. 1. Threelevel fourquadran converer and s dealzed represenaon as a swchng nework The zero volage can be realzed by hree, he volages ± v / by wo dfferen swchng saes, whch are called redundan saes /4/$. 4 I. 438

2 4 35h Annual I Power lecroncs Specalss Conference Aachen, Germany, 4 III. TOLRANC BAND CONTROL STRATGY The curren conrol s usually only he nner loop of a cascaded conrol, whch has o regulae, for example, he DC lnk volage v v1 v. The ouer volage conroller deermnes he curren demand * for he nner curren conrol. Ths paper, however, focuses only on he nner curren conrol, see Fg.. The man dea of a olerance band curren conrol s prey clear: When he curren hs he lower hreshold of he olerance band, he converer volage has o be decreased, when he curren hs he upper hreshold, he volage has o be ncreased, Fg. 3. These evens of hng he upper and lower hreshold wll be represened by he bnary sgnals and, respecvely: TABL I SWITCHING STATS AND RSULTING CONRTR OLTAG * S 1 S * c volage * conroller c ncrease decrease ( > * ) ( < * ) ncrease decrease v 1 v v 1 v v 1 v v1 v Fg. 3. Tolerance band conrol curren conroller Fg.. Cascaded conrol srucure ncrease S decrease However, some addonal ssues have o be consdered: The swchng acons should be dsrbued equally o he swches n order o ge balanced swchng losses. The swchng acons should be used economcally o reduce swchng losses or o ge a small curren rpple, respecvely. The DC lnk capacors have o be charged equally. The requremens can be fulflled, f only he smalles possble drvng volages are used along he npu nducance L, and, f redundan saes are alernaed o balance he load of he swches and he DC lnk. If, for example, he npu volage somewhere n he range beween v / and v, only he converer volages v { v /, v } should be used o ncrease or decrease he curren, resp., because hese volages resuls n smalles curren slopes: d L v d L v v s v v / v v s > < The volage v can be realzed only by he sae ( S 1, S ) ( ), so here s no choce, bu he represenaon of v / should alernae beween ( ) and ( ) for balanced load. Ths leads o a perodc sequence of four saes, whch s ( ) ( ) ( ) ( ) L ( ) If ha sequence s arranged as a cycle, a sae graph as shown whn Fg. 4 resuls. The ransons beween he saes are rggered by he evens and, respecvely. Such a conrol specfcaon usng a sae graph s much clearer han a nesed fhenelse consrucon of a sequenally programmed algorhm. Anoher cycle can be consruced for he range < v < v /. Ths cycle makes use of all hree represenaons of he zero volage, see Fg. 5. The cycles for he oher wo ranges v / < v < and v < v < v / are smlar o he presened ones, so ha hey are omed here. In oal, here exs four such cycles for he parcular ranges of he npu volage. The ask s now o lnk he four separae cycles. One road could be o swch from one cycle o anoher by measurng he npu volage v. Bu ha can also be done observng only he curren conrol error whou any volage measuremen: Afer a swchng acon, he curren wll usually be forced back no he olerance band and wll h he oppose hreshold nex. If hs s no he case,.e. he curren remans ousde he olerance band or hs he same hreshold wce, ndcaes ha he chosen volage s no longer suffcen and has o be swched over o one of he adjacen cycles. For praccal realzaon, he me delays of he sysem have o be aken no accoun so ha he 439

3 4 35h Annual I Power lecroncs Specalss Conference Aachen, Germany, 4 procedure s as follows: A mer wll be sared, when he curren hs a hreshold ( or ). If, afer wang an amoun of me T, he same hreshold s sll exceeded or s h a second me, he sgnals and wll be se. These sgnals are used as rggers o swch over o an adjacen cycle as shown n Fg. 6. If he oppose hreshold s h nex, he mer wll be rese and sared agan. S v v / Fg. 4. Cycle for v / < v < v and resulng swchng sequence S 1 S v / Fg. 5. Cycle for < v < v / and resulng swchng sequence v v < v < v < v < v v < v < < v < v Fg. 6. Curren conrol sae graph wh lnked man cycles 44

4 4 35h Annual I Power lecroncs Specalss Conference Aachen, Germany, 4 I. DC LINK BALANCING As poned ou above, he conrol of he DC lnk volage v v1 v s ask of an ouer conrol loop, whch makes use of he demanded curren * of he nner loop. However, s no possble o esablsh an ouer conrol ha regulaes boh volages v 1 and v, because only one demand * s avalable for he nner loop. So, balancng of he volages v 1, v has o be done by he nner conrol and mus be negraed no he curren conroller, see Fg. 7. The dea s o exchange he redundan saes n he cycles, f he DC lnks are no longer balanced. Two sgnals are nroduced o ndcae ha he volage devaon s larger han an allowed hreshold ud. I s necessary o consder he sgn of he curren for correc compensaon: v* d c volage * conroller ( v1 v > v ) ( > ) ( v1 v < v ) ( < ) ( v v > v ) ( < ) ( v v < v ) ( > ) 1 c 1 curren conroller S Wh hese sgnals, he sae graph s modfed as shown n Fg. 8. The resul s ha redundan saes are no longer alernaed unl a balanced saus s reesablshed. (The ransons rggered by T m whn Fg. 8 wll be explaned n he nex secon.) c1 v Fg. 7. Cascaded conrol srucure wh DC lnk balancng. CONSIDRATION OF MINIMUM ON/OFF TIM So far, he converer was modeled as wo deal swches ha can arbrarly be swched on and off. One real effec o be consdered are he mnmum on and off mes of he ncluded IGBT: Afer swchng a converer leg, a mnmum me has o be passed by before successve swchng s allowed whou damage of he ranssors. These mnmum on/off me T m s n he range of a mcrosecond. In mos cases, no problems arse from hs resrcon, even f wo sae graph ransons are rggered whn a me perod shorer han T m. The reason s ha successve swchngs are dsrbued o dfferen converer legs so ha he mnmum on/off me s no volaed. There are, however, some excepons: In he case < v < v /, for example, he sae graph operaes n one of s nner cycles (Fg. 6). If he npu volage s assumed o be close o v /, he saes ha realze zero volage (.e. ( ), ( ), ( ) ) wll be acvaed only for very shor me perods so ha, e.g., he wo ransons ( ) ( ) ( ) wll occur very rapdly n sequence. In ha case, he ranssors of he rgh converer leg would be urned on and off very fas n conflc wh mnmum on/off me. Tha problem can be solved by a modfcaon of he sae graph. If, e.g., he sae ( ) s held for a me longer han T m whou any exernal even, he followng sae ( ) wll be skpped, see Fg. 8. Noe ha he ranson s only an nernal sae ranson, no converer swchng wll occur. The resulng swchng sequence s hen T m, ( ) ( ) ( ) ( ) T m T m Tm Tm Fg. 8. Curren conrol sae graph ncludng balancng of he DC lnk and consderaon of mnmum on/off me 441

5 4 35h Annual I Power lecroncs Specalss Conference Aachen, Germany, 4 S 1 S * * 1ms Fg. 9. Measuremen resul of he olerance band conrol whch avods he problem of swchng he same nverer leg n rapd successon. However, s no helpful o skp he sae ( ) n all cases. If he npu volage s close o zero, makes sense o use ( ) and ( ) as zero volages o avod oher mnmum on/off me resrcons n ha range. I. MASURMNT RSULTS The conroller was realzed usng a feld programmable gae array (FPGA) wh some analogue comparaors. A dgal sgnal processor or a mcroconroller s no requred. The conroller was esed wh a laboraory se up of a hreelevel nverer. Fg. 9 shows ha he conroller works well as was desgned. In parcular, can be seen from ha fgure, ha hs conroller s able o cope even wh a raher low swchng frequency as abou 1 Hz whn Fg. 9, whch s usually he doman of PWM approaches. RFRNCS [1] W. Huang, A new conrol for mulphase buck converer wh fas ransen response, Appled Power lecroncs Conference and xposon, Anahem, Calforna, 1. [] J. Böcker, Dscreeven Converer Conrol, uropean Conf. on Power lecroncs and Applcaons, Toulouse, 3. [3] K. Rauma, O. Laakkonen, J. Luukko, O. Pyrhönen, Comparson of alernave mplemenaons of DTC usng FPGA crcus, 1h uropean Conf. on Power lecroncs and Applcaons, Toulouse, 3. [4] I. Takahash, Y. Ohmor, Hghperformance drec orque conrol of an nducon moor, I Transacons on Indusry Applcaons, ol. 5, No., March/Aprl [5] M. Meyer, A. Sonnenmoser, A hyseress curren conrol for parallel conneced lnesde converers of an nverer locomove, uropean Conf. on Power lecroncs and Applcaons, Brghon [6] S. Salama, S. Lennon, Overshoo and lm cycle free curren conrol mehod for PWM nverers, uropean Conf. on Power lecroncs and Applcaons, Florence, 1991, pp II. CONCLUSION I has been shown how o generalze he olerance band conrol mehod for converer sysems wh several swchng saes. Sae graphs are an approprae mehod o desgn and o specfy he conroller. The conroller can be realzed usng programmable logc lke FPGA. A dgal sgnal processor or a mcroconroller s no necessary. The olerance band conrol s able o manage even low swchng frequences, whch are usually he doman of PWM approaches. 44