Directions for simulation of beyond-cmos devices. Dmitri Nikonov, George Bourianoff, Mark Stettler

Transcription

1 Directions for simulation of beyond-cmos devices Dmitri Nikonov, George Bourianoff, Mark Stettler

2 Outline Challenges and responses in nanoelectronic simulation Limits for electronic devices and motivation for non-chargebased computing Simulations of spintronic devices Nonequilibrium spin devices and power dissipation New architectures QCA etc. 2

3 Transistor Nanotechnology Beyond CMOS, in this talk 3

4 Phonon-limited Mobility in Nanowires Phonon Mobility (cm 2 /Vs) () NMOS Diameter (A) 28 8 Diameter Gate Voltage (V) The phonon-limited mobility is degraded in narrow wires over the planar MOSFET mobility. R. Kotlyar et al., Appl. Phys. Lett. 84, 527 (24), Intel. 4

5 Carbon nanotubes and carbon nanoribbons Mobility increases with size CNR have better mobility for the same size CNT have better mobility for the same bandgap B. Obradovic et al., Appl. Phys. Lett. 88, 422 (26), Intel. 5

6 Nanoelectronic simulations Challenge: find the best option for the nanoelectronic transistor Response: Industry is far along in simulation of the ultimate CMOS. Nanowire, carbon nanotube, and carbon nanoribbon transistors have been looked at. None was found to have a decisive advantage vs. CMOS. Directions: - predict a nanoelectronic device dramatically better than CMOS - prove when quantum transport simulation necessary (i.e. drift-diffusion-schrodinger-poisson breaks down) 6

7 Outline Challenges and responses in nanoelectronic simulation Limits for electronic devices and motivation for non-chargebased computing Simulations of spintronic devices Nonequilibrium spin devices and power dissipation New architectures QCA etc. 7

8 Quantum limit of MOSFET a E b E b a w w Size limited by quantum confinement Switching time determined by the time-energy uncertainty relation Energy set by the barrier height ~kt; margin against thermal noise. Zhirnov et al., Proc. IEEE 9, 934 (23). 8

9 MOSFET is optimal electronic switch Gate Delay (ps) Switching. Energy. (fj)... Limit... L GATE (µm) L GATE (µm) Current CMOS device scaling towards the ideal limit * Data courtesy of Robert Chau (Intel) Limit 9

10 Additional technology entries Electric charge FET, D structures, RTD, SET Electric dipole ferroelectric, QCA Magnetic dipole/spin spintronics, magnetic QCA, nanomagnetics Light intensity photonics Mechanical position nano-electro-mechanical systems (NEMS) Orbital state metal-insulator, order-disorder, ion or molecular orbit Quantum state quantum interference, RSFQ (superconducting, entanglement quantum computing

11 Energy vs. Length Spintronics achieves a lower power dissipation limit. NEMS and photonics are too power hungry. Nikonov, Bourianoff, presentation at the workshop Silicon Nanoelectronics and Beyond III, Dec. 25.

12 Computing limits and non-charge based logics Challenge: choose best non-charge-based device Response: All electronic devices obey the limit arising from fundamental physics. Need to explore non-charge-based devices to continue scaling. Many risky and immature alternative logics. No clear advantage vs. CMOS. Directions: - tools for simple simulation of non-charge-based devices - predict which options are dramatically better than electronics 2

13 Outline Challenges and responses in nanoelectronic simulation Limits for electronic devices and motivation for non-chargebased computing Simulations of spintronic devices Nonequilibrium spin devices and power dissipation New architectures QCA etc. 3

14 Quantum transport through tunneling barrier CoFe MgO CoFe current Nonequilibrium Green s functions for transport. Split spin bands in ferromagnets. Neglect charge density - linear potential (for now). Obtain tunneling magnetoresistance. Intel (unpublished). Similar to approach of Yanik, Klimeck, and Datta, Purdue U., cond-mat/6537 4

15 DOS and occupation Vsd=.6V anti-parallel Plots - electron density, density of states, spin polarization. White line top of the barrier 5

16 Current and spin current Vsd=.6V antiparallel The P and AP cases differ by a subtle balance of the positive and negative parts of current spectrum. 6

17 Tunneling magnetoresistance AP P Predicts decrease of TMR vs. voltage, Intel (unpublished) Predicts inverse magnetoresistance!!! which is observed experimentally. Promising for memory. More importantly spin-electronic interface. 7

18 Simulation of spintronic devices Challenge: simulation capability to enable experimental demonstration of a practical spintronic device Response: Spintronics seems promising re. energy efficiency. Many experimental devices: memories commercialized, logic immature. Theoretical treatments too optimistic, do not include all relevant aspects. Directions: - general spintronic simulator, handling most of proposed devices - achieve predictive power by close interaction with experimentalists - to filter device options, not to discover new phenomena 8

19 Outline Challenges and responses in nanoelectronic simulation Limits for electronic devices and motivation for non-chargebased computing Simulations of spintronic devices Nonequilibrium spin devices and power dissipation New architectures QCA etc. 9

20 Momentum and spin relaxation in bulk GaAs Dyakonov-Perel and Elliott-Yafet mechanisms Material / system Bulk 3K Bulk 3K Bulk 3K equilibration time X -3 sec X - sec 8-5 X -2 sec Length scale Comments Reference electron E.Pop et.al Journal of equilibration HeatTransfer, Vol 28, time July 26 4nm - 26 nm Phonon equilibration time Accoustic phonons Bulk 3K 7.6 X -4 sec 7.6 nm Free Electrons Spin Systems Si 28 lattice at 3K X -3 sec electron bound to defect Si 28 lattice at 3K.5 X 3 sec Nuclear spin Diamond films at 3K.5 X 3 sec 5 nm Nitrogen - vacancy pair E.Pop et.al Journal of HeatTransfer, Vol 28, July 26 A Balandin CNSI FENA Seminar, UCLA February 22, 25 A Balandin CNSI FENA Seminar, UCLA February 22, 25 T.D. Ladd, et.al, PHYSICAL REVIEW B 7, 44 (25) T.D. Ladd, et.al, PHYSICAL REVIEW B 7, 44 (25) Gaebel et. al, Nature Physics, Vol 2, June 2 Spin relaxation is slower than momentum relaxation. easier to isolate spin from the environment, out of equilibrium. Bourianoff, Nikonov, Gargini, tbp Solid State Electronics (27). 2

21 Stages of computation z B clock y x Clock field aligns spins gives them B meas z y x spin splitting Apply field to induce state splitting to measure spin (magnetic STM)* B set z B y x Set the initial value +z or -z Switch the state from +z to -z z B clock y x Spin magnitude decreased - time for another clocking No energy barrier between the computational states! z y x *Spin state destroyed by reading. Not used till next clock cycle. Only few spins are read. 2

22 Clocking is the main source of dissipation GB c s tanh ˆ c = x 2 2kT B need to stop after this time and refresh the magnitude of spin τ c =./ γ ( Ω ) 33ns l B c Energy dissipated as spin aligns to clocking field h/2 E = k T tot = 4.8 B 5 τ tanh() τ kt B sw c S + S - B x S τ eq τ c t t Nikonov, Bourianoff, Gargini, J. Superconductivity and Novel Magnetism, v. 9, #6, 497 (26). 22

23 Nonequilibrium computing Challenge: can one lower power dissipation via operation out of thermal equilibrium? Response: Lower power dissipation is predicted in a simple spin model. Directions: - practical device scheme - prove advantage vs. electronic logic 23

24 Outline Challenges and responses in nanoelectronic simulation Limits for electronic devices and motivation for non-chargebased computing Simulations of spintronic devices Nonequilibrium spin devices and power dissipation New architectures QCA etc. 24

25 Quantum cellular automata logic gates A= MAJORITY A B C Out B= AND Out= C= OR NOT A= Out= States in cell oriented along the preferred axis, e.g. easy axis of a magnet 25

26 Magnetization in LSMO on STO Example of inverter and a majority gate. Operation determined by the material, shape and stress anisotropy. Intel (unpublished) 26

27 Non-traditional architectures Challenge: what are the architectures of choice for beyond CMOS devices Response: QCA architecture is one example specifically suited for spintronics. Directions: - simulator with device-circuit link for beyond CMOS devices - which architecture brings out the best performance of noncharge-based devices - any application-specific architecture for beyond CMOS that is dramatically better than CMOS The (computer) clock is ticking!!! 27

28 BACKUP SLIDES

29 Mass and bandgap Trend: bandgap proportional to mass. Similar values in semicon., carbon nanotubes, nanoribbons. 7.5nm nm.4nm.6nm carbon nanotube diameter graphene nanoribbon width 29

30 Which material is best for on-current? V =.7V t ox = var ε = 6 L = nm 7.5nm nm.4nm.6nm Optimal material depends on device parameters. <3x variation of drive current. carbon nanotube diameter graphene nanoribbon width 3

31 Requirements to logic devices Performance (esp. speed) Architectural compatibility w CMOS (connections, voltage range) Stability and reliability CMOS process compatibility (fabricated on the same wafer) Room temperature operation Energy efficiency (energy per switching) Low sensitivity to parameters (e.g. fabrication variations) Scalability (remains functional as size shrinks) * After ITRS 23 3

32 Evaluation of Alternative Logic Two numbers: Performance potential Risk 3 = better than CMOS 3 = solutions known 2 = comparable to CMOS 2 = concept feasible = worse than CMOS = no known solution International Technology Roadmap for Semiconductors

33 Correlated metal oxides 3d orbitals of transition metal z y x e g t 2g hopping localized x 2 -y 2 3z 2 -r 2 zx yz xy Materials like LaSrMnO3 exhibit Ferroelectric, ferromagnetic, antiferromagnetic, metal, insulator regions depending on stoichiometry 33