MC MC MC MC145408

Size: px

Start display at page:

Download "MC MC MC MC145408"

Duane Adams
6 years ago
Views:

1 SEIOUTO TEHIAL ATA Order this document by 0/ EIA E and ITT. These devices are silicon gate OS Is that combine both the transmitter and receiver to fulfill the electrical specifications of EIA Standard E and ITT.. The drivers feature true TTL input compatibility, slew rate limiting outputs, 00 Ω power off source impedance, and output typically switching to within % of the supply rails. The receivers can handle up to ± while presenting to kω impedance. Hysteresis in the receivers aid in the reception of noisy signals. y combining both drivers and receivers in a single OS chip, these devices provide efficient, low power solutions for both EIA E and. applications. These devices offer the following performance features: rivers ± to ± Supply ange 00 Ω Power Off Source Impedance Output urrent Limiting TTL and OS ompatible Inputs river Slew ate ange Limited to 0 /µs aximum eceivers ± Input ange to kω Input Impedance 0. of Hysteresis for Enhanced oise Immunity TTL and OS ompatible Outputs Available river/eceiver ombinations evice rivers eceivers igure o. of Pins Alternative EIA devices to consider are: Three Supply Single Supply 0 ( x ) 0 ( x ) 0 ( x ) with Power own 0 ( x ) with Power own 0 ( x ) with Power own AHIE Y EESALE SEIOUTO, I. P SUIX PLASTI IP ASE P SUIX PLASTI IP ASE W SUIX SO PAAE ASE W SUIX SO PAAE ASE E S SUIX SSOP ASE 0 OEI IOATIO 0P Plastic IP 0P Plastic IP 0P Plastic IP 0P Plastic IP 0W SO Package 0W SO Package 0W SO Package 0W SO Package 0S SSOP E / T0000 otorola, Inc. OTOOLA

2 OTOOLA 0 IES/ EEIES x Tx x x Tx x x Tx O I O O I O O I 0 PI ASSIETS (IP, SO, A SSOP) 0 IES/ EEIES x Tx x Tx x Tx x Tx O I O I O I O I 0 0 IES/ EEIES x Tx Tx x Tx Tx x Tx O I I O I I O I 0 x Tx x Tx x Tx x Tx x 0 I O I O I O I O I O Tx 0 IES/ EEIES UTIOAL IAA ES POTETIO + O x. kω kω Tx 00 Ω + LEEL SHIT.0. I. EEIE IE + AHIE Y EESALE SEIOUTO, I.

3 ASOLUTE AXIU ATIS (oltages referenced to, except where noted) ating Symbol alue Unit Supply oltage ( ) Input oltage ange x xn I In I 0. to to. 0. to +.0 to + 0. to + urrent rain per Pin I ± 00 ma Power issipation P W Operating Temperature ange TA 0 to + Storage Temperature ange Tstg to + 0 ELETIAL HAATEISTIS (All polarities referenced to = 0, TA = 0 to + ) Supply oltage Quiescent Supply urrent (Outputs Unloaded, Inputs Low) Parameter Symbol in Typ ax Unit = + = = + I ISS I... to to 00 0 EEIE ELETIAL SPEIIATIOS (oltage polarities referenced to = 0, = +, =, TA = 0 to +, = +, ± 0%) Input Turn On Threshold O = OL haracteristic Symbol in Typ ax Unit x xn This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. or proper operation it is recommended that out and in be constrained to the ranges described as follows: igital I/O: river Inputs (I): ( I ). eceiver Outputs (O): ( O ). EIA I/O: river Outputs (Tx): ( Tx Txn ). eceiver Inputs (x): x xn + ). eliability of operation is enhanced if unused outputs are tied off to an appropriate logic voltage level (e.g., either or for I, and for x). AHIE Y EESALE SEIOUTO, I. on... µa Input Turn Off Threshold O = OH Input Threshold Hysteresis = on off Input esistance ( ) x xn ( + ) x xn off 0.. hys in. kω High Level Output oltage Iout = µa x = to * (O On) Iout =.0 ma OH.... Low Level Output oltage x = + to + * (O On) Iout = + ma Iout = + ma OL * This is the range of input voltages as specified by EIA E to cause a receiver to be in the high or low. OTOOLA

4 IE ELETIAL SPEIIATIOS (oltage Polarities eferenced to = 0, = +, =, TA = 0 to +, = +, ± 0%) igital Input oltage Logic 0 Logic Input urrent I = I = Output High oltage I = Logic 0, L = kω = +.0, =.0 = +.0, =.0 = +.0, =.0 Output Low oltage* I = Logic, L = kω = +.0, =.0 = +.0, =.0 = +.0, =.0 Input urrent (igure ) Output Short ircuit urrent = +, = Tx Shorted to ** Tx Shorted to ± *** haracteristic Symbol in Typ ax Unit I In I In Tx Txn Tx Txn Tx Txn Tx Txn IL IH IIL IIH OH OL ±.0 Zoff 00 Ω * oltage specifications are in terms of absolute values. ** Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation limits will be exceeded. *** This condition could exceed package limitations. IS ± ± 0 ± 0 ± 00 SWITHI HAATEISTIS ( = +, ± 0%, = +, =, TA = 0 to + ; See igures and ) rivers Propagation elay Time Tx Low to High L = kω, L = 0 p High to Low L = kω, L = 0 p AHIE Y EESALE SEIOUTO, I. haracteristic Symbol in Typ ax Unit tplh tphl µa ma ns Output Slew ate inimum Load L = kω, L = 0 p ( = to, = to ) S ± ± 0 aximum Load L = kω, L = 00 p ( =, =, = ) /µs eceivers (L = 0 p) Propagation elay Time Low to High tplh 0 0 ns High to Low tphl 0 0 Output ise Time tr 0 00 ns Output all Time tf 0 00 ns OTOOLA

5 IES I Tx tphl EEIES x O 0% 0% 0% tf 0% tphl 0% 0% tf tplh I Tx I I I I Tx Tx Tx Tx igure. Power Off Source esistance Illustrated for 0 tr tplh tr + 0 OH OL + 0 OH OL in = ± out in I IES AHIE Y EESALE SEIOUTO, I. Tx + tshl Slew ate = tslh or tshl + tslh igure. Switching haracteristics igure. Slew ate haracteristics igital Power Supply PI ESIPTIOS The digital supply pin, which is connected to the logic power supply (+. maximum). round round return pin is typically connected to the signal ground pin of the EIA E connector (Pin ) as well as to the logic power supply ground. ost Positive evice Pin The most positive power supply pin, which is typically + to +. ost egative evice Pin The most negative power supply pin, which is typically to. x xn eceive ata Input Pins These are the EIA E receive signal inputs. A voltage between + and + is decoded as a space, and causes the corresponding O pin to swing to ground (0 ). A voltage between and is decoded as a mark, and causes the corresponding O pin to swing to. O On ata Output Pins These are the receiver digital output pins which swing from to. Each output pin is capable of driving one LSTTL input load. OTOOLA

6 I In ata Input Pins These are the high impedance digital input pins to the drivers. Input voltage levels on these pins are LSTTL compatible and must be between and. A weak pull up on each input sets all unused I pins to, causing the corresponding unused driver outputs to be at. Tx TXn Transmit ata Output Pins These are the EIA E transmit signal output pins, which swing from to. A logic at the I input causes the corresponding Tx output to swing to. A logic 0 at the I input causes the corresponding Tx out to swing to. The actual levels and slew rate achieved will depend on the output loading (L L). APPLIATIO IOATIO POWE SUPPLY OSIEATIOS igure shows a technique to guard against excessive device current. The diode prevents excessive current from flowing through an internal diode from the pin to the pin when < by approximately 0. or greater. This high current condition can exist for a short period of time during power up/down. Additionally, if the + supply is switched ZLT x 0 off while the + is on and the off supply is a low impedance to ground, the diode will prevent current flow through the internal diode. The diode is used as a voltage clamp, to prevent from drifting positive to, in the event that power is removed from (Pin ). If power is removed, and the impedance from the pin to ground is greater than approximately kω, this pin will be pulled to by internal circuitry causing excessive current in the pin. If by design, neither of the above conditions are allowed to exist, then the diodes and are not required. ES POTETIO ES protection on I devices that have their pins accessible to the outside world is essential. High static voltages applied to the pins when someone touches them either directly or indirectly can cause damage to gate oxides and transistor junctions by coupling a portion of the energy from the I/O pin to the power supply buses of the I. This coupling will usually occur through the internal ES protection diodes. The key to protecting the I is to shunt as much of the energy to ground as possible before it enters the I. igure shows a technique which will clamp the ES voltage at approximately ± using the ZLT. Any residual voltage which appears on the supply pins is shunted to ground through the capacitors. This scheme has provided protection to the interface part up to ± 0 k, using the human body model test AHIE Y EESALE SEIOUTO, I x O Tx I x O Tx x I O Tx I x O Tx I x 0 O Tx I igure OTOOLA

7 PAAE IESIOS P SUIX PLASTI IP ASE 0 -A- -T- SEATI T SEATI 0 E A PL E 0. (0.00) T A PL L P SUIX PLASTI IP ASE 0 J PL 0. (0.00) T. IESIOI A TOLEAI PE ASI Y.,.. OTOLLI IESIO: IH.. IESIO L TO ETE O LEA WHE OE PAALLEL.. IESIO OES OT ILUE OL LASH. I A E J L IHES I AX S S S ILLIETES I AX S... S S HAEE OTOU OPTIOAL.. IESIO L TO ETE O LEAS WHE OE PAALLEL.. IESIOI A TOLEAI PE ASI Y.,.. OTOLLI IESIO: IH. AHIE Y EESALE SEIOUTO, I. 0. (0.00) T A L J PL OTE 0. (0.00) T IHES ILLIETES I I AX I AX A E 0.00 S. S S. S J L 0.00 S. S OTOOLA

8 W SUIX SO PAAE ASE 0 T SEATI A 0 X 0.00 (0.) T A S S X X A 0X P 0.00 (0.) T SEATI 0.00 (0.) T A S S X J W SUIX SO PAAE ASE E 0 P 0.00 (0.) X. IESIOI A TOLEAI PE ASI Y.,.. OTOLLI IESIO: ILLIETE.. IESIOS A A O OT ILUE OL POTUSIO.. AXIU OL POTUSIO 0.0 (0.00) PE SIE.. IESIO OES OT ILUE AA POTUSIO. ALLOWALE AA POTUSIO SHALL E 0. (0.00) TOTAL I EXESS O IESIO AT AXIU ATEIAL OITIO. ILLIETES IHES I I AX I AX A S 0.00 S J P IESIOI A TOLEAI PE ASI Y.,.. OTOLLI IESIO: ILLIETE.. IESIOS A A O OT ILUE OL POTUSIO.. AXIU OL POTUSIO 0. (0.00) PE SIE.. IESIO OES OT ILUE AA POTUSIO. ALLOWALE AA POTUSIO SHALL E 0. (0.00) TOTAL I EXESS O IESIO AT AXIU ATEIAL OITIO. AHIE Y EESALE SEIOUTO, I. X J X ILLIETES IHES I I AX I AX A S 0.00 S J P OTOOLA

9 S SUIX SSOP ASE 0 0 L 0.0 (0.00) T SEATI L/ PI IET 0. (0.00) T X E 0. (0.00) T U S S A U S 0 H U J ETAIL E 0. (0.00) ETAIL E ÇÇÇ ÉÉÉ SETIO J W AHIE Y EESALE SEIOUTO, I.. IESIOI A TOLEAI PE ASI Y.,.. OTOLLI IESIO: ILLIETE.. IESIO A OES OT ILUE OL LASH, POTUSIOS O ATE US. OL LASH O ATE US SHALL OT EXEE 0. (0.00) PE SIE.. IESIO OES OT ILUE ITELEA LASH O POTUSIO. ITELEA LASH O POTUSIO SHALL OT EXEE 0. (0.00) PE SIE.. IESIO OES OT ILUE AA POTUSIO/ITUSIO. ALLOWALE AA POTUSIO SHALL E 0. (0.00) TOTAL I EXESS O IESIO AT AXIU ATEIAL OITIO. AA ITUSIO SHALL OT EUE IESIO Y OE THA 0.0 (0.00) AT LEAST ATEIAL OITIO.. TEIAL UES AE SHOW O EEEE OLY.. IESIO A A AE TO E ETEIE AT ATU W. ILLIETES IHES I I AX I AX A S 0.0 S H J J L otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in otorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any license under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/Affirmative Action Employer. fax is a trademark of otorola, Inc. How to reach us: USA / EUOPE / Locations ot Listed: otorola Literature istribution; JAPA: ippon otorola Ltd.: SP, Strategic Planning Office,, P.O. ox 0, enver, olorado or 00 ishi otanda, Shagawa ku, Tokyo, Japan. 0 fax : AX0@ .sps.mot.com TOUHTOE 0 0 ASIA/PAII: otorola Semiconductors H.. Ltd.; Tai Ping Industrial Park, otorola ax ack System US & anada OLY 00 Ting ok oad, Tai Po,.T., Hong ong. HOE PAE: USTOE OUS ETE: 00 OTOOLA /

High Performance Silicon Gate CMOS

SEIONDUTOR TEHNIAL DATA High Performance Silicon Gate OS The 5/7H32A is identical in pinout to the LS32. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible