What is the Cost of Determinism? Cedomir Segulja, Tarek S. Abdelrahman University of Toronto

Size: px
Start display at page:

Download "What is the Cost of Determinism? Cedomir Segulja, Tarek S. Abdelrahman University of Toronto"

Transcription

1 What is the Cost of Determinism? Cedomir Segulja, Tarek S. Abdelrahman University of Toronto

2 Source: [Youtube] [Intel]

3 Non-Determinism Same program + same input same output This is bad for Testing Too many interleaving to test Debugging Hard to debug when behavior is not repeatable Selling CAD tools users expect each run to produce the same circuit

4 Determinism 1 2 Is good, but costly What is the fundamental cost of determinism? What is this cost across various execution environments? Determinism in the field Deterministic Schedulers Maximum Slowdown DMP [Devietti et al. 2009] 1.7x Kendo [Olszewski et al. 2009] 1.6x Grace [Berger et al. 2009] 3.6x CoreDet [Bergan et al. 2010] 10x Calvin [Hower et al. 2011] 1.7x RCDC [Devietti et al. 2011] 1.7x Dthreads [Liu et al. 2011] Conversion [Merrifield and Eriksson 2013] Parrot [Cui et al. 2013] 3.8x RFDet [Lu et al. 2014] 2.6x Source: [Bergan et al. 2011] and the respective papers *Only to show that determinism comes at a cost, and not to be used for a direct comparison (different features, benchmarks, # threads, etc.) 4x 5x

5 What is Determinism? Property that requires observing the same output whenever program runs with the same input SyncOrder determinism [Lu and Scott 11] Require the same program result and same order of synchronization More flexible than internal determinism Still greatly eases testing [Cui et al. 13] We assume data-race-freedom Determinism during debugging is needed But the cost of determinism matters the most in production External SyncOrder Internal All data races are bugs [Boehm 2008, S. Adve 2010, Marino et al. 2010, Lucia et al. 2010, ] Data races in general do not help performance [Boehm 12]

6 What is the impact of enforcing a fixed synchronization order on program execution time?

7 Schedule-Record-Replay Framework 1 2 application schedule application thread 1 thread 2 scheduler serial replayer hybrid round-robin dynamic-a dynamic-s perturber architectures idle small perturbations recorder NUMA DVFS background processes

8 barnes cholesky fft fmm lu_cb lu_ncb ocean_cp ocean_ncp radiosity radix raytrace_splash2x volrend water_nsquared water_spatial blackscholes bodytrack dedup facesim ferret fluidanimate raytrace_parsec streamcluster swaptions vips Normalized Execution Time Replayer Force threads to wait only when absolutely necessary under the schedule And do so with as little overhead as possible Non-deterministic execution vs. Non-deterministic execution with the replayer s overhead

9 Schedules When does a thread pass its turn? At the end serial After each synchronization operation round-robin After each instruction/store dynamic-a/dynamic-s After N instructions hybrid N = 100,000 No reduced serial mode Deterministic Schedulers Grace [Berger et al. 2009] Dthreads [Liu et al. 2011] Conversion [Merrifield and Eriksson 2013] Parrot [Cui et al. 2013] Kendo [Olszewski et al. 2009] RCDC [Devietti et al. 2011] RFDet [Lu et al. 2014] DMP [Devietti et al. 2009] CoreDet [Bergan et al. 2010] Calvin [Hower et al. 2011] Schedule serial round-robin round-robin round-robin dynamic dynamic dynamic hybrid hybrid hybrid

10 Platform 8-core Xeon E SPLASH-2 and PARSEC benchmarks, 8 threads Deterministic slowdown deterministic execution time non deterministic execution time Data races in general do not help performance [Boehm 12] 15 benchmarks had races, performance degradation in only 3 barnes (11%), radiosity (5%), raytrace_parsec (8%)

11 parsec splash Benchmarks serial round-robin dynamic-s dynamic-a hybrid barnes cholesky fft fmm lu_cb lu_ncb ocean_cp ocean_ncp radiosity radix raytrace volrend water_nsquared water_spatial blackscholes bodytrack dedup facesim ferret fluidanimate raytrace streamcluster swaptions vips average slowdown maximum slowdown

12 For this set of benchmarks and our platform, and implementation overhead set aside, the fundamental cost of determinism is small.

13 What is the performance cost of insisting on the same schedule across different environments?

14 Schedule-Record-Perturb-Replay Framework 1 2 application schedule application thread 1 thread 2 scheduler serial replayer hybrid round-robin dynamic-a dynamic-s perturber architectures idle small perturbations recorder NUMA DVFS background processes

15 Perturber Small perturbations (context switches, thread migrations, page faults) Simulate first order effects by inserting small delays (μs and ms) Background processes Spawn additional threads and control their work to sleep ratio Dynamic voltage and frequency scaling (DVFS) Use Linux s cpufreq system to explore different DVFS policies Non-uniform memory access (NUMA) Spread threads over two NUMA nodes Asymmetric architectures Use DVFS to create asymmetry [Shelepov et al. 2009]

16 Metric Deterministic slowdown deterministic execution time non deterministic execution time Same conditions during both runs, for example deterministic execution time with background processes non deterministic execution time with background processes

17 parsec splash Benchmarks Quiet Small perturbations Backgroud proc. DVFS Asym. Arch. NUMA balanced unbalanced balanced unbalanced auto manual 4/4 1/7 barnes cholesky fft fmm lu_cb lu_ncb ocean_cp ocean_ncp radiosity radix raytrace volrend water_nsquared water_spatial blackscholes bodytrack dedup facesim ferret fluidanimate raytrace streamcluster swaptions vips avg. slowdown max. slowdown

18 Insisting on the same schedule in the presence of skewed conditions can slow down execution by a factor of almost 2x.

19 Conclusions Employed the schedule-record-replay framework to divorce implementation overhead from the fundamental cost of enforcing deterministic execution Fundamental cost of determinism is small (4% on avg., 33 % max.) There is room for lowering overheads in current deterministic systems Measured this fundamental cost across a range of execution environments The cost of raises to almost 2x when threads face skewed conditions Do we need a more relaxed definition of determinism? Quantified various sources of non-determinism Deterministic logical clocks are not deterministic (not only due to the performance counters imperfections [Weaver et al. 2013])

20 Thank you!

Impact of Thread and Frequency Scaling on Performance and Energy in Modern Multicores: A Measurement-based Study

Impact of Thread and Frequency Scaling on Performance and Energy in Modern Multicores: A Measurement-based Study Impact of Thread and Frequency Scaling on Performance and Energy in Modern Multicores: A Measurement-based Study Armen Dzhagaryan Electrical and Computer Engineering The University of Alabama in Huntsville

More information

DMP. Deterministic Shared Memory Multiprocessing. Presenter: Wu, Weiyi Yale University

DMP. Deterministic Shared Memory Multiprocessing. Presenter: Wu, Weiyi Yale University DMP Deterministic Shared Memory Multiprocessing 1 Presenter: Wu, Weiyi Yale University Outline What is determinism? How to make execution deterministic? What s the overhead of determinism? 2 What Is Determinism?

More information

UC Santa Barbara. Operating Systems. Christopher Kruegel Department of Computer Science UC Santa Barbara

UC Santa Barbara. Operating Systems. Christopher Kruegel Department of Computer Science UC Santa Barbara Operating Systems Christopher Kruegel Department of Computer Science http://www.cs.ucsb.edu/~chris/ Many processes to execute, but one CPU OS time-multiplexes the CPU by operating context switching Between

More information

Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism

Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism Nima Honarmand, Nathan Dautenhahn, Josep Torrellas and Samuel T. King (UIUC) Gilles Pokam and Cristiano Pereira (Intel) iacoma.cs.uiuc.edu

More information

Region-Based May-Happen-in-Parallel Analysis for C Programs

Region-Based May-Happen-in-Parallel Analysis for C Programs Region-Based May-Happen-in-Parallel Analysis for C Programs Peng Di, Yulei Sui, Ding Ye and Jingling Xue School of Computer Science and Engineering, UNSW Australia {pengd, ysui, dye, jingling}@cse.unsw.edu.au

More information

Parallelization of Multilevel Preconditioners Constructed from Inverse-Based ILUs on Shared-Memory Multiprocessors

Parallelization of Multilevel Preconditioners Constructed from Inverse-Based ILUs on Shared-Memory Multiprocessors Parallelization of Multilevel Preconditioners Constructed from Inverse-Based ILUs on Shared-Memory Multiprocessors J.I. Aliaga 1 M. Bollhöfer 2 A.F. Martín 1 E.S. Quintana-Ortí 1 1 Deparment of Computer

More information

Scheduling I. Today Introduction to scheduling Classical algorithms. Next Time Advanced topics on scheduling

Scheduling I. Today Introduction to scheduling Classical algorithms. Next Time Advanced topics on scheduling Scheduling I Today Introduction to scheduling Classical algorithms Next Time Advanced topics on scheduling Scheduling out there You are the manager of a supermarket (ok, things don t always turn out the

More information

CPU Consolidation versus Dynamic Voltage and Frequency Scaling in a Virtualized Multi-Core Server: Which is More Effective and When

CPU Consolidation versus Dynamic Voltage and Frequency Scaling in a Virtualized Multi-Core Server: Which is More Effective and When 1 CPU Consolidation versus Dynamic Voltage and Frequency Scaling in a Virtualized Multi-Core Server: Which is More Effective and When Inkwon Hwang, Student Member and Massoud Pedram, Fellow, IEEE Abstract

More information

Saving Energy in the LU Factorization with Partial Pivoting on Multi-Core Processors

Saving Energy in the LU Factorization with Partial Pivoting on Multi-Core Processors 20th Euromicro International Conference on Parallel, Distributed and Network-Based Special Session on Energy-aware Systems Saving Energy in the on Multi-Core Processors Pedro Alonso 1, Manuel F. Dolz 2,

More information

Scheduling I. Today. Next Time. ! Introduction to scheduling! Classical algorithms. ! Advanced topics on scheduling

Scheduling I. Today. Next Time. ! Introduction to scheduling! Classical algorithms. ! Advanced topics on scheduling Scheduling I Today! Introduction to scheduling! Classical algorithms Next Time! Advanced topics on scheduling Scheduling out there! You are the manager of a supermarket (ok, things don t always turn out

More information

LSN 15 Processor Scheduling

LSN 15 Processor Scheduling LSN 15 Processor Scheduling ECT362 Operating Systems Department of Engineering Technology LSN 15 Processor Scheduling LSN 15 FCFS/FIFO Scheduling Each process joins the Ready queue When the current process

More information

Che-Wei Chang Department of Computer Science and Information Engineering, Chang Gung University

Che-Wei Chang Department of Computer Science and Information Engineering, Chang Gung University Che-Wei Chang chewei@mail.cgu.edu.tw Department of Computer Science and Information Engineering, Chang Gung University } 2017/11/15 Midterm } 2017/11/22 Final Project Announcement 2 1. Introduction 2.

More information

Performance Metrics & Architectural Adaptivity. ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So

Performance Metrics & Architectural Adaptivity. ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So Performance Metrics & Architectural Adaptivity ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So What are the Options? Power Consumption Activity factor (amount of circuit switching) Load Capacitance (size

More information

Extending Parallel Scalability of LAMMPS and Multiscale Reactive Molecular Simulations

Extending Parallel Scalability of LAMMPS and Multiscale Reactive Molecular Simulations September 18, 2012 Extending Parallel Scalability of LAMMPS and Multiscale Reactive Molecular Simulations Yuxing Peng, Chris Knight, Philip Blood, Lonnie Crosby, and Gregory A. Voth Outline Proton Solvation

More information

Scalable Tools for Debugging Non-Deterministic MPI Applications

Scalable Tools for Debugging Non-Deterministic MPI Applications Scalable Tools for Debugging Non-Deterministic MPI Applications ReMPI: MPI Record-and-Replay tool Scalable Tools Workshop August 2nd, 2016 Kento Sato, Dong H. Ahn, Ignacio Laguna, Gregory L. Lee, Mar>n

More information

A Physical-Aware Task Migration Algorithm for Dynamic Thermal Management of SMT Multi-core Processors

A Physical-Aware Task Migration Algorithm for Dynamic Thermal Management of SMT Multi-core Processors A Physical-Aware Task Migration Algorithm for Dynamic Thermal Management of SMT Multi-core Processors Abstract - This paper presents a task migration algorithm for dynamic thermal management of SMT multi-core

More information

Dense Arithmetic over Finite Fields with CUMODP

Dense Arithmetic over Finite Fields with CUMODP Dense Arithmetic over Finite Fields with CUMODP Sardar Anisul Haque 1 Xin Li 2 Farnam Mansouri 1 Marc Moreno Maza 1 Wei Pan 3 Ning Xie 1 1 University of Western Ontario, Canada 2 Universidad Carlos III,

More information

TDDB68 Concurrent programming and operating systems. Lecture: CPU Scheduling II

TDDB68 Concurrent programming and operating systems. Lecture: CPU Scheduling II TDDB68 Concurrent programming and operating systems Lecture: CPU Scheduling II Mikael Asplund, Senior Lecturer Real-time Systems Laboratory Department of Computer and Information Science Copyright Notice:

More information

BeiHang Short Course, Part 7: HW Acceleration: It s about Performance, Energy and Power

BeiHang Short Course, Part 7: HW Acceleration: It s about Performance, Energy and Power BeiHang Short Course, Part 7: HW Acceleration: It s about Performance, Energy and Power James C. Hoe Department of ECE Carnegie Mellon niversity Eric S. Chung, et al., Single chip Heterogeneous Computing:

More information

3D Cartesian Transport Sweep for Massively Parallel Architectures on top of PaRSEC

3D Cartesian Transport Sweep for Massively Parallel Architectures on top of PaRSEC 3D Cartesian Transport Sweep for Massively Parallel Architectures on top of PaRSEC 9th Scheduling for Large Scale Systems Workshop, Lyon S. Moustafa, M. Faverge, L. Plagne, and P. Ramet S. Moustafa, M.

More information

CPU Scheduling Exercises

CPU Scheduling Exercises CPU Scheduling Exercises NOTE: All time in these exercises are in msec. Processes P 1, P 2, P 3 arrive at the same time, but enter the job queue in the order presented in the table. Time quantum = 3 msec

More information

Logic BIST. Sungho Kang Yonsei University

Logic BIST. Sungho Kang Yonsei University Logic BIST Sungho Kang Yonsei University Outline Introduction Basics Issues Weighted Random Pattern Generation BIST Architectures Deterministic BIST Conclusion 2 Built In Self Test Test/ Normal Input Pattern

More information

CHAPTER 5 - PROCESS SCHEDULING

CHAPTER 5 - PROCESS SCHEDULING CHAPTER 5 - PROCESS SCHEDULING OBJECTIVES To introduce CPU scheduling, which is the basis for multiprogrammed operating systems To describe various CPU-scheduling algorithms To discuss evaluation criteria

More information

Performance Metrics for Computer Systems. CASS 2018 Lavanya Ramapantulu

Performance Metrics for Computer Systems. CASS 2018 Lavanya Ramapantulu Performance Metrics for Computer Systems CASS 2018 Lavanya Ramapantulu Eight Great Ideas in Computer Architecture Design for Moore s Law Use abstraction to simplify design Make the common case fast Performance

More information

VLSI Design Verification and Test Simulation CMPE 646. Specification. Design(netlist) True-value Simulator

VLSI Design Verification and Test Simulation CMPE 646. Specification. Design(netlist) True-value Simulator Design Verification Simulation used for ) design verification: verify the correctness of the design and 2) test verification. Design verification: Response analysis Specification Design(netlist) Critical

More information

CSE 380 Computer Operating Systems

CSE 380 Computer Operating Systems CSE 380 Computer Operating Systems Instructor: Insup Lee & Dianna Xu University of Pennsylvania, Fall 2003 Lecture Note 3: CPU Scheduling 1 CPU SCHEDULING q How can OS schedule the allocation of CPU cycles

More information

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. 1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change

More information

The Quasi-Synchronous Approach to Distributed Control Systems

The Quasi-Synchronous Approach to Distributed Control Systems The Quasi-Synchronous Approach to Distributed Control Systems Paul Caspi caspi@imag.fr Verimag Laboratory http://www-verimag.imag.fr Crisys Esprit Project http://borneo.gmd.de/ ap/crisys/ The Quasi-Synchronous

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

Scheduling. Uwe R. Zimmer & Alistair Rendell The Australian National University

Scheduling. Uwe R. Zimmer & Alistair Rendell The Australian National University 6 Scheduling Uwe R. Zimmer & Alistair Rendell The Australian National University References for this chapter [Bacon98] J. Bacon Concurrent Systems 1998 (2nd Edition) Addison Wesley Longman Ltd, ISBN 0-201-17767-6

More information

Highly-scalable branch and bound for maximum monomial agreement

Highly-scalable branch and bound for maximum monomial agreement Highly-scalable branch and bound for maximum monomial agreement Jonathan Eckstein (Rutgers) William Hart Cynthia A. Phillips Sandia National Laboratories Sandia National Laboratories is a multi-program

More information

Testability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors.

Testability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors. Testability Lecture 6: Logic Simulation Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted from the presentation prepared by book authors Slide 1 of 27 Outline What

More information

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

More information

Technical Report GIT-CERCS. Thermal Field Management for Many-core Processors

Technical Report GIT-CERCS. Thermal Field Management for Many-core Processors Technical Report GIT-CERCS Thermal Field Management for Many-core Processors Minki Cho, Nikhil Sathe, Sudhakar Yalamanchili and Saibal Mukhopadhyay School of Electrical and Computer Engineering Georgia

More information

Scheduling for Reduced CPU Energy

Scheduling for Reduced CPU Energy Scheduling for Reduced CPU Energy M. Weiser, B. Welch, A. Demers and S. Shenker Appears in "Proceedings of the First Symposium on Operating Systems Design and Implementation," Usenix Association, November

More information

NCU EE -- DSP VLSI Design. Tsung-Han Tsai 1

NCU EE -- DSP VLSI Design. Tsung-Han Tsai 1 NCU EE -- DSP VLSI Design. Tsung-Han Tsai 1 Multi-processor vs. Multi-computer architecture µp vs. DSP RISC vs. DSP RISC Reduced-instruction-set Register-to-register operation Higher throughput by using

More information

Cost-Effective Partitioning for Detection of Atomicity Violations: An Empirical Study

Cost-Effective Partitioning for Detection of Atomicity Violations: An Empirical Study Cost-Effective Partitioning for etection of Atomicity Violations: An Empirical Study Shangru Wu, Chunbai Yang, Changjiang Jia, and W.K. Chan Abstract ynamic concurrency bug detectors predict and then examine

More information

Shedding the Shackles of Time-Division Multiplexing

Shedding the Shackles of Time-Division Multiplexing Shedding the Shackles of Time-Division Multiplexing Farouk Hebbache with Florian Brandner, 2 Mathieu Jan, Laurent Pautet 2 CEA List, LS 2 LTCI, Télécom ParisTech, Université Paris-Saclay Multi-core Architectures

More information

Simulation of the IEEE 1588 Precision Time Protocol in OMNeT++

Simulation of the IEEE 1588 Precision Time Protocol in OMNeT++ Simulation of the IEEE 1588 Precision Time Protocol in OMNeT++ Wolfgang Wallner wolfgang-wallner@gmx.at September 15, 2016 Presentation Outline Introduction Motivation Problem statement Presentation Outline

More information

Performance Evaluation of MPI on Weather and Hydrological Models

Performance Evaluation of MPI on Weather and Hydrological Models NCAR/RAL Performance Evaluation of MPI on Weather and Hydrological Models Alessandro Fanfarillo elfanfa@ucar.edu August 8th 2018 Cheyenne - NCAR Supercomputer Cheyenne is a 5.34-petaflops, high-performance

More information

Estimation of Instantaneous Frequency Fluctuation in a Fast DVFS Environment Using an Empirical BTI Stress-Relaxation Model

Estimation of Instantaneous Frequency Fluctuation in a Fast DVFS Environment Using an Empirical BTI Stress-Relaxation Model Estimation of Instantaneous Fluctuation in a Fast DVFS Environment Using an Empirical BTI Stress-Relaxation Model Chen Zhou, Xiaofei Wang, Weichao Xu, *Yuhao Zhu, *Vijay Janapa Reddi, and Chris H. Kim

More information

RAID+: Deterministic and Balanced Data Distribution for Large Disk Enclosures

RAID+: Deterministic and Balanced Data Distribution for Large Disk Enclosures RAID+: Deterministic and Balanced Data Distribution for Large Disk Enclosures Guangyan Zhang, Zican Huang, Xiaosong Ma SonglinYang, Zhufan Wang, Weimin Zheng Tsinghua University Qatar Computing Research

More information

ECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview

ECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview 407 Computer Aided Design for Electronic Systems Simulation Instructor: Maria K. Michael Overview What is simulation? Design verification Modeling Levels Modeling circuits for simulation True-value simulation

More information

CPU Scheduling. Heechul Yun

CPU Scheduling. Heechul Yun CPU Scheduling Heechul Yun 1 Recap Four deadlock conditions: Mutual exclusion No preemption Hold and wait Circular wait Detection Avoidance Banker s algorithm 2 Recap: Banker s Algorithm 1. Initialize

More information

Review for the Midterm Exam

Review for the Midterm Exam Review for the Midterm Exam 1 Three Questions of the Computational Science Prelim scaled speedup network topologies work stealing 2 The in-class Spring 2012 Midterm Exam pleasingly parallel computations

More information

Qualitative vs Quantitative metrics

Qualitative vs Quantitative metrics Qualitative vs Quantitative metrics Quantitative: hard numbers, measurable Time, Energy, Space Signal-to-Noise, Frames-per-second, Memory Usage Money (?) Qualitative: feelings, opinions Complexity: Simple,

More information

UMBC. At the system level, DFT includes boundary scan and analog test bus. The DFT techniques discussed focus on improving testability of SAFs.

UMBC. At the system level, DFT includes boundary scan and analog test bus. The DFT techniques discussed focus on improving testability of SAFs. Overview Design for testability(dft) makes it possible to: Assure the detection of all faults in a circuit. Reduce the cost and time associated with test development. Reduce the execution time of performing

More information

Process Scheduling. Process Scheduling. CPU and I/O Bursts. CPU - I/O Burst Cycle. Variations in Bursts. Histogram of CPU Burst Times

Process Scheduling. Process Scheduling. CPU and I/O Bursts. CPU - I/O Burst Cycle. Variations in Bursts. Histogram of CPU Burst Times Scheduling The objective of multiprogramming is to have some process running all the time The objective of timesharing is to have the switch between processes so frequently that users can interact with

More information

Blind Identification of Power Sources in Processors

Blind Identification of Power Sources in Processors Blind Identification of Power Sources in Processors Sherief Reda School of Engineering Brown University, Providence, RI 2912 Email: sherief reda@brown.edu Abstract The ability to measure power consumption

More information

Neural Network-Based Accelerators for Transcendental Function Approximation

Neural Network-Based Accelerators for Transcendental Function Approximation Neural Network-Based Accelerators for Transcendental Function Approximation Schuyler Eldridge Florian Raudies David Zou Ajay Joshi Department of Electrical and Computer Engineering, Boston University Center

More information

Dynamic Voltage and Frequency Scaling Under a Precise Energy Model Considering Variable and Fixed Components of the System Power Dissipation

Dynamic Voltage and Frequency Scaling Under a Precise Energy Model Considering Variable and Fixed Components of the System Power Dissipation Dynamic Voltage and Frequency Scaling Under a Precise Energy Model Csidering Variable and Fixed Compents of the System Power Dissipati Kihwan Choi W-bok Lee Ramakrishna Soma Massoud Pedram University of

More information

Simulation of Process Scheduling Algorithms

Simulation of Process Scheduling Algorithms Simulation of Process Scheduling Algorithms Project Report Instructor: Dr. Raimund Ege Submitted by: Sonal Sood Pramod Barthwal Index 1. Introduction 2. Proposal 3. Background 3.1 What is a Process 4.

More information

Relyzer: Application Resiliency Analyzer for Transient Faults

Relyzer: Application Resiliency Analyzer for Transient Faults 1 Relyzer: Application Resiliency Analyzer for Transient Faults Siva Kumar Sastry Hari 1,2, Helia Naeimi 2, Pradeep Ramachandran 1, and Sarita V. Adve 1 1 Department of Computer Science, University of

More information

MICROPROCESSOR REPORT. THE INSIDER S GUIDE TO MICROPROCESSOR HARDWARE

MICROPROCESSOR REPORT.   THE INSIDER S GUIDE TO MICROPROCESSOR HARDWARE MICROPROCESSOR www.mpronline.com REPORT THE INSIDER S GUIDE TO MICROPROCESSOR HARDWARE ENERGY COROLLARIES TO AMDAHL S LAW Analyzing the Interactions Between Parallel Execution and Energy Consumption By

More information

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks ABSTRACT Weicheng Liu, Emre Salman Department of Electrical and Computer Engineering Stony Brook University Stony Brook, NY 11794 [weicheng.liu,

More information

EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis

EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top

More information

Lecture 8: Sequential Multipliers

Lecture 8: Sequential Multipliers Lecture 8: Sequential Multipliers ECE 645 Computer Arithmetic 3/25/08 ECE 645 Computer Arithmetic Lecture Roadmap Sequential Multipliers Unsigned Signed Radix-2 Booth Recoding High-Radix Multiplication

More information

Immediate Detection of Predicates in Pervasive Environments

Immediate Detection of Predicates in Pervasive Environments Immediate Detection of redicates in ervasive Environments Ajay Kshemkalyani University of Illinois at Chicago November 30, 2010 A. Kshemkalyani (U Illinois at Chicago) Immediate Detection of redicates......

More information

ECE 448 Lecture 6. Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code. George Mason University

ECE 448 Lecture 6. Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code. George Mason University ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code George Mason University Required reading P. Chu, FPGA Prototyping by VHDL Examples

More information

CPU SCHEDULING RONG ZHENG

CPU SCHEDULING RONG ZHENG CPU SCHEDULING RONG ZHENG OVERVIEW Why scheduling? Non-preemptive vs Preemptive policies FCFS, SJF, Round robin, multilevel queues with feedback, guaranteed scheduling 2 SHORT-TERM, MID-TERM, LONG- TERM

More information

Amdahl's Law. Execution time new = ((1 f) + f/s) Execution time. S. Then:

Amdahl's Law. Execution time new = ((1 f) + f/s) Execution time. S. Then: Amdahl's Law Useful for evaluating the impact of a change. (A general observation.) Insight: Improving a feature cannot improve performance beyond the use of the feature Suppose we introduce a particular

More information

Improved Deadline Monotonic Scheduling With Dynamic and Intelligent Time Slice for Real-time Systems

Improved Deadline Monotonic Scheduling With Dynamic and Intelligent Time Slice for Real-time Systems Improved Deadline Monotonic Scheduling With Dynamic and Intelligent Time Slice for Real-time Systems H. S. Behera, Sushree Sangita Panda and Jana Chakraborty Department of Computer Science and Engineering,

More information

Lecture 7: Logic design. Combinational logic circuits

Lecture 7: Logic design. Combinational logic circuits /24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic

More information

CS505: Distributed Systems

CS505: Distributed Systems Cristina Nita-Rotaru CS505: Distributed Systems Ordering events. Lamport and vector clocks. Global states. Detecting failures. Required reading for this topic } Leslie Lamport,"Time, Clocks, and the Ordering

More information

TDDI04, K. Arvidsson, IDA, Linköpings universitet CPU Scheduling. Overview: CPU Scheduling. [SGG7] Chapter 5. Basic Concepts.

TDDI04, K. Arvidsson, IDA, Linköpings universitet CPU Scheduling. Overview: CPU Scheduling. [SGG7] Chapter 5. Basic Concepts. TDDI4 Concurrent Programming, Operating Systems, and Real-time Operating Systems CPU Scheduling Overview: CPU Scheduling CPU bursts and I/O bursts Scheduling Criteria Scheduling Algorithms Multiprocessor

More information

Lecture 16 More Profiling: gperftools, systemwide tools: oprofile, perf, DTrace, etc.

Lecture 16 More Profiling: gperftools, systemwide tools: oprofile, perf, DTrace, etc. Lecture 16 More Profiling: gperftools, systemwide tools: oprofile, perf, DTrace, etc. ECE 459: Programming for Performance March 6, 2014 Part I gperftools 2 / 49 Introduction to gperftools Google Performance

More information

EET 310 Flip-Flops 11/17/2011 1

EET 310 Flip-Flops 11/17/2011 1 EET 310 Flip-Flops 11/17/2011 1 FF s and some Definitions Clock Input: FF s are controlled by a trigger or Clock signal. All FF s have a clock input. If a device which attempts to do a FF s task does not

More information

TSCCLOCK: A LOW COST, ROBUST, ACCURATE SOFTWARE CLOCK FOR NETWORKED COMPUTERS

TSCCLOCK: A LOW COST, ROBUST, ACCURATE SOFTWARE CLOCK FOR NETWORKED COMPUTERS TSCCLOCK: A LOW COST, ROBUST, ACCURATE SOFTWARE CLOCK FOR NETWORKED COMPUTERS Darryl Veitch d.veitch@ee.unimelb.edu.au http://www.cubinlab.ee.unimelb.edu.au/ darryl Collaboration with Julien Ridoux CUBIN,

More information

Juggle: Proactive Load Balancing on Multicore Computers

Juggle: Proactive Load Balancing on Multicore Computers Juggle: Proactive Load Balancing on Multicore Computers ABSTRACT Steven Hofmeyr LBNL shofmeyr@lbl.gov Costin Iancu LBNL ciancu@lbl.gov We investigate proactive dynamic load balancing on multicore systems,

More information

Online Scheduling Switch for Maintaining Data Freshness in Flexible Real-Time Systems

Online Scheduling Switch for Maintaining Data Freshness in Flexible Real-Time Systems Online Scheduling Switch for Maintaining Data Freshness in Flexible Real-Time Systems Song Han 1 Deji Chen 2 Ming Xiong 3 Aloysius K. Mok 1 1 The University of Texas at Austin 2 Emerson Process Management

More information

Energy-efficient Mapping of Big Data Workflows under Deadline Constraints

Energy-efficient Mapping of Big Data Workflows under Deadline Constraints Energy-efficient Mapping of Big Data Workflows under Deadline Constraints Presenter: Tong Shu Authors: Tong Shu and Prof. Chase Q. Wu Big Data Center Department of Computer Science New Jersey Institute

More information

Clocked Synchronous State-machine Analysis

Clocked Synchronous State-machine Analysis Clocked Synchronous State-machine Analysis Given the circuit diagram of a state machine: Analyze the combinational logic to determine flip-flop input (excitation) equations: D i = F i (Q, inputs) The input

More information

Analysis of PFLOTRAN on Jaguar

Analysis of PFLOTRAN on Jaguar Analysis of PFLOTRAN on Jaguar Kevin Huck, Jesus Labarta, Judit Gimenez, Harald Servat, Juan Gonzalez, and German Llort CScADS Workshop on Performance Tools for Petascale Computing Snowbird, UT How this

More information

Time. To do. q Physical clocks q Logical clocks

Time. To do. q Physical clocks q Logical clocks Time To do q Physical clocks q Logical clocks Events, process states and clocks A distributed system A collection P of N single-threaded processes (p i, i = 1,, N) without shared memory The processes in

More information

CPU scheduling. CPU Scheduling

CPU scheduling. CPU Scheduling EECS 3221 Operating System Fundamentals No.4 CPU scheduling Prof. Hui Jiang Dept of Electrical Engineering and Computer Science, York University CPU Scheduling CPU scheduling is the basis of multiprogramming

More information

ENERGY EFFICIENT TASK SCHEDULING OF SEND- RECEIVE TASK GRAPHS ON DISTRIBUTED MULTI- CORE PROCESSORS WITH SOFTWARE CONTROLLED DYNAMIC VOLTAGE SCALING

ENERGY EFFICIENT TASK SCHEDULING OF SEND- RECEIVE TASK GRAPHS ON DISTRIBUTED MULTI- CORE PROCESSORS WITH SOFTWARE CONTROLLED DYNAMIC VOLTAGE SCALING ENERGY EFFICIENT TASK SCHEDULING OF SEND- RECEIVE TASK GRAPHS ON DISTRIBUTED MULTI- CORE PROCESSORS WITH SOFTWARE CONTROLLED DYNAMIC VOLTAGE SCALING Abhishek Mishra and Anil Kumar Tripathi Department of

More information

Mark Redekopp, All rights reserved. Lecture 1 Slides. Intro Number Systems Logic Functions

Mark Redekopp, All rights reserved. Lecture 1 Slides. Intro Number Systems Logic Functions Lecture Slides Intro Number Systems Logic Functions EE 0 in Context EE 0 EE 20L Logic Design Fundamentals Logic Design, CAD Tools, Lab tools, Project EE 357 EE 457 Computer Architecture Using the logic

More information

Lecture 2: CMOS technology. Energy-aware computing

Lecture 2: CMOS technology. Energy-aware computing Energy-Aware Computing Lecture 2: CMOS technology Basic components Transistors Two types: NMOS, PMOS Wires (interconnect) Transistors as switches Gate Drain Source NMOS: When G is @ logic 1 (actually over

More information

Energy-aware scheduling for GreenIT in large-scale distributed systems

Energy-aware scheduling for GreenIT in large-scale distributed systems Energy-aware scheduling for GreenIT in large-scale distributed systems 1 PASCAL BOUVRY UNIVERSITY OF LUXEMBOURG GreenIT CORE/FNR project Context and Motivation Outline 2 Problem Description Proposed Solution

More information

Cycle Error Correction in Asynchronous Clock Modeling for Cycle-Based Simulation

Cycle Error Correction in Asynchronous Clock Modeling for Cycle-Based Simulation 1 Cycle Error Correction in Asynchronous Clock Modeling for Cycle-Based Simulation Junghee Lee and Joonhwan Yi Telecommunication R&D Center Samsung Electronics {junghee77.lee, joonhwan.yi} @ samsung.com

More information

Parallel PIPS-SBB Multi-level parallelism for 2-stage SMIPS. Lluís-Miquel Munguia, Geoffrey M. Oxberry, Deepak Rajan, Yuji Shinano

Parallel PIPS-SBB Multi-level parallelism for 2-stage SMIPS. Lluís-Miquel Munguia, Geoffrey M. Oxberry, Deepak Rajan, Yuji Shinano Parallel PIPS-SBB Multi-level parallelism for 2-stage SMIPS Lluís-Miquel Munguia, Geoffrey M. Oxberry, Deepak Rajan, Yuji Shinano ... Our contribution PIPS-PSBB*: Multi-level parallelism for Stochastic

More information

Lecture 4: Process Management

Lecture 4: Process Management Lecture 4: Process Management Process Revisited 1. What do we know so far about Linux on X-86? X-86 architecture supports both segmentation and paging. 48-bit logical address goes through the segmentation

More information

CS 550 Operating Systems Spring CPU scheduling I

CS 550 Operating Systems Spring CPU scheduling I 1 CS 550 Operating Systems Spring 2018 CPU scheduling I Process Lifecycle Ready Process is ready to execute, but not yet executing Its waiting in the scheduling queue for the CPU scheduler to pick it up.

More information

CPU Scheduling. CPU Scheduler

CPU Scheduling. CPU Scheduler CPU Scheduling These slides are created by Dr. Huang of George Mason University. Students registered in Dr. Huang s courses at GMU can make a single machine readable copy and print a single copy of each

More information

Embedded Systems Design: Optimization Challenges. Paul Pop Embedded Systems Lab (ESLAB) Linköping University, Sweden

Embedded Systems Design: Optimization Challenges. Paul Pop Embedded Systems Lab (ESLAB) Linköping University, Sweden of /4 4 Embedded Systems Design: Optimization Challenges Paul Pop Embedded Systems Lab (ESLAB) Linköping University, Sweden Outline! Embedded systems " Example area: automotive electronics " Embedded systems

More information

Counters. We ll look at different kinds of counters and discuss how to build them

Counters. We ll look at different kinds of counters and discuss how to build them Counters We ll look at different kinds of counters and discuss how to build them These are not only examples of sequential analysis and design, but also real devices used in larger circuits 1 Introducing

More information

Saving Energy in Sparse and Dense Linear Algebra Computations

Saving Energy in Sparse and Dense Linear Algebra Computations Saving Energy in Sparse and Dense Linear Algebra Computations P. Alonso, M. F. Dolz, F. Igual, R. Mayo, E. S. Quintana-Ortí, V. Roca Univ. Politécnica Univ. Jaume I The Univ. of Texas de Valencia, Spain

More information

VLSI Physical Design Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

VLSI Physical Design Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur VLSI Physical Design Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture - 54 Design for Testability So, in the last lecture we talked

More information

HYCOM and Navy ESPC Future High Performance Computing Needs. Alan J. Wallcraft. COAPS Short Seminar November 6, 2017

HYCOM and Navy ESPC Future High Performance Computing Needs. Alan J. Wallcraft. COAPS Short Seminar November 6, 2017 HYCOM and Navy ESPC Future High Performance Computing Needs Alan J. Wallcraft COAPS Short Seminar November 6, 2017 Forecasting Architectural Trends 3 NAVY OPERATIONAL GLOBAL OCEAN PREDICTION Trend is higher

More information

Real-Time Systems. Event-Driven Scheduling

Real-Time Systems. Event-Driven Scheduling Real-Time Systems Event-Driven Scheduling Marcus Völp, Hermann Härtig WS 2013/14 Outline mostly following Jane Liu, Real-Time Systems Principles Scheduling EDF and LST as dynamic scheduling methods Fixed

More information

Distributed Computing. Synchronization. Dr. Yingwu Zhu

Distributed Computing. Synchronization. Dr. Yingwu Zhu Distributed Computing Synchronization Dr. Yingwu Zhu Topics to Discuss Physical Clocks Logical Clocks: Lamport Clocks Classic paper: Time, Clocks, and the Ordering of Events in a Distributed System Lamport

More information

Evaluation of Energy-Optimizing Scheduling Algorithms for Streaming Computation on Massively Parallel Architectures

Evaluation of Energy-Optimizing Scheduling Algorithms for Streaming Computation on Massively Parallel Architectures masterthesis 2014/8/6 13:48 page #1 Final thesis Evaluation of Energy-Optimizing Scheduling Algorithms for Streaming Computation on Massively Parallel Architectures by Johan Janzén LITH-IDA-EX-2014/043

More information

Integration and Higher Level Testing

Integration and Higher Level Testing Integration and Higher Level Testing Software Testing and Verification Lecture 11 Prepared by Stephen M. Thebaut, Ph.D. University of Florida Context Higher-level testing begins with the integration of

More information

CpE358/CS381. Switching Theory and Logical Design. Class 16

CpE358/CS381. Switching Theory and Logical Design. Class 16 CpE358/CS38 Switching Theory and Logical Design Class 6 CpE358/CS38 Summer- 24 Copyright 24-585 Today Fundamental concepts of digital systems (Mano Chapter ) inary codes, number systems, and arithmetic

More information

Binding Performance and Power of Dense Linear Algebra Operations

Binding Performance and Power of Dense Linear Algebra Operations 10th IEEE International Symposium on Parallel and Distributed Processing with Applications Binding Performance and Power of Dense Linear Algebra Operations Maria Barreda, Manuel F. Dolz, Rafael Mayo, Enrique

More information

Timing Driven Power Gating in High-Level Synthesis

Timing Driven Power Gating in High-Level Synthesis Timing Driven Power Gating in High-Level Synthesis Shih-Hsu Huang and Chun-Hua Cheng Department of Electronic Engineering Chung Yuan Christian University, Taiwan Outline Introduction Motivation Our Approach

More information

Module 5: CPU Scheduling

Module 5: CPU Scheduling Module 5: CPU Scheduling Basic Concepts Scheduling Criteria Scheduling Algorithms Multiple-Processor Scheduling Real-Time Scheduling Algorithm Evaluation 5.1 Basic Concepts Maximum CPU utilization obtained

More information

An Energy-efficient Task Scheduler for Multi-core Platforms with per-core DVFS Based on Task Characteristics

An Energy-efficient Task Scheduler for Multi-core Platforms with per-core DVFS Based on Task Characteristics 1 An -efficient Task Scheduler for Multi-core Platforms with per-core DVFS Based on Task Characteristics Ching-Chi Lin, You-Cheng Syu, Chao-Jui Chang, Jan-Jan Wu, Pangfeng Liu, Po-Wen Cheng and Wei-Te

More information

How to deal with uncertainties and dynamicity?

How to deal with uncertainties and dynamicity? How to deal with uncertainties and dynamicity? http://graal.ens-lyon.fr/ lmarchal/scheduling/ 19 novembre 2012 1/ 37 Outline 1 Sensitivity and Robustness 2 Analyzing the sensitivity : the case of Backfilling

More information

Chapter 6: CPU Scheduling

Chapter 6: CPU Scheduling Chapter 6: CPU Scheduling Basic Concepts Scheduling Criteria Scheduling Algorithms Multiple-Processor Scheduling Real-Time Scheduling Algorithm Evaluation 6.1 Basic Concepts Maximum CPU utilization obtained

More information