The Quasi-Synchronous Approach to Distributed Control Systems

Size: px
Start display at page:

Download "The Quasi-Synchronous Approach to Distributed Control Systems"

Transcription

1 The Quasi-Synchronous Approach to Distributed Control Systems Paul Caspi Verimag Laboratory Crisys Esprit Project ap/crisys/

2 The Quasi-Synchronous Approach to Distributed Control Systems Paul Caspi Verimag Laboratory Crisys Esprit Project ap/crisys/ Where does it come from? How to simulate it? How to understand it? Fault-tolerance

3 Where does it come from? From analog boards to computers Analog Board Clock periodic clocks A/D Computer D/A synchronous programs

4 Synchronous Programming General initialize state; loop each input event read other inputs; compute outputs and state; emit outputs end loop Several styles (imperative, data-flow,...) Allow multiple simultaneous event : no performance problems

5 Synchronous Programming Periodic initialize state; loop each clock read other inputs; compute outputs and state; emit outputs end loop

6 Synchronous Programming Periodic initialize state; loop each clock read other inputs; compute outputs and state; emit outputs end loop most applications of synchronous programming are actually periodic ones. hybridity: sampling differential equations require periodicity!

7 Where does it come from? From networks of analog boards to local area networks Analog Board Analog Board Clock Clock A/D Computer Serial Serial Computer D/A Clock Clock independent periodic clocks A/D Computer Computer D/A synchronous programs Bus

8 Interest Autonomy, robustness Each computer is a complete one, including its own clock and even possibly its own power supply. Communication between computers is non-blocking, based on periodic reads and writes, akin to periodic sampling.

9 How to formalize it Net View on chain - eq_chain same_period(c1, c2) and same_period(c2, c3) and same_period(c3, c1) c3 c2 c1 FBY FBY x FBY f1 FBY f2 f3 z Synchronous simulation, test and verification tools apply Efficiency issues?

10 How to understand it? Communication Abstraction Continuous Systems Non Continuous Systems Mixed Systems

11 Communication Abstration Worst situation: reads occur just before writes x(t-2t) write clock x (t) read clock Bounded communication delays T

12 Uniformly Continuous Signals x x ε η(ε) ε 0 η 0 t t t t η x x t x t ε Bounded delays yield bounded errors

13 Uniformly Continuous Systems ε η(ε) System ε 0 η 0 x x x x η f x f x ε Bounded errors yield bounded errors

14 But... Even very simple controllers are not uniformly continuous. PID for instance η Controller Bounded errors do not yield bounded errors

15 Stabilized Systems The closed-loop system computes uniformly continuous signals ε η(ε) U Controller X Z Plant Y Bounded delays yield bounded errors

16 Doubts... This casts a doubt on two wishful thoughts: composability system properties are the mere addition of sub-system ones separation of concerns: automatic control people specify computer science people implement Critical control systems require a tight cooperation between both people

17 Non Continuous Systems Combinational Systems Robust Sequential Systems Sequential Systems

18 Uniform Bounded-Variability There exists a minimum stable time T x associated with a signal x. x T x T x The analog of uniform continuity?

19 Sampling Tuples A possible sampling a b X X

20 Sampling Tuples Another possible sampling a X X! X!! b Non deterministic bounded delays

21 But... Delays on tuples do not yield delayed tuples x δ x y y Solution : Confirmation functions

22 Confirmation Functions When a component of a tuple changes, wait for some max " min time before taking it into account. If x#, y# are $ min% max& bounded images of x and y, then con f irm$ x# % y# & is a delayed image of $ x% y& allows to retrieve the continuous framework

23 Confirmation Functions Net View on confirm - eq_confirm difft4 watchdog U nmax Idt4 Ud nmax ' E( max ) min T min * + 1

24 Robust Sequential Systems idea : avoid critical races, between state variables : order insensitivity, between inputs : confluence Property checker

25 - Can robustness analysis be avoided? example : mutual exclusion Property : always not (y and z) a non robust solution : z y -

26 .. Can robustness analysis be avoided? example : mutual exclusion Property : always not (y and z) a robust solution : z y same answer as for error analysis in continuous systems

27 / / Robust solutions are distributable a robust solution : z y z waits for y to go down before going up and conversely. not y not z y 1 not y z 1 not z no critical race!

28 Non Robust Sequential Systems require either soft or hard synchronization. Time Triggered Architecture for instance.

29 A soft synchronization algorithm Non Robust Sequential Systems a b c requires a speed-up by 4 broadcast region execute region next broadcast

30 Implementation Net View on SYNCH - eq_synch FBY 1 SCHED u nu FBY 1 UN XN VARNODE1 Idt3 nx C3

31 Implementation State Machine View - SCHED write1 idle 1 : true 1 : nu and not NUP 2 : NUP write2 wait1 1 : true 1 : true wait2 1 : true 3 : (not nu) and not NUP 2 : NUP execute 1 : nu and not NUP

32 Mixed Systems Example : Threshold crossing ε S C t Relates errors and delays : τ4 τ 5 2ε C6 7 t8 5 This analysis too should not be skipped

33 Concurrency Actual Practices (Airbus) 6hz P1 P2 P3 3hz 2hz P2.1 P2.2 P3.1 P3.2 P3.3 P1 P2.1 P3.1 P1 P2.2 P3.2 P1 P2.1 P3.3

34 Concurrency A Crisys Proposal: earliest deadline preemptive scheduling P1 P2 P3 P1 P3* P1 P2 Schedulability condition ; WET i9 1: i 1 n T i

35 Concurrency A Crisys Proposal: earliest deadline preemptive scheduling P1 P2 P3 P1 P3* P1 P2 Schedulability condition > WET i< 1= i 1 n T i Generalizes the synchronous program execution condition WET > T

36 Concurrency Exact functional semantics is guaranteed as soon as Slow processes communicate with fast processes through a slow clock unit delay c t f t f t A A A B A D A A A x x 0 x 1 x 2 x 3 x 4 x? c x 0 x 2 x 4 f@ x? ca f@ x 0 f@ x 2 f@ x 4 f@ x? ca z z 0 z 0 f@ x 0 f@ x 2 z 0C za c z 0 z 0 f@ f@ f@ x 0 x 0 x 2

37 Fault Tolerance E Continuous Computations : Threshold Voting Units differ from more than the maximum normal error

38 Fault Tolerance F Continuous Computations : Threshold Voting Units differ from more than the maximum normal error F Combinational : Bounded-Delay Voting Units differ from more than the maximum normal delay

39 Fault Tolerance G Continuous Computations : Threshold Voting Units differ from more than the maximum normal error G Combinational : Bounded-Delay Voting Units differ from more than the maximum normal delay G Sequential Computations : 2/2 Bounded-Delay Voting

40 Bounded-Delay Voters Net View on vote2_2 - eq_vote2_2 X1 T3plus X2 T3plus Idt3 Xinit T3plus X watchdog n n H EI max J min T min K L 1

41 Sequential Computations Idea: vote on input and on state But Byzantine problems 2M 2 votes are not sensitive to Byzantine problems: N a bad unit is only compared with a single good one: it agrees: it looks good it disagrees: a fault is detected.

42 Sequential Computations: 2/2 Sequential Voters Net View on SeqVote - eq_seqvote U1 vote2_2t4 T4plus confirm VARNODE2 T3plus NX U2 nu nx Uinit X2 FBY 1 vote2_2t3 T3plus nnx XinitP Xinit nx O nmax up nmax x nnx O n Q nx

43

44 W R W W R R W R R R Proof Hints X S FT XU UV X 1 S FT XU U 1V X 1 S FT X 1 U U 1V τ u τ x X 1 S FT XU U 1V τ u τ x X 1 S FT X 1 U U 1V

45 Conclusion X Some insight on techniques used in practice. X maybe useful for designers and certification authorities ( Crisys Esprit Project) X An attempt to catch the attention of the Computer Science Community on these important problems.

46 Questions Y When are clock synchronization methods useful and more efficient than the ones presented here?

47 Questions Z When are clock synchronization methods useful and more efficient than the ones presented here? Z How to safely encompass some event-driven computations within the approach?

48 Questions [ When are clock synchronization methods useful and more efficient than the ones presented here? [ How to safely encompass some event-driven computations within the approach? [ Are there linguistic ways to robustness (synchronous-asynchronous languages)?

49 Questions \ When are clock synchronization methods useful and more efficient than the ones presented here? \ How to safely encompass some event-driven computations within the approach? \ Are there linguistic ways to robustness (synchronous-asynchronous languages)? \ Is there a common framework encompassing both theories? continuous uniformly continuous signals uniformly continuous functions unstable systems discrete uniform bounded variability robust systems sequential non robust systems

Synchronous Modelling of Complex Systems

Synchronous Modelling of Complex Systems Synchronous Modelling of Complex Systems Nicolas Halbwachs Verimag, Grenoble joint work with L. Mandel LRI E. Jahier, P. Raymond, X. Nicollin Verimag and D. Lesens Astrium Space Transportation () 1 / 45

More information

A Brief Introduction to Model Checking

A Brief Introduction to Model Checking A Brief Introduction to Model Checking Jan. 18, LIX Page 1 Model Checking A technique for verifying finite state concurrent systems; a benefit on this restriction: largely automatic; a problem to fight:

More information

Task Models and Scheduling

Task Models and Scheduling Task Models and Scheduling Jan Reineke Saarland University June 27 th, 2013 With thanks to Jian-Jia Chen at KIT! Jan Reineke Task Models and Scheduling June 27 th, 2013 1 / 36 Task Models and Scheduling

More information

The Weakest Failure Detector to Solve Mutual Exclusion

The Weakest Failure Detector to Solve Mutual Exclusion The Weakest Failure Detector to Solve Mutual Exclusion Vibhor Bhatt Nicholas Christman Prasad Jayanti Dartmouth College, Hanover, NH Dartmouth Computer Science Technical Report TR2008-618 April 17, 2008

More information

Design of Real-Time Software

Design of Real-Time Software Design of Real-Time Software Reference model Reinder J. Bril Technische Universiteit Eindhoven Department of Mathematics and Computer Science System Architecture and Networking Group P.O. Box 513, 5600

More information

Andrew Morton University of Waterloo Canada

Andrew Morton University of Waterloo Canada EDF Feasibility and Hardware Accelerators Andrew Morton University of Waterloo Canada Outline 1) Introduction and motivation 2) Review of EDF and feasibility analysis 3) Hardware accelerators and scheduling

More information

TESTING is one of the most important parts of the

TESTING is one of the most important parts of the IEEE TRANSACTIONS 1 Generating Complete Controllable Test Suites for Distributed Testing Robert M. Hierons, Senior Member, IEEE Abstract A test suite is m-complete for finite state machine (FSM) M if it

More information

Agreement Protocols. CS60002: Distributed Systems. Pallab Dasgupta Dept. of Computer Sc. & Engg., Indian Institute of Technology Kharagpur

Agreement Protocols. CS60002: Distributed Systems. Pallab Dasgupta Dept. of Computer Sc. & Engg., Indian Institute of Technology Kharagpur Agreement Protocols CS60002: Distributed Systems Pallab Dasgupta Dept. of Computer Sc. & Engg., Indian Institute of Technology Kharagpur Classification of Faults Based on components that failed Program

More information

Failure detectors Introduction CHAPTER

Failure detectors Introduction CHAPTER CHAPTER 15 Failure detectors 15.1 Introduction This chapter deals with the design of fault-tolerant distributed systems. It is widely known that the design and verification of fault-tolerent distributed

More information

N-Synchronous Kahn Networks A Relaxed Model of Synchrony for Real-Time Systems

N-Synchronous Kahn Networks A Relaxed Model of Synchrony for Real-Time Systems N-Synchronous Kahn Networks A Relaxed Model of Synchrony for Real-Time Systems Albert Cohen 1, Marc Duranton 2, Christine Eisenbeis 1, Claire Pagetti 1,4, Florence Plateau 3 and Marc Pouzet 3 POPL, Charleston

More information

A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware

A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware Julien Schmaltz Institute for Computing and Information Sciences Radboud University Nijmegen The Netherlands

More information

Quasi-synchrony. Timothy Bourke 1,2. 1. INRIA Paris. 2. École normale supérieure (DI)

Quasi-synchrony. Timothy Bourke 1,2. 1. INRIA Paris. 2. École normale supérieure (DI) Quasi-synchrony Timothy Bourke 1,2 1. INRIA Paris 2. École normale supérieure (DI) Timothy.Bourke@inria.fr These slides describe research together with Guillaume Baudart and Marc Pouzet 31 October 2017,

More information

Real Time Operating Systems

Real Time Operating Systems Real Time Operating ystems Luca Abeni luca.abeni@unitn.it Interacting Tasks Until now, only independent tasks... A job never blocks or suspends A task only blocks on job termination In real world, jobs

More information

Embedded Systems Development

Embedded Systems Development Embedded Systems Development Lecture 2 Finite Automata & SyncCharts Daniel Kästner AbsInt Angewandte Informatik GmbH kaestner@absint.com Some things I forgot to mention 2 Remember the HISPOS registration

More information

Embedded Systems 14. Overview of embedded systems design

Embedded Systems 14. Overview of embedded systems design Embedded Systems 14-1 - Overview of embedded systems design - 2-1 Point of departure: Scheduling general IT systems In general IT systems, not much is known about the computational processes a priori The

More information

Control Synthesis of Discrete Manufacturing Systems using Timed Finite Automata

Control Synthesis of Discrete Manufacturing Systems using Timed Finite Automata Control Synthesis of Discrete Manufacturing Systems using Timed Finite utomata JROSLV FOGEL Institute of Informatics Slovak cademy of Sciences ratislav Dúbravská 9, SLOVK REPULIC bstract: - n application

More information

From High-Level Component-Based Models to Distributed Implementations

From High-Level Component-Based Models to Distributed Implementations From High-Level Component-Based Models to Distributed Implementations Borzoo Bonakdarpour Marius Bozga Mohamad Jaber Jean Quilbeuf Joseph Sifakis VERIMAG, Centre Équation, 2 avenue de Vignate, 38610, Gières,

More information

Communicating and Mobile Systems

Communicating and Mobile Systems Communicating and Mobile Systems Overview:! Programming Model! Interactive Behavior! Labeled Transition System! Bisimulation! The π-calculus! Data Structures and λ-calculus encoding in the π-calculus References:!

More information

Embedded Systems Development

Embedded Systems Development Embedded Systems Development Lecture 3 Real-Time Scheduling Dr. Daniel Kästner AbsInt Angewandte Informatik GmbH kaestner@absint.com Model-based Software Development Generator Lustre programs Esterel programs

More information

Shared Memory vs Message Passing

Shared Memory vs Message Passing Shared Memory vs Message Passing Carole Delporte-Gallet Hugues Fauconnier Rachid Guerraoui Revised: 15 February 2004 Abstract This paper determines the computational strength of the shared memory abstraction

More information

Non-Work-Conserving Non-Preemptive Scheduling: Motivations, Challenges, and Potential Solutions

Non-Work-Conserving Non-Preemptive Scheduling: Motivations, Challenges, and Potential Solutions Non-Work-Conserving Non-Preemptive Scheduling: Motivations, Challenges, and Potential Solutions Mitra Nasri Chair of Real-time Systems, Technische Universität Kaiserslautern, Germany nasri@eit.uni-kl.de

More information

There are three priority driven approaches that we will look at

There are three priority driven approaches that we will look at Priority Driven Approaches There are three priority driven approaches that we will look at Earliest-Deadline-First (EDF) Least-Slack-Time-first (LST) Latest-Release-Time-first (LRT) 1 EDF Earliest deadline

More information

Semi-asynchronous. Fault Diagnosis of Discrete Event Systems ALEJANDRO WHITE DR. ALI KARIMODDINI OCTOBER

Semi-asynchronous. Fault Diagnosis of Discrete Event Systems ALEJANDRO WHITE DR. ALI KARIMODDINI OCTOBER Semi-asynchronous Fault Diagnosis of Discrete Event Systems ALEJANDRO WHITE DR. ALI KARIMODDINI OCTOBER 2017 NC A&T State University http://www.ncat.edu/ Alejandro White Semi-asynchronous http://techlav.ncat.edu/

More information

Modeling Synchronous Systems in BIP

Modeling Synchronous Systems in BIP Unité Mixte de Recherche 5104 CNRS - INPG - UJF Centre Equation 2, avenue de VIGNATE F-38610 GIERES tel : +33 456 52 03 40 fax : +33 456 52 03 50 http://www-verimag.imag.fr Modeling Synchronous Systems

More information

Logic Model Checking

Logic Model Checking Logic Model Checking Lecture Notes 10:18 Caltech 101b.2 January-March 2004 Course Text: The Spin Model Checker: Primer and Reference Manual Addison-Wesley 2003, ISBN 0-321-22862-6, 608 pgs. the assignment

More information

Assertions and Measurements for Mixed-Signal Simulation

Assertions and Measurements for Mixed-Signal Simulation Assertions and Measurements for Mixed-Signal Simulation PhD Thesis Thomas Ferrère VERIMAG, University of Grenoble (directeur: Oded Maler) Mentor Graphics Corporation (co-encadrant: Ernst Christen) October

More information

A framework for simulation and symbolic state space analysis of non-markovian models

A framework for simulation and symbolic state space analysis of non-markovian models A framework for simulation and symbolic state space analysis of non-markovian models Laura Carnevali, Lorenzo Ridi, Enrico Vicario SW Technologies Lab (STLab) - Dip. Sistemi e Informatica (DSI) - Univ.

More information

Verification of clock synchronization algorithm (Original Welch-Lynch algorithm and adaptation to TTA)

Verification of clock synchronization algorithm (Original Welch-Lynch algorithm and adaptation to TTA) Verification of clock synchronization algorithm (Original Welch-Lynch algorithm and adaptation to TTA) Christian Mueller November 25, 2005 1 Contents 1 Clock synchronization in general 3 1.1 Introduction............................

More information

Distributed Systems Principles and Paradigms. Chapter 06: Synchronization

Distributed Systems Principles and Paradigms. Chapter 06: Synchronization Distributed Systems Principles and Paradigms Maarten van Steen VU Amsterdam, Dept. Computer Science Room R4.20, steen@cs.vu.nl Chapter 06: Synchronization Version: November 16, 2009 2 / 39 Contents Chapter

More information

Distributed Systems Principles and Paradigms

Distributed Systems Principles and Paradigms Distributed Systems Principles and Paradigms Chapter 6 (version April 7, 28) Maarten van Steen Vrije Universiteit Amsterdam, Faculty of Science Dept. Mathematics and Computer Science Room R4.2. Tel: (2)

More information

Real Time Operating Systems

Real Time Operating Systems Real Time Operating ystems hared Resources Luca Abeni Credits: Luigi Palopoli, Giuseppe Lipari, and Marco Di Natale cuola uperiore ant Anna Pisa -Italy Real Time Operating ystems p. 1 Interacting Tasks

More information

Counters. We ll look at different kinds of counters and discuss how to build them

Counters. We ll look at different kinds of counters and discuss how to build them Counters We ll look at different kinds of counters and discuss how to build them These are not only examples of sequential analysis and design, but also real devices used in larger circuits 1 Introducing

More information

Stéphane Lafortune. August 2006

Stéphane Lafortune. August 2006 UNIVERSITY OF MICHIGAN DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE LECTURE NOTES FOR EECS 661 CHAPTER 1: INTRODUCTION TO DISCRETE EVENT SYSTEMS Stéphane Lafortune August 2006 References for

More information

Synchronous Sequential Circuit

Synchronous Sequential Circuit Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait

More information

TTA and PALS: Formally Verified Design Patterns for Distributed Cyber-Physical

TTA and PALS: Formally Verified Design Patterns for Distributed Cyber-Physical TTA and PALS: Formally Verified Design Patterns for Distributed Cyber-Physical DASC 2011, Oct/19 CoMMiCS Wilfried Steiner wilfried.steiner@tttech.com TTTech Computertechnik AG John Rushby rushby@csl.sri.com

More information

Simulation and Verification of Asynchronous Systems by means of a Synchronous Model

Simulation and Verification of Asynchronous Systems by means of a Synchronous Model c IEEE Computer Society ress, ACSD 06 Simulation and Verification of Asynchronous Systems by means of a Synchronous Model Nicolas Halbwachs and Louis Mandel Vérimag, Grenoble France Abstract Synchrony

More information

Lecture 13. Real-Time Scheduling. Daniel Kästner AbsInt GmbH 2013

Lecture 13. Real-Time Scheduling. Daniel Kästner AbsInt GmbH 2013 Lecture 3 Real-Time Scheduling Daniel Kästner AbsInt GmbH 203 Model-based Software Development 2 SCADE Suite Application Model in SCADE (data flow + SSM) System Model (tasks, interrupts, buses, ) SymTA/S

More information

Cryptographic Asynchronous Multi-Party Computation with Optimal Resilience

Cryptographic Asynchronous Multi-Party Computation with Optimal Resilience Cryptographic Asynchronous Multi-Party Computation with Optimal Resilience Martin Hirt 1, Jesper Buus Nielsen 2, and Bartosz Przydatek 1 1 Department of Computer Science, ETH Zurich 8092 Zurich, Switzerland

More information

Laxity Release Optimization for Simulink Models

Laxity Release Optimization for Simulink Models Preprints of the 19th World Congress The International Federation of Automatic Control Laxity Release Optimization for imulink Models Kaijie Qin, Guiming Luo, Xibin Zhao chool of oftware, Tsinghua University,

More information

Real-Time Systems. LS 12, TU Dortmund

Real-Time Systems. LS 12, TU Dortmund Real-Time Systems Prof. Dr. Jian-Jia Chen LS 12, TU Dortmund April 24, 2014 Prof. Dr. Jian-Jia Chen (LS 12, TU Dortmund) 1 / 57 Organization Instructor: Jian-Jia Chen, jian-jia.chen@cs.uni-dortmund.de

More information

Towards optimal synchronous counting

Towards optimal synchronous counting Towards optimal synchronous counting Christoph Lenzen Joel Rybicki Jukka Suomela MPI for Informatics MPI for Informatics Aalto University Aalto University PODC 5 July 3 Focus on fault-tolerance Fault-tolerant

More information

Embedded Systems 5. Synchronous Composition. Lee/Seshia Section 6.2

Embedded Systems 5. Synchronous Composition. Lee/Seshia Section 6.2 Embedded Systems 5-1 - Synchronous Composition Lee/Seshia Section 6.2 Important semantic model for concurrent composition Here: composition of actors Foundation of Statecharts, Simulink, synchronous programming

More information

Real-Time Reactive System - CCS with Time Delays

Real-Time Reactive System - CCS with Time Delays Real-Time Reactive System - CCS with Time Delays Wai Leung Sze (Stephen) Swansea University VINO 18th July 2011 Overview Introduction of real-time reactive system Describing the real-time reactive system

More information

Distributed Consensus

Distributed Consensus Distributed Consensus Reaching agreement is a fundamental problem in distributed computing. Some examples are Leader election / Mutual Exclusion Commit or Abort in distributed transactions Reaching agreement

More information

Do we have a quorum?

Do we have a quorum? Do we have a quorum? Quorum Systems Given a set U of servers, U = n: A quorum system is a set Q 2 U such that Q 1, Q 2 Q : Q 1 Q 2 Each Q in Q is a quorum How quorum systems work: A read/write shared register

More information

As Soon As Probable. O. Maler, J.-F. Kempf, M. Bozga. March 15, VERIMAG Grenoble, France

As Soon As Probable. O. Maler, J.-F. Kempf, M. Bozga. March 15, VERIMAG Grenoble, France As Soon As Probable O. Maler, J.-F. Kempf, M. Bozga VERIMAG Grenoble, France March 15, 2013 O. Maler, J.-F. Kempf, M. Bozga (VERIMAG Grenoble, France) As Soon As Probable March 15, 2013 1 / 42 Executive

More information

Component-Based Construction of Deadlock-Free Systems

Component-Based Construction of Deadlock-Free Systems Component-Based Construction of Deadlock-Free Systems Extended Abstract Gregor Gössler 1 and Joseph Sifakis 2 1 INRIA Rhône-Alpes, goessler@inrialpes.fr 2 VERIMAG, sifakis@imag.fr Abstract. We propose

More information

Real-Time Scheduling and Resource Management

Real-Time Scheduling and Resource Management ARTIST2 Summer School 2008 in Europe Autrans (near Grenoble), France September 8-12, 2008 Real-Time Scheduling and Resource Management Lecturer: Giorgio Buttazzo Full Professor Scuola Superiore Sant Anna

More information

Performance-based Dynamic Scheduling of Hybrid Real-time Applications on a Cluster of Heterogeneous Workstations 1

Performance-based Dynamic Scheduling of Hybrid Real-time Applications on a Cluster of Heterogeneous Workstations 1 Performance-based Dynamic Scheduling of Hybrid Real-time Applications on a Cluster of Heterogeneous Worstations 1 Ligang He, Stephen A. Jarvis, Daniel P. Spooner and Graham R. Nudd Department of Computer

More information

VLSI Design Verification and Test Simulation CMPE 646. Specification. Design(netlist) True-value Simulator

VLSI Design Verification and Test Simulation CMPE 646. Specification. Design(netlist) True-value Simulator Design Verification Simulation used for ) design verification: verify the correctness of the design and 2) test verification. Design verification: Response analysis Specification Design(netlist) Critical

More information

Probabilistic Deadline Miss Analysis of Real-Time Systems Using Regenerative Transient Analysis

Probabilistic Deadline Miss Analysis of Real-Time Systems Using Regenerative Transient Analysis Probabilistic Deadline Miss Analysis of Real-Time Systems Using Regenerative Transient Analysis L. Carnevali 1, A. Melani 2, L. Santinelli 3, G. Lipari 4 1 Department of Information Engineering, University

More information

Exam Spring Embedded Systems. Prof. L. Thiele

Exam Spring Embedded Systems. Prof. L. Thiele Exam Spring 20 Embedded Systems Prof. L. Thiele NOTE: The given solution is only a proposal. For correctness, completeness, or understandability no responsibility is taken. Sommer 20 Eingebettete Systeme

More information

Time and Schedulability Analysis of Stateflow Models

Time and Schedulability Analysis of Stateflow Models Time and Schedulability Analysis of Stateflow Models Marco Di Natale Scuola Superiore S. Anna Haibo Zeng Mc Gill University Outline Context: MBD of Embedded Systems Relationship with PBD An Introduction

More information

Time. Lakshmi Ganesh. (slides borrowed from Maya Haridasan, Michael George)

Time. Lakshmi Ganesh. (slides borrowed from Maya Haridasan, Michael George) Time Lakshmi Ganesh (slides borrowed from Maya Haridasan, Michael George) The Problem Given a collection of processes that can... only communicate with significant latency only measure time intervals approximately

More information

Aperiodic Task Scheduling

Aperiodic Task Scheduling Aperiodic Task Scheduling Jian-Jia Chen (slides are based on Peter Marwedel) TU Dortmund, Informatik 12 Germany Springer, 2010 2017 年 11 月 29 日 These slides use Microsoft clip arts. Microsoft copyright

More information

SFM-11:CONNECT Summer School, Bertinoro, June 2011

SFM-11:CONNECT Summer School, Bertinoro, June 2011 SFM-:CONNECT Summer School, Bertinoro, June 20 EU-FP7: CONNECT LSCITS/PSS VERIWARE Part 3 Markov decision processes Overview Lectures and 2: Introduction 2 Discrete-time Markov chains 3 Markov decision

More information

Refinement-Robust Fairness

Refinement-Robust Fairness Refinement-Robust Fairness Hagen Völzer Institut für Theoretische Informatik Universität zu Lübeck May 10, 2005 0 Overview 1. Problem 2. Formalization 3. Solution 4. Remarks 1 Problem weak fairness wrt

More information

A Multi-Periodic Synchronous Data-Flow Language

A Multi-Periodic Synchronous Data-Flow Language Julien Forget 1 Frédéric Boniol 1 David Lesens 2 Claire Pagetti 1 firstname.lastname@onera.fr 1 ONERA - Toulouse, FRANCE 2 EADS Astrium Space Transportation - Les Mureaux, FRANCE November 19, 2008 1 /

More information

Convergence of a distributed asynchronous learning vector quantization algorithm.

Convergence of a distributed asynchronous learning vector quantization algorithm. Convergence of a distributed asynchronous learning vector quantization algorithm. ENS ULM, NOVEMBER 2010 Benoît Patra (UPMC-Paris VI/Lokad) 1 / 59 Outline. 1 Introduction. 2 Vector quantization, convergence

More information

Autonomous Agent Behaviour Modelled in PRISM A Case Study

Autonomous Agent Behaviour Modelled in PRISM A Case Study Autonomous Agent Behaviour Modelled in PRISM A Case Study Ruth Hoffmann 1, Murray Ireland 1, Alice Miller 1, Gethin Norman 1, and Sandor Veres 2 1 University of Glasgow, Glasgow, G12 8QQ, Scotland 2 University

More information

RUN-TIME EFFICIENT FEASIBILITY ANALYSIS OF UNI-PROCESSOR SYSTEMS WITH STATIC PRIORITIES

RUN-TIME EFFICIENT FEASIBILITY ANALYSIS OF UNI-PROCESSOR SYSTEMS WITH STATIC PRIORITIES RUN-TIME EFFICIENT FEASIBILITY ANALYSIS OF UNI-PROCESSOR SYSTEMS WITH STATIC PRIORITIES Department for Embedded Systems/Real-Time Systems, University of Ulm {name.surname}@informatik.uni-ulm.de Abstract:

More information

Formal Methods in Software Engineering

Formal Methods in Software Engineering Formal Methods in Software Engineering Modeling Prof. Dr. Joel Greenyer October 21, 2014 Organizational Issues Tutorial dates: I will offer two tutorial dates Tuesdays 15:00-16:00 in A310 (before the lecture,

More information

On the Design of Adaptive Supervisors for Discrete Event Systems

On the Design of Adaptive Supervisors for Discrete Event Systems On the Design of Adaptive Supervisors for Discrete Event Systems Vigyan CHANDRA Department of Technology, Eastern Kentucky University Richmond, KY 40475, USA and Siddhartha BHATTACHARYYA Division of Computer

More information

Formal Models of Timed Musical Processes Doctoral Defense

Formal Models of Timed Musical Processes Doctoral Defense Formal Models of Timed Musical Processes Doctoral Defense Gerardo M. Sarria M. Advisor: Camilo Rueda Co-Advisor: Juan Francisco Diaz Universidad del Valle AVISPA Research Group September 22, 2008 Motivation

More information

A Simplified Approach for Testing Real-Time Systems Based on Action Refinement

A Simplified Approach for Testing Real-Time Systems Based on Action Refinement A Simplified Approach for Testing Real-Time Systems Based on Action Refinement Saddek Bensalem, Moez Krichen, Lotfi Majdoub, Riadh Robbana, Stavros Tripakis Verimag Laboratory, Centre Equation 2, avenue

More information

The Concurrent Consideration of Uncertainty in WCETs and Processor Speeds in Mixed Criticality Systems

The Concurrent Consideration of Uncertainty in WCETs and Processor Speeds in Mixed Criticality Systems The Concurrent Consideration of Uncertainty in WCETs and Processor Speeds in Mixed Criticality Systems Zhishan Guo and Sanjoy Baruah Department of Computer Science University of North Carolina at Chapel

More information

Process Scheduling for RTS. RTS Scheduling Approach. Cyclic Executive Approach

Process Scheduling for RTS. RTS Scheduling Approach. Cyclic Executive Approach Process Scheduling for RTS Dr. Hugh Melvin, Dept. of IT, NUI,G RTS Scheduling Approach RTS typically control multiple parameters concurrently Eg. Flight Control System Speed, altitude, inclination etc..

More information

Composing Heterogeneous Reactive Systems

Composing Heterogeneous Reactive Systems Composing Heterogeneous Reactive Systems ALBERT BENVENISTE and BENOÎT CAILLAUD Irisa/Inria LUCA P. CARLONI Columbia University PAUL CASPI Verimag and ALBERTO L. SANGIOVANNI-VINCENTELLI University of California,

More information

June 8 th Riga, Latvia

June 8 th Riga, Latvia Laurent Fesquet Taha.Beyrouthy@imag.fr Laurent.Fesquet@imag.fr June 8 th 2010- Riga, Latvia Outline Asynchronous logic Non uniform sampling Asynchronous convolution product Asynchronous FIR filter Conclusion

More information

Formally Correct Monitors for Hybrid Automata. Verimag Research Report n o TR

Formally Correct Monitors for Hybrid Automata. Verimag Research Report n o TR Formally Correct Monitors for Hybrid Automata Goran Frehse, Nikolaos Kekatos, Dejan Nickovic Verimag Research Report n o TR-2017-5 September 20, 2017 Verimag, University of Grenoble Alpes, Grenoble, France.

More information

Some lesser-known contributions of Paul Caspi

Some lesser-known contributions of Paul Caspi Some lesser-known contributions of Paul Caspi Jacques pulou With some help from E. Closse and D. Weil France Telecom R&D MAPS/AMS/SUME research & development Paul 's Doctorate Thesis : identifying unstable

More information

Non-Preemptive and Limited Preemptive Scheduling. LS 12, TU Dortmund

Non-Preemptive and Limited Preemptive Scheduling. LS 12, TU Dortmund Non-Preemptive and Limited Preemptive Scheduling LS 12, TU Dortmund 09 May 2017 (LS 12, TU Dortmund) 1 / 31 Outline Non-Preemptive Scheduling A General View Exact Schedulability Test Pessimistic Schedulability

More information

Formal Semantics for Grafcet Controlled Systems 1 Introduction 2 Grafcet

Formal Semantics for Grafcet Controlled Systems 1 Introduction 2 Grafcet Formal Semantics for Grafcet Controlled Systems JANAN ZAYTOON Laboratoire d'automatique et de Microélectronique Faculté des Sciences Moulin de la Housse, BP 1039, 51687 Reims cedex 2 FRANCE Abstract: Grafcet

More information

FAULT-TOLERANT CONTROL OF CHEMICAL PROCESS SYSTEMS USING COMMUNICATION NETWORKS. Nael H. El-Farra, Adiwinata Gani & Panagiotis D.

FAULT-TOLERANT CONTROL OF CHEMICAL PROCESS SYSTEMS USING COMMUNICATION NETWORKS. Nael H. El-Farra, Adiwinata Gani & Panagiotis D. FAULT-TOLERANT CONTROL OF CHEMICAL PROCESS SYSTEMS USING COMMUNICATION NETWORKS Nael H. El-Farra, Adiwinata Gani & Panagiotis D. Christofides Department of Chemical Engineering University of California,

More information

Finally the Weakest Failure Detector for Non-Blocking Atomic Commit

Finally the Weakest Failure Detector for Non-Blocking Atomic Commit Finally the Weakest Failure Detector for Non-Blocking Atomic Commit Rachid Guerraoui Petr Kouznetsov Distributed Programming Laboratory EPFL Abstract Recent papers [7, 9] define the weakest failure detector

More information

Logical Time. 1. Introduction 2. Clock and Events 3. Logical (Lamport) Clocks 4. Vector Clocks 5. Efficient Implementation

Logical Time. 1. Introduction 2. Clock and Events 3. Logical (Lamport) Clocks 4. Vector Clocks 5. Efficient Implementation Logical Time Nicola Dragoni Embedded Systems Engineering DTU Compute 1. Introduction 2. Clock and Events 3. Logical (Lamport) Clocks 4. Vector Clocks 5. Efficient Implementation 2013 ACM Turing Award:

More information

Multicore Semantics and Programming

Multicore Semantics and Programming Multicore Semantics and Programming Peter Sewell Tim Harris University of Cambridge Oracle October November, 2015 p. 1 These Lectures Part 1: Multicore Semantics: the concurrency of multiprocessors and

More information

Degradable Agreement in the Presence of. Byzantine Faults. Nitin H. Vaidya. Technical Report #

Degradable Agreement in the Presence of. Byzantine Faults. Nitin H. Vaidya. Technical Report # Degradable Agreement in the Presence of Byzantine Faults Nitin H. Vaidya Technical Report # 92-020 Abstract Consider a system consisting of a sender that wants to send a value to certain receivers. Byzantine

More information

This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and

This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution

More information

Interface Automata with Complex Actions - Extended Version

Interface Automata with Complex Actions - Extended Version Interface Automata with Complex Actions - Extended Version Shahram Esmaeilsabzali Nancy A. Day Farhad Mavaddat David R. Cheriton School of Computer Science University of Waterloo Waterloo, Ontario, Canada

More information

Special Nodes for Interface

Special Nodes for Interface fi fi Special Nodes for Interface SW on processors Chip-level HW Board-level HW fi fi C code VHDL VHDL code retargetable compilation high-level synthesis SW costs HW costs partitioning (solve ILP) cluster

More information

ECE 448 Lecture 6. Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code. George Mason University

ECE 448 Lecture 6. Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code. George Mason University ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code George Mason University Required reading P. Chu, FPGA Prototyping by VHDL Examples

More information

The Discrete EVent System specification (DEVS) formalism

The Discrete EVent System specification (DEVS) formalism The Discrete EVent System specification (DEVS) formalism Hans Vangheluwe The DEVS formalism was conceived by Zeigler [Zei84a, Zei84b] to provide a rigourous common basis for discrete-event modelling and

More information

A Canonical Contraction for Safe Petri Nets

A Canonical Contraction for Safe Petri Nets A Canonical Contraction for Safe Petri Nets Thomas Chatain and Stefan Haar INRIA & LSV (CNRS & ENS Cachan) 6, avenue du Président Wilson 935 CACHAN Cedex, France {chatain, haar}@lsvens-cachanfr Abstract

More information

Monitoring and Fault-Diagnosis with Digital Clocks

Monitoring and Fault-Diagnosis with Digital Clocks Author manuscript, published in "6th Int. Conf. on Application of Concurrency to System Design (ACSD'06) (2006)" Monitoring and Fault-Diagnosis with Digital Clocks Karine Altisen Verimag Laboratory Karine.Altisen@imag.fr

More information

Decentralized Control of Discrete Event Systems with Bounded or Unbounded Delay Communication

Decentralized Control of Discrete Event Systems with Bounded or Unbounded Delay Communication Decentralized Control of Discrete Event Systems with Bounded or Unbounded Delay Communication Stavros Tripakis Abstract We introduce problems of decentralized control with communication, where we explicitly

More information

Process Algebras and Concurrent Systems

Process Algebras and Concurrent Systems Process Algebras and Concurrent Systems Rocco De Nicola Dipartimento di Sistemi ed Informatica Università di Firenze Process Algebras and Concurrent Systems August 2006 R. De Nicola (DSI-UNIFI) Process

More information

Clock-driven scheduling

Clock-driven scheduling Clock-driven scheduling Also known as static or off-line scheduling Michal Sojka Czech Technical University in Prague, Faculty of Electrical Engineering, Department of Control Engineering November 8, 2017

More information

Bounding the End-to-End Response Times of Tasks in a Distributed. Real-Time System Using the Direct Synchronization Protocol.

Bounding the End-to-End Response Times of Tasks in a Distributed. Real-Time System Using the Direct Synchronization Protocol. Bounding the End-to-End Response imes of asks in a Distributed Real-ime System Using the Direct Synchronization Protocol Jun Sun Jane Liu Abstract In a distributed real-time system, a task may consist

More information

Embedded Systems Design: Optimization Challenges. Paul Pop Embedded Systems Lab (ESLAB) Linköping University, Sweden

Embedded Systems Design: Optimization Challenges. Paul Pop Embedded Systems Lab (ESLAB) Linköping University, Sweden of /4 4 Embedded Systems Design: Optimization Challenges Paul Pop Embedded Systems Lab (ESLAB) Linköping University, Sweden Outline! Embedded systems " Example area: automotive electronics " Embedded systems

More information

Automatic Synthesis of Distributed Protocols

Automatic Synthesis of Distributed Protocols Automatic Synthesis of Distributed Protocols Rajeev Alur Stavros Tripakis 1 Introduction Protocols for coordination among concurrent processes are an essential component of modern multiprocessor and distributed

More information

CS3110 Spring 2017 Lecture 21: Distributed Computing with Functional Processes

CS3110 Spring 2017 Lecture 21: Distributed Computing with Functional Processes CS3110 Spring 2017 Lecture 21: Distributed Computing with Functional Processes Robert Constable Date for Due Date PS6 Out on April 24 May 8 (day of last lecture) 1 Introduction In the next two lectures,

More information

Dependable Computer Systems

Dependable Computer Systems Dependable Computer Systems Part 3: Fault-Tolerance and Modelling Contents Reliability: Basic Mathematical Model Example Failure Rate Functions Probabilistic Structural-Based Modeling: Part 1 Maintenance

More information

UMBC. At the system level, DFT includes boundary scan and analog test bus. The DFT techniques discussed focus on improving testability of SAFs.

UMBC. At the system level, DFT includes boundary scan and analog test bus. The DFT techniques discussed focus on improving testability of SAFs. Overview Design for testability(dft) makes it possible to: Assure the detection of all faults in a circuit. Reduce the cost and time associated with test development. Reduce the execution time of performing

More information

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

More information

Timo Latvala. March 7, 2004

Timo Latvala. March 7, 2004 Reactive Systems: Safety, Liveness, and Fairness Timo Latvala March 7, 2004 Reactive Systems: Safety, Liveness, and Fairness 14-1 Safety Safety properties are a very useful subclass of specifications.

More information

Paper Presentation. Amo Guangmo Tong. University of Taxes at Dallas January 24, 2014

Paper Presentation. Amo Guangmo Tong. University of Taxes at Dallas January 24, 2014 Paper Presentation Amo Guangmo Tong University of Taxes at Dallas gxt140030@utdallas.edu January 24, 2014 Amo Guangmo Tong (UTD) January 24, 2014 1 / 30 Overview 1 Tardiness Bounds under Global EDF Scheduling

More information

Quantitative Safety Analysis of Non-Deterministic System Architectures

Quantitative Safety Analysis of Non-Deterministic System Architectures Quantitative Safety Analysis of Non-Deterministic System Architectures Adrian Beer University of Konstanz Department of Computer and Information Science Chair for Software Engineering Adrian.Beer@uni.kn

More information

Scheduling. Uwe R. Zimmer & Alistair Rendell The Australian National University

Scheduling. Uwe R. Zimmer & Alistair Rendell The Australian National University 6 Scheduling Uwe R. Zimmer & Alistair Rendell The Australian National University References for this chapter [Bacon98] J. Bacon Concurrent Systems 1998 (2nd Edition) Addison Wesley Longman Ltd, ISBN 0-201-17767-6

More information

Barrier. Overview: Synchronous Computations. Barriers. Counter-based or Linear Barriers

Barrier. Overview: Synchronous Computations. Barriers. Counter-based or Linear Barriers Overview: Synchronous Computations Barrier barriers: linear, tree-based and butterfly degrees of synchronization synchronous example : Jacobi Iterations serial and parallel code, performance analysis synchronous

More information