2. General formula for Runge-Kutta methods

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1 NOLTA, IEICE Pper Equivlent circuits for implicit unge-kutt metods in circuit simultors for nonliner circuits Ysuiko Toym 1), Ttusy Kuwzki 1, nd Jun Sirtki 1 Mkiko Okumur 1 1 Kngw Institute of Tecnology, Atsugi-si, Jpn. ) y-toym@ele.kngw-it.c.jp Abstrct: Tis pper describes metod of implementing duiia nd LobttoIIIA of implicit unge-kutt formuls into circuit simultors for nonliner circuits s numericl integrtion. Tese implicit unge-kutt metods ve ig orders nd re A-stble. Equivlent circuits t discrete time for liner nd nonliner elements re proposed. Circuits t times between pst nd present time re needed in ddition to te equivlent circuit t present time. Solutions t intermedite nd present times must be estimted simultneously. So, te size of equivlent circuit becomes lrger tn te numericl integrtion in conventionl circuit simultors. However, since te orders of tese lgoritms re ig, tis problem is solved by using lrger time step for numericl integrtion compred to conventionl metods to sve clcultion time. Te implicit unge-kutt nd conventionl metods re compred in terms of ccurcy nd computtionl costs using exmple circuits. Key Words: implicit unge-kutt metods, duiia, LobttoIIIA, numericl integrtion, trpezoidl 1. Introduction In conventionl time-domin circuit simultors, multistep bckwrd-differentil-formuls suc s Ger s metods nd trpezoidl lgoritm re used to solve ordinry differentil equtions [1-5]. Te order of trpezoidl lgoritm is second nd Ger s metods ve lgoritms of more tn te second order. However, te lter re not prcticlly used. One of te resons is tt tey re not A-stble. It is n importnt problem to implement A-stble ig order integrtion metods into circuit simultor. An licit unge-kutt metod of te fort order is well known [5]. Explicit metods cn evlute nonliner crcteristics by using only vlues t pst times. However, tey re not A-stble nd difficult to implement into te circuit simultor employing modified nodl nlysis [6]. On te oter nd, duiia nd LobttoIIIA in implicit unge-kutt formuls re A-stble even if te order is more tn te second. Terefore, tey re suitble for integrtion metods of te circuit simultion. Implementtion of duiia nd LobttoIIIA in implicit unge-kutt metods for te circuit simultors ws introduced in [7] nd study bot trnsient nd stedy-stte responses of utonomous nd nonutonomous circuits ws described in [8]. Furtermore, equivlent models nd teir equtions of implicit unge-kutt metods for liner nd nonliner elements were proposed in [9, 10]. Since, te [eceived: December 18, evised: My 28, Publised: October 1, 2010.] [DOI: /nolt.1.176] Nonliner Teory nd Its Applictions, IEICE, vol. 1, no. 1, pp. 176N185 IEICE

2 size of equivlent circuits becme lrger tn te conventionl numericl integrtion metods used in stndrd circuit simultors, becuse te equivlent circuits t time between pst nd present re needed in ddition to equivlent circuits t present time. Solutions t intermedite nd present time must be estimted simultneously. However, since implicit unge-kutt formuls suc s duiia nd LobttoIIIA re order 2 or more nd re A-stble, lrger time step for numericl integrtion compred to conventionl metods cn be used to sve clcultion cost. Tis pper describes metod of implementing implicit unge-kutt formuls suc s duiia nd LobttoIIIA into circuit simultors s numericl integrtion. It is bsed on te pper [9] in NOLTA2009. unge-kutt metods re lined in Section 2. An equivlent model for liner element is described in Section 3 nd model for bipolr junction trnsistor BJT) s nonliner elements is proposed in Section 4. In Section 5, comprison of te error between implicit unge-kutt metods nd conventionl metods re described. Computtionl costs of proposed metods nd conventionl metods re discussed using exmple circuits in Section Generl formul for unge-kutt metods For ordinry differentil eqution y = ft, y), unge-kutt metods re given by Y i = y n s j=1 ijf t n c j, Y j ) i = 1, 2,, s) y n1 = y n s i=1 b if t n c i, Y i ) were ec coefficient of 1) is given by Butcer rrngement sown in Tble I [11]. 1) Te formul is Tble I. Butcer rrngement. c s c s c s s1 s2... ss b 1 b 2... b s licit wen te upper tringle coefficients ij i j) re ll 0. Te metod is implicit except tese cses. In duiia nd LobttoIIIA, te upper tringle elements ij i j) re not zero nd ten tey re implicit numericl integrtions. Te prmeter s in Tble I denotes te number of times for evlution. Te order of metods re decided by p = 2s 1 p = 2s 2 for duiia, for LobttoIIIA. Terefore, for duiia, te order is te 3rd wen s = 2 nd te 5t wen s = 3. For LobttoIIIA, te order is te 4t wen s = 3 nd te 6t wen s = 4. Te prmeters c i denote te intermedite times. Te 3rd order-duiia s one intermedite time, s c 1 = 1 3, c 2 = 1. Te 4t order- LobttoIIIA s lso one intermedite time, s c 1 = 0, c 2 = 1 2, c 3 = 1. Z Te 5t order-duiia nd te 6t order-lobttoiiia ve two intermedite times. In implicit unge-kutt metods, te size of equivlent circuits depends on te number of intermedite times. Te scle of circuit increses wen te number of intermedite times increse. Terefore, we discuss te 3rd order-duiia nd te 4t order-lobttoiiia wit one intermedite time. Te 3rd order-duiia nd te 4t order-lobttoiiia, wic re referred to s te 3rd-duIIA nd te 4t-LobttoIIIA, respectively Assuming tt m ij = ij,m 10 = m 20 = 0 in 3rd-duIIA nd m ij = i1)j1) in te 4t- LobttoIIIA, te two implicit unge-kutt metods cn be written s follows [7]: Y t ) yt n ) m 10 ft n ) m 11 ft ) m 12 ft n1 ) = 0 yt n1 ) yt n ) m 20 ft n ) m 21 ft ) m 22 ft n1 ) = )

3 were t n, t nd t n1 indicte pst time, n intermedite time nd present time. 3. Equivlent models for liner element 3.1 Liner cpcitor Applying 2) to ordinry differentil eqution for liner cpcitor : it) = C dv c dt nd rerrnging, Eq. 3) is obtined. m 12 m 22 )v n m 22 v m 12 v n1 i = C m 10m 22 m 12 m 20 )i n C m 11m 22 m 12 m 21 ) m 11 m 21 )v n m 21 v m 11 v n1 i n1 = C m 10m 21 m 11 m 20 )i n C m 11m 22 m 12 m 21 ) Ten, te equivlent circuit is sown in Fig. 1. Te eqution for te simultion is given by B B A A v 1,n1 P B B A A v 2,n1 E E D D v 1, = P F E E D D v 2, F 3) 4) were v 1, nd v 2, re te voltges t n intermedite time t wile v 1,n1 nd v 2,n1 re te v1, v1,n1 v1 vc v2 vc D F v2, E vcn1 P B Avc v2,n1 vcn1 Fig. 1. Equivlent circuit of liner cpcitor for te 3rd-duIIA nd te 4t LobttoIIIA. voltges t present time t n1. Prmeters A nd E denote te coefficients of voltge controlled current source VCCS). Te VCCS wit coefficient A is controlled by v c nd E is controlled by v cn1. Tey re clculted by A = m 21 C m 11m 22 m 12 m 21 ), E = m 12 C m 11m 22 m 12 m 21 ). Prmeters B nd D sow dmittnces tt re coefficients of te voltge t ec moment. Tey re clculted by m 11 B = C m 11m 22 m 12 m 21 ), D = m 22 C m 11m 22 m 12 m 21 ). Prmeters P nd F re independent current sources tt cn be computed from te pst voltge nd current vlues. P = m 11 m 21 )v cn C m 10m 21 m 11 m 20 )i cn C m 11m 22 m 12 m 21 ) F = m 12 m 22 )v cn C m 10m 22 m 12 m 20 )i cn C m 11m 22 m 12 m 21 ) Te size of te equivlent circuits in te 3rd-duIIA nd te 4t-LobttoIIIA becomes twice s lrge s trpezoidl metod nd te vribles in te equtions become lso twice becuse tey include ones t intermedite time. 178

4 4. Implementtion into BJT Consider Gummel-Poon model for BJT re sown in Fig. 2. It consists of contct resistnces, diodes nd VCCS. C i C C v BC i C v BC cin D 1 B i B B i B bin i 1 i 2 i CE v BE Fig. 2. i D 2 E i E v BE E E Gummel-Poon model for BJT. ein 4.1 Equivlent model for diode ig s ic v gv) qv) Fig. 3. Diode model. A model of diode is sown in Fig. 3. It consists of contct resistnce s, nonliner conductnce gv) nd nonliner cpcitor qv) Lineriztion nd numericl integrtion for nonliner cpcitor We ssume tt te reltionsip of te current i c nd te cpcitor voltge v re given by i c t) = dqv) ) dt ) v qv) = T t I s 1 NV t were T t, I s nd N ec sows run time, sturtion current nd n emission coefficient. Applying 2) to ordinry differentil eqution 5) nd linerizing by Newton metod, we rec Eq. 6), were represents te number of Newton itertion. i c = m 22 α qv ) C v i cn1 = m 11 α qv n1 ) C n1 v v )} m 12 α } qv n1 ) C n1 v n1 v n1 ) 1 α m 12 m 22 )qv n ) m 10 m 22 m 12 m 20 )C n )} } )} n1 v n1 ) m 21 α qv ) C v v m21 m 11 )qv n) ) m 10 m 21 m 11 m 20 )C n ) } 1 α Prmeters C, C n1, C n nd α in 6) re given by C = qv) v C n = qv) v v=v C n1 = qv) v v=v n1 α = m 11 m 22 m 12 m 21 ). v=vn 179 5) 6)

5 Eqution 6) is rewritten by followings: i c = G c v g cn1 v n1 I c i cn1 = G cn1 v n1 g c v I cn1 7) were G c nd G cn1 re conductnces nd decided by G c = m 22 α C G cn1 = m 11 α C n1, g cn1 nd g c in 7) sow te coefficients of VCCS. Te VCCS wit coefficient g cn1 is connected to te equivlent circuit t t nd controlled by voltge t t n1. Prmeter g c is connected to te equivlent circuit t t n1 nd controlled by voltge t t. Tey re determined by I k c nd I k cn1 in 7) re given by were ec term is clculted by I c1 I c2 i c1 i c2 g cn1 = m 12 α C n1 g c = m 21 α C. = m 22/α) = m 11/α) = m 12/α) = m 21/α) I c = I c1 I cn1 = I c2 qv i c1 I c1n i c2 I c2n ) T t I s C } v } qv n1 ) T ti s C n1 v n1 } C n1 v n1 qv n1 ) T ti s C v I c1n = T t I s m 12 m 22 )/α qv ) T t I s } T ti s α [m 12 m 22 ) m 10 m 22 m 12 m 20 )} qv n ) T t I s 1] I c2n = T t I s m 21 m 11 )/α T ti s α [m 21 m 11 ) m 10 m 21 m 11 m 20 )} qv n ) T t I s 1] Lineriztion for nonliner conductnce Nonliner conductnce is linerized by pplying Newton metod t bot t nd t n1, s te 3rd- duiia nd te 4t-LobttoIIIA ve one intermedite point. Ten, te equivlent model for nonliner conductnce consists of conductnces G g nd G gn1 nd independent current sources I g nd I gn1 wic re prllel wit ec oter, were I g G g = gv) v v=v = gv ) G g v G gn1 = gv) v v=v n1 I gn1 = gv n1 ) G gn1 v n Equivlent circuit for diode An equivlent circuit t j 1) Newton itertion nd n 1) discrete time for diode is sown in Fig. 4, were G = G g G c I = I g I c G = G gn1 G cn1 I Ten, te eqution for te simultion is given by Eq. 8). 180 = I gn1 I cn1.

6 G s G s G s G s G G g cn1 g cn1 G G g c g c G s G s g cn1 G s G s G g cn1 G g c g c G G v 1,n1 v 2,n1 v 3,n1 v 1, v 2, v 3, = I I I I 8) v1 v1 n1 v2 Gs v2 n1 Gs v G I gcn1 vn1 vn1 G I gc v v3 v3 n1 Fig. 4. Equivlent circuit for diode. From Fig. 4, te size of te equivlent circuits in te 3rd-duIIA nd te 4t-LobttoIIIA becomes twice s lrge s trpezoidl metod nd te vribles in te equtions become lso twice becuse tey include ones t intermedite time. 4.2 Implementtion into voltge controlled current source i CE Voltge controlled current source i CE in Fig. 2 is controlled by v BC nd v BE nd it is given by i CE = I } }) S vbe vbc, Q B N F V T N V T were Q B is bse crge density, N F nd N re forwrd nd reverse current emission coefficients. V T is clled terml voltge nd is given by kt/q. Assuming tt i CE = f CE v BE, v BC ), we pply Newton metod to voltges nd currents t present nd intermedite times. Ten, i CEn1) i CE) re given by i CEn1) = i 0n1) g BCn1) v BCn1) g BEn1) v BEn1) 9) Prmeters g BEn1) ec time. Prmeters g BCn1) v BC t ec time. Prmeters i 0n1) prmeter re sown by followings : i CE) = i 0) g BC) v BC) g BE) v BE) 10) nd g BE) denote te coefficients of VCCS. Tey re controlled by v BE t denote te coefficients of VCCS. Tey re controlled by nd g BC) nd i 0) g BEn1) = v ) I S BEn1) Q Bn1) N F V T N F V T g BE) = v ) I S BE) Q B) N F V T N F V T g BCn1) = v I S BCn1) Q Bn1) N V T N V T g BC) = v ) I S BC) Q B) N V T N V T i 0n1) = I S Q 1 v! v BEn1) Bn1) N F V T i 0) = I S Q B) re independent current sources. Te results of ec 1 v BCn1) 1 v! BE) N F V T N V T ) v BE) N F V T ) 1 v BC) N V T ) 181 ) BEn1) N F V T ) } v BCn1) N V T } v BC) N V T

7 4.3 Equivlent circuit for BJT An equivlent circuit t j 1) Newton itertion nd n 1) discrete time for BJT is sown in Fig. 5. v BC ) i C ) C cin v BC n1) i C n1) C cin B i B ) G1) bin I1 g1cn1v BC n1) i 0 ) gbe vbe ) ) gbc ) vbc ) B i B n1) G1 n1) bin I1 g1cn1v BC ) i 0 n1) gbe vbe n1) n1) gbc n1) vbc n1) G2 ) I2 g2cn1 v BE n1) G2 n1) I2 g2cn1 v BE ) v BE ) i E ) ein v BE n1) i E n1) ein Fig. 5. Equivlent circuit for BJT. 5. Comprison of te error wit te conventionl metod Te estimted error of te trpezoidl, te 3rd-duIIA nd te 4t-LobttoIIIA for n C circuit sown in Fig. 6, ε is clculted by ε = c v v 100[%] were v c is n exct solution t t = 1[s] clculted from v c t) = E 1 t ) C v c nd v is numericl solution of ec numericl integrtion metod. An exct solution is used s te pst vlue to clculte te present numericl solution. Te results re sown in Fig. 7, were te orizontl xis sows te time step nd te verticl xis sows te error. According to te grp, lrger time steps cn be used in implicit unge-kutt metods in order to obtin te sme ccurcy s te trpezoidl rule. For exmple, te 3rd-duIIA cn use 3.6 times te numericl integrtion time step s lrge s te trpezoidl rule nd te 4t-LobttoIIIA cn use 8.6 times s lrge time step s te trpezoidl wit [%] error. 500kΩ E 10V 1µF C - vc Fig. 6. C circuit. 6. Comprison of computtionl costs Te computtionl costs between proposed implicit unge-kutt metods nd te trpezoidl metod re compred using n C circuit in Fig. 6, diode circuit in Fig. 8 nd n mplifier circuit in Fig. 9. Clcultion time of two implicit unge-kutt metods nd trpezoidl for C circuit is sown in Fig. 10, were te orizontl xis is te time step of numericl integrtion nd te verticl xis is 182

8 Trpezoidl2nd) duiia3rd) LobttoIIIA4t) Error [%] Time step [sec] Fig. 7. Error of ec numericl integrtion. clcultion time. Te computtionl costs of unge-kutt metods nd trpezoidl becme lmost te sme in tis cse. We consider tt unge-kutt metods wit ig ccurcy re superior to trpezoidl for liner nd smll scle circuits. Clcultion time of unge-kutt metods nd trpezoidl for diode circuit is Fig. 11. According to te grp, te computtionl costs of unge- Kutt metods nd trpezoidl become te sme if unge-kutt metods use bout 3.9 times te step size s te trpezoidl. Clcultion time of unge-kutt metods nd trpezoidl for mplifier circuit is Fig. 12. According to te grp, te computtionl costs of tese metods become te sme if unge-kutt metods use bout 4.5 times te step size s te trpezoidl. In implicit unge- Kutt metods, Newton itertion must be pplied to te circuits t intermedite times nd present time. Ten, clcultion of te prmeters in 8) for te equivlent model of BJT in te mplifier circuit becomes lrger tn tt for te diode circuit. Terefore, numericl integrtion time step for te mplifier circuit to obtin computtionl costs sme s te trpezoidl becomes lrger tn tt for diode circuit. In ddition, iger ccurcy is obtined for te 4t-LobttoIIIA tn trpezoidl metod, even if we use lrger time step tn trpezoidl. sin2πft) f=1k 1kΩ Output voltge Fig. 8. Diode circuit. Vin=10sinwt [mv] f=1[khz] =58.3k b=12.5k c=5.1k e=1.5k Cx=20u v in Cy=300u - Vcc=12 Cx b i B i C i E c e v out - Cy i CC Vcc Fig. 9. Amplifier circuit. Assuming tt computtionl cost increses in proportionl to N 1.5, wee N is number of vribles, under considertion of sprse mtrix, computtionl cost becomes times te trpezoidl, becuse te numbers of vribles for te 3rd-duIIA nd 4t-LobttoIIIA re twice. equired memories for te 3rd-duIIA nd te 4t-LobttoIIIA become bout 2 2 = 4 times s lrge s trpezoidl, since te scles of teir circuits re twice te size. 7. Conclusion Tis pper described te tecnique for implementing two types of implicit unge-kutt formuls, te 3rd-duIIA nd te 4t-LobttoIIIA s numericl integrtion into nonliner elements, wic re 183

9 Clcultion time [sec] Trpezoidl duiia3rd) LobttoIIIA4t) Fig Time step [sec] Clcultion time of tree metods in C circuit. Clcultion time [sec] Trpezoidl2nd) duiia3rd) LobttoIIIA4t) bout 3.9 times Fig Time step [sec] Clcultion time of tree metods in diode circuit Trpezoidl2nd) duiia3rd) LobttoIIIA4t) Clcultion time[sec] bout 4.5 times Fig Time step [sec] Clcultion time of tree metods in mplifier circuit. A-stble nd ve ig orders. Te equivlent circuits nd teir equtions of liner nd nonliner elements for te simultion re proposed. For tese implicit unge-kutt metods, te equivlent circuit t one intermedite time ws necessry in ddition to te equivlent circuit t present time. Terefore, ltoug computtionl cost increses from te trpezoidl metod, lrger time steps of numericl integrtion cn be used in order to obtin te sme ccurcy s trpezoidl. Te time step wic mkes te sme computtionl costs s trpezoidl, te 4t-LobttoIIIA cn obtin muc iger ccurcy tn trpezoidl. Te proposed metod is effective for te simultors of te circuits wose scle is smll nd ccurcy is required, since computtionl cost will increse if nonliner elements increse. eferences [1] L.O. Cu nd P.-M. Lin, Computer-Aided Anlysis of Electronic Circuits: Algoritns nd Computtionl Tecniques, Prentice-Hll, Inc., Englewood Cliffs, N.J., [2] C.W. Ger, Numericl Initil Vlue Problems in Ordinry Differentil Equtions, Prentice-Hll, [3] L.W. Ngel nd D.O. Pederson, SPICE-simultion progrm wit integrted circuit empsis, Memo., no. EL-M382, Univ. of Cliforni, Berkley, April

10 [4] L. Ngel, SPICE2: A Computer Progrm to Simulte Semiconductor Circuits, Memo., no. EL- M520, Univ. of Cliforni, Berkley, My [5] A. Usid nd M. Tnk, Computer Simultions of Electronic Circuits, Coron Publising Co., LTD., Jpnese edition, [6] C. Ho, A.E. eli, nd P. Brennn, Te modified nodl proc to net work nlysis, IEEE Trns. Circuits nd Systems., vol. CAS-22, no. 6, pp , June [7] P. Mffezzoni, L. Codecs, nd D. D Amore, Time-domin simultion of nonliner circuits troug implicit unge-kutt metods, IEEE Trns. Circuits nd Systems., vol. 54, no. 2, pp , [8] P. Mffezzoni, A verstile time-domin pproc to simulte oscilltors in F circuits, IEEE Trns. Circuits nd Systems., vol. 56, no. 3, pp , [9] Y. Toym, J. Sirtki, nd M. Okumur, Implementtion of implicit unge-kutt metods into circuit simultors for nonliner circuits, Proc. NOLTA 09, [10] Y. Tkkur, Y. Toym, J. Sirtki, nd M. Okumur, An implementtion in to te circuit simultion of implicit unge-kutt metods, IEICE Trns. on Fundmentls Electronics, Communiction nd Computer, Jpnese edition, vol. J92-A, no. 11 pp , [11] E. Hirer, G. Wnner, nd S.P. Nørsett, Solving Ordinry Differentil Equtions I, Springerverlg, Berlin, Heidelberg, [12] E. Hirer nd G. Wnner, Solving Ordinry Differentil Equtions II, Springer-verlg, Berlin, Heidelberg,