Permission to copy without fee all or part of this material is granted, provided that the copies are not made or distributed for direct commercial

Transcription

1 Precomputation-Based Sequential Loic Optimization or Low Power Mazhar Alidina, Jose Monteiro, Srinivas Devadas Department o EECS MIT, Cambride, MA Marios Papaethymiou Department o EE Yale University, CT Abhijit Ghosh MERL Sunnyvale, CA Abstract We address the problem o optimizin loic-level sequential circuits or low power. We present a powerul sequential loic optimization method that is based on selectively precomputin the output loic values o the circuit one clock cycle beore they are required, and usin the precomputed values to reduce internal switchin activity in the succeedin clock cycle. We present two dierent precomputation architectures which exploit this observation. We present an automatic method o synthesizin precomputation loic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Upto 75% reductions in averae switchin activity and power dissipation are possible with marinal increases in circuit area and delay. 1 Introduction Averae power dissipation has recently emered as an important parameter in the desin o eneral-purpose and application-specic interated circuits. Optimization or low power can be applied at many dierent levels o the desin hierarchy. For instance, alorithmic and architectural transormations can trade o throuhput, circuit area, and power dissipation [5], and loic optimization methods have been shown to have a sinicant impact on the power dissipation o combinational loic circuits [12]. In CMOS circuits, the probabilistic averae switchin activity o a circuit is a ood measure o the averae power dissipation o the circuit. Averae power dissipation can thus be computed by estimatin the averae switchin activity. Several methods to estimate power dissipation or CMOS combinational circuits have been developed (e.., [7, 10]). More recently, ecient and accurate methods o power dissipation estimation or sequential circuits have been developed [9, 13]. In this work, we are concerned with the problem o optimizin loic-level sequential circuits or low power. Previous work in the area o sequential loic synthesis or low power has ocused on state encodin (e.., Currently at AT&T Bell Laboratories, Allentown, PA [11]) and retimin [8] alorithms. We present apower- ul sequential loic optimization method that is based on selectively precomputin the output loic values o the circuit one clock cycle beore they are required, and usin the precomputed values to reduce internal switchin activity in the succeedin clock cycle. The primary optimization step is the synthesis o the precomputation loic, which computes the output values or a subset o input conditions. I the output values can be precomputed, the oriinal loic circuit can be \turned o" in the next clock cycle and will not have any switchin activity. Since the savins in the power dissipation o the oriinal circuit is oset by the power dissipated in the precomputation phase, the selection o the subset o input conditions or which the output is precomputed is critical. The precomputation loic adds to the circuit area and can also result in an increased clock period. Given a loic-level sequential circuit, we present an automatic method o synthesizin the precomputation loic so as to achieve a maximal reduction in switchin activity. We present experimental results on various sequential circuits. For some circuits, 75% reductions in averae power dissipation are possible with marinal increases in circuit area and delay. The model we use to relate switchin activity to power dissipation can be ound in [7]. In Section 2 we describe two dierent precomputation architectures. An alorithm that synthesizes precomputation loic so as to achieve power dissipation reduction is presented in Section 3. In Section 4 we describe a method or multiple-cycle precomputation. In Section 5 we describe additional precomputation architectures which are the subject o onoin research. Experimental results are presented in Section 6. 2 Precomputation Architectures We describe two dierent precomputation architectures and discuss their characteristics in terms o their impact on power dissipation, circuit area and circuit delay. 2.1 First Precomputation Architecture Consider the circuit o Fiure 1. We have a combinational loic block A that is separated by reisters R 1 Permission to copy without ee all or part o this material is ranted, provided that the copies are not made or distributed or direct commercial advantae, the ACM copyriht notice and the title o the publication and its date appear, and notice is iven that copyin is by permission o the Association or Computin Machinery. To copy otherwise, or to republish, requires a ee and/or speciic permission ACM /94/0011/0074 $3.50

2 x 1 A x 1 A R3 x n x n Fiure 1: Oriinal Circuit x 1 1 x n A Fiure 2: First Precomputation Architecture and R 2. While R 1 and R 2 are shown as distinct reisters in Fiure 1 they could, in act, be the same reister. We will rst assume that block A has a sinle output and that it implements the Boolean unction. The rst precomputation architecture is shown in Fiure 2. Two Boolean unctions 1 and 2 are the predictor unctions. We require: FF FF 1 =1 ) =1 (1) 2 =1 ) =0 (2) Thereore, durin clock cycle t i either 1 or 2 evaluates to a 1, we set the load enable sinal o the reister R 1 to be 0. This means that in clock cycle t + 1 the inputs to the combinational loic block A do not chane. I 1 evaluates to a1inclock cycle t, the input to reister R 2 is a 1 in clock cycle t + 1, and i 2 evaluates to a 1, then the input to reister R 2 is a 0. Note that 1 and 2 cannot both be 1 durin the same clock cycle due to the conditions imposed by Equations 1 and 2. Apower reduction in block A is obtained because or a subset o input conditions correspondin to the inputs to A do not chane implyin zero switchin activity. However, the area o the circuit has increased due to additional loic correspondin to 1, 2, the two additional ates shown in the ure, and the two ip- ops marked FF. The delay between R 1 and R 2 has increased due to the addition o the and-or ate. Note also that 1 and 2 add to the delay o paths that oriinally ended at R 1 but now pass throuh 1 or 2 and the nor ate beore endin at the load enable sinal o the reister R 1. Thereore, we would like to apply this transormation on non-critical loic blocks. The choice o 1 and 2 is critical. We wish to include as many input conditions as we can in 1 and 2. In other words, we wish to maximize the probability o 1 or 2 evaluatin to a 1. In the extreme case this probability can be made unityi 1 =and 2 =. However, this would imply a duplication o the loic block A and Fiure 3: Second Precomputation Architecture no reduction in power with a twoold increase in area! To obtain reduction in power with marinal increases in circuit area and delay, 1 and 2 have to be sinicantly less complex than. One way o ensurin this is to make 1 and 2 depend on sinicantly ewer inputs than. This leads us to the second precomputation architecture o Fiure Second Precomputation Architecture In the architecture o Fiure 3, the inputs to the block A have been partitioned into two sets, correspondin to the reisters R 1 and R 2. The output o the loic block A eeds the reister R 3. The unctions 1 and 2 satisy the conditions o Equations 1 and 2 as beore, but 1 and 2 only depend on a subset o the inputs to. I 1 or 2 evaluates to a 1 durin clock cycle t, the load enable sinal to the reister R 2 is turned o. This implies that the outputs o R 2 durin clock cycle t + 1 do not chane. However, since the outputs o reister R 1 are updated, the unction will evaluate to the correct loical value. A power reduction is achieved because only a subset o the inputs to block A chane which should produce reduced switchin activity in most cases. As beore, 1 and 2 have to be sinicantly less complex than and the probability o bein a 1 should be hih in order to achieve substantial power ains. The delay o the circuit between R 1 /R 2 and R 3 is unchaned, allowin precomputation o loic that is on the critical path. However, the delay o paths that oriinally ended at R 1 /R 2 has increased. The choice o inputs to 1 and 2 has to be made rst, and then the particular unctions that satisy Equations 1 and 2 have to be selected. A method to perorm this selection is described in Section An Example We ive an example that illustrates the act that substantial power ains can be achieved with marinal increases in circuit area and delay. The circuit we are considerin is a n-bit comparator that compares two n-bit numbers C and D and computes the unction C > D. The optimized circuit with precomputation loic is shown in Fiure 4. The precomputation loic is as ollows. 1 = Chn 1i Dhn 1i

3 C<n 1> D<n 1> C<n 2> D<n 2> C<0> D<0> C > D Fiure 4: A Comparator Example 2 = Chn 1i Dhn 1i Clearly, when 1 =1,Cis reater than D, and when 2 =1,C is less than D. We have to implement = Chn 1i Dhn 1i where stands or the exclusive-nor operator. Assumin a uniorm probability or the inputs 1, the probability that the xnor ate evaluates to a 1 is 0:5, reardless o n. For lare n, we can nelect the power dissipation in the xnor R3 ate, and thereore, we can expect to achieve a power reduction o close to 50%. The reduction will depend upon the relative power dissipated by the vector pairs with Chn 1i Dhn 1i= 1 and the vector pairs with Chn 1i Dhn 1i =0. I we add the inputs Chn 2i and Dhn 2i to 1 and 2 we expect to achieve a power reduction close to 75%. 3 Synthesis o Precomputation Loic 3.1 Introduction In this section, we will describe methods to determine the unctionality o the precomputation loic, and then describe methods to eciently implement the loic. We will ocus primarily on the second precomputation architecture illustrated in Fiure 3. In order to ensure that the precomputation loic is sinicantly less complex than the combinational loic in the oriinal circuit, we will restrict ourselves to identiyin 1 and 2 such that they depend on a relatively small subset o the inputs to the loic block A. 3.2 Precomputation and Observability Don't- Cares Assume that we have a loic unction (X), with X = x 1 ; ; x n, correspondin to block A o Fiure 2. Given that the loic unction implemented by block A is, then the observability don't-care set or input x i is iven by: ODC i = xi xi + xi xi where xi and xi are the coactors o with respect to x i, and similarly or. 1 The assumption here is that each C hii and Dhii has a 0:5 static probability o bein a 0 or a 1. I we determine that a iven input combination is in ODC i then we can disable the loadin o x i into the reister. I we wish to disable the loadin o reisters x m ; x m+1 ; ; x N, we will have to implement the unction: = NY i=m ODC i and use as the (active low) load enable sinal or the reisters correspondin to x m ; x m+1 ; ; x N. 3.3 Precomputation Loic Consider the architecture o Fiure 3. Assume that the inputs x 1 ; ; x m, with m<nhave been selected as the variables that 1 and 2 depend on. We have to nd 1 and 2 such that they satisy the constraints o Equations 1 and 2, respectively, and such that prob( = 1) is maximum. We can determine 1 and 2 usin universal quantication on. The universal quantication o a unction with respect to a variable x i is dened as: U xi = xi xi Given a subset o inputs S = x 1 ; ; x m, set D = X S. We can dene: U D = U xm+1...u xn Theorem = U D satises Equation 1. Further, no unction h(x 1 ; ; x m ) exists such that prob(h = 1) > prob( 1 = 1) and such that h = 1 ) =1. Proo. By construction, i or some input combination a 1 ; ; a m causes 1 (a 1 ; ; a m ) = 1, then or that combination o x 1 ; ; x m and all possible combinations o variables in x m+1 ; ; x n (a 1 ; ; a m ; x m+1 ; ; x n )=1. We cannot add any minterm over x 1 ; ; x m to 1 because or any minterm that is added, there will be some combination o x m+1 ; ; x n or which (x 1 ; ; x n ) will evaluate to a 0. Thereore, we cannot nd any unction h that satises Equation 1 and such that prob(h =1)>prob( 1 = 1). Similarly, iven a subset o inputs S, we can obtain a maximal 2 by: 2 = U D = U xm+1...u xn We can compute the unctionality o the precomputation loic as Selectin a Subset o Inputs Given a unction we wish to select the \best" subset o inputs S o cardinality k. Given S, wehaved=x S and we compute 1 = U D, 2 = U D. In the sequel, we assume that the best set o inputs corresponds to the inputs which result in prob( = 1) bein maximum or a iven k. We know that prob( =1) =prob( 1 =1)+prob( 2 = 1) since 1 and 2 cannot

4 SECT INPUTS(, k ): /* = unction to precompute */ /* k = # o inputs to precompute with */ BEST PROB = 0; SECTED SET = ; SECT RECUR(,,, X, jxj k ); return( SECTED SET ) ; SECT RECUR( a, b, D, Q, l ): i( jdj + jqj <l) pr = prob( a =1)+prob( b =1); i( pr BEST PROB ) else i( jdj == l ) BEST PROB = pr ; SECTED SET = X D ; choose x i 2 Q such that i is minimum ; SECT RECUR( U xi a, U xi b, D [ x i, Q x i, l ); SECT RECUR( a, b, D, Q x i, l ); Fiure 5: Procedure to Determine the Optimal Set o Inputs both be 1 on the same input vector. The above cost unction inores the power dissipated in the precomputation loic, but since the number o inputs to the precomputation loic is sinicantly smaller than the total number o inputs, this is a ood approximation. A branch and bound alorithm is used to determine the optimal set o inputs maximizin the probability o the 1 and 2 unctions. This alorithm is shown in pseudo-code in Fiure 5 and is described in detail in [1] Implementin the Loic The Boolean operations o or and universal quantication required in the input selection procedure can be carried out eciently usin reduced, ordered Binary Decision Diarams (ROBDDs) [4]. We obtain a ROBDD or the unction. AROBDD can be converted into a multiplexor-based network (see [2]) or into a sumo-products cover. The network or cover can be optimized usin standard combinational loic optimization methods that reduce area [3] or those that taret low power dissipation [12]. 3.4 Multiple-Output Functions In eneral, we have a multiple-output unction 1 ; ; m that corresponds to loic block A in Fiures 2 and 3. All the procedures described thus ar can be eneralized to the multiple-output case. The unctions 1i and 2i are obtained usin the equations below. 1i = U D i 2i = U D i where D = X S as beore. The unction whose complement drives the load enable sinal is obtained as: = my i=1 ( 1i + 2i ) The unction corresponds to the set o input conditions where the variables in S control the values o all the i 's reardless o the values o variables in D = X S Selectin a Subset o Outputs In eneral, it is hard to nd a set o inputs or which every output o a multiple-output unction is precomputable. We have developed an alorithm, which iven amultiple-output unction, selects a subset o outputs and a subset o inputs so as to maximize a iven cost unction that is dependent on the probability o the precomputation loic and the number o selected outputs. This alorithm is described in pseudo-code in Fiure 6 and is described in detail in [1]. Since we are only precomputin a subset o outputs, wemay incorrectly evaluate the outputs that we are not precomputin as we disable certain inputs durin particular clock cycles. I an output that is not bein precomputed depends on an input that is bein disabled, then the output will be incorrect. Once a set o outputs G F and a set o precomputation loic inputs S X have been selected, we need to duplicate the reisters correspondin to (support(g) S) \ support(f G). The inputs that are bein disabled are in support(g) S. Loic in the F G outputs that depends on the set o duplicated inputs has to be duplicated as well. It is precisely or this reason that we maximize prg ates(g)/total ates rather than prg in the output-selection alorithm as we want to reduce the amount o duplication as much as possible. 4 Multiple Cycle Precomputation 4.1 Basic Stratey It is possible to precompute output values that are not required in the succeedin clock cycle, but required 2 or more clock cycles later. We ive an example illustratin multiple-cycle precomputation. Consider the circuit o Fiure 7. The unction computes (C + D) > (X + Y )intwo clock cycles. Attemptin to precompute C + D or X + Y usin the methods o the previous section do not result in any savins because there are too many outputs to consider. However, 2-cycle precomputation can reduce switchin activity by close to 12:5% i the unctions below are used. 1 = Chn 1iDhn 1iXhn 1iYhn 1i

5 SECT OUTPUTS( F = 1 ; ; m, k ): /* F = multi-output unc. to precompute */ /* k = # o inputs to precompute with */ BEST COST=0; SEL OP SET = ; SECT OREC(, F,1,k); return( SEL OP SET); C D + R5 K > R7 SECT OREC( G, H, proldg, k ): l = ates(g [ H)/total ates proldg ; i( l BEST COST ) BEST PROB = total ates/ates(g [ H) BEST COST ; i( G 6= ) i( SECT INPUTS( G, k )==) prg = BEST PROB ; cost = prg ates(g)/total ates ; i( cost > BEST COST) BEST COST = cost ; SEL OP SET = G ; choose i 2 H such that i is minimum ; SECT OREC( G [ i, H i, prg, k ); SECT OREC( G, H i, prg, k ); X R3 Y R4 x[2:n] + R6 Fiure 7: Adder-Comparator Circuit x1 x1 L 0 1 R4 Fiure 6: Procedure to Determine the Optimal Set o Outputs 2 = Chn 1iDhn 1iXhn 1iYhn 1i where 1 and 2 satisy the constraints o Equations 1 and 2, respectively. Since prob( )= 2 =0:125, 16 we can disable the loadin o reisters Chn 2 : 0i, Dhn 2: 0i, Xhn 2: 0i, and Y hn 2: 0i12:5% o the time, which results in switchin activity reduction. This percentae can be increased to over 45% by usin Chn 2i throuh Y hn 2i. We can additionally use sinlecycle precomputation loic (as illustrated in Fiure 4) to urther reduce switchin activity in the > comparator o Fiure 7. More examples o this technique can be ound in [1]. 5 Other Precomputation Architectures In this section, we describe additional precomputation architectures. We rst present an architecture that is applicable to all loic circuits and does not require, or instance, that the inputs should be in the observability don't-care set in order to be disabled. This was the case or the architectures shown in Section 2. We also extend precomputation so that it can be used in combinational loic circuits. x 1 R3 Fiure 8: Precomputation Usin the Shannon Expansion 5.1 Multiplexor-Based Precomputation All loic unctions can be written in a Shannon expansion. For the unction with inputs X = x 1 ; ;x n, we can write: = x 1 x1 + x 1 x1 (3) where x1 and x1 are the coactors o with respect to x 1. Fiure 8 shows an architecture based on Equation 3. We implement the unctions x1 and x1. Dependin on the value o x 1, only one o the coactors is computed while the other is disabled by settin the load-enable sinal o its input reister. The input x 1 drives the select line o a multiplexor which chooses the correct coactor. The main advantae o this architecture is that it applies to all loic unctions. The input x 1 in the example was chosen or the purpose o illustration. In act, any

6 x 1 x 3 x 4 x 5 x 1 x 3 x 4 x 5 A A B (a) Oriinal Network (b) Final Network Fiure 9: Combinational Loic Precomputation input x 1 ; ;x n could have been selected. Unlike the architectures described earlier, we do not require that the inputs bein disabled should be don't-cares or the input conditions which we are precomputin. In other words, the inputs bein disabled do not have to be in the observability don't-care set. A disadvantae o this architecture is that we need to duplicate the reisters or the inputs not bein used to turn o part o the loic. On the other hand, no precomputation loic unctions have been added to the circuit. The alorithm to select the best input or this architecture is also quite dierent. We will not discuss this alorithm in detail, except to mention that in this case, we are interested in ndin the input that yields the most area ecient x1 and x1 unctions. 5.2 Combinational Loic Precomputation The architectures described so ar apply only to sequential circuits. We now describe precomputation o combinational circuits. Suppose we have some combinational loic unction composed o two sub-unctions A and B as shown in Fiure 9(a). Suppose we also want to precompute this unction with the inputs x 4 and x 5. Fiure 9(b) shows how this can be accomplished. For simplicity, pass transistors, instead o transmission ates, are shown. The unction with inputs x 4 and x 5 drives the ates o the pass transistors. As in the previous architectures, = Hence, when is a 0, the pass transistors are turned o and the new values o loic block A are prevented rom propaatin into loic block B. The inputs x 4 and x 5 are also inputs to the loic block B just as in the oriinal network in order to ensure that the output is set correctly. For the combinational architecture, there is an implied delay constraint, i.e. the pass transistors should B be o beore the new values o A are computed. In the example shown, the worst-case delay o the block plus the arrival time o inputs x 4 or x 5 should be less than the best-case delay o loic block A plus the arrival time o the inputs x 1,,orx 3. The arrival time o an input is dened as the time at which the input settles to its steady state value [6]. I the delay constraint is not met, then it may be necessary to delay the x 1,, and x 3 inputs with respect to the x 4 and x 5 inputs in order to et the switchin activity reduction in loic block B. 6 Experimental Results At rst we present results on datapath circuits such as carry-select adders, comparators, and interconnections o adders and comparators in Table 1. The precomputation architecture o Fiure 3 was used in all examples and the selection o outputs and inputs to use or precomputation was done manually or examples csa16, add comp16 and add max16 and automatically (usin the alorithms outlined in Fiures 5 and 6) or the rest. For each circuit, the number o literals, levels o loic and power o the oriinal circuit, the number o inputs, literals and levels o the precompute loic, the nal power and the percent reduction in power are shown. All power estimates are in micro-watts and are computed usin the techniques described in [7]. A zero delay model and a clock requency o 20MHz was assumed. The rued script o sis was used to optimize the precompute loic. Power dissipation decreases or almost all cases. For circuit comp16, a 16-bit parallel comparator, the power decreases by asmuch as 60% when 8 inputs are used or precomputation. Multiple-cycle precomputation results are iven or circuits add comp16 and add max16. The circuit add comp16 is shown in Fiure 7, and the circuit add max16 is the same circuit with the comparator replaced by a maximum unction. For circuit add comp16, or instance, the numbers 4/8 under the th column indicates that 4 inputs are used to precompute the adders in the rst cycle and 8 inputs are used to precompute the comparator in the next cycle. Results on random loic circuits are presented in Table 2. The random loic circuits are taken rom the MCNC combinational benchmark sets. We have presented results or those examples where sinicant savins in power was obtained. Once aain, the same precomputation architecture and input and output selection alorithms are used as in Table 1 and the columns have the same meanin, except or the second and third columns which show the number o inputs and outputs o each circuit. It is noteworthy that in some cases, as much as 75% reduction in power dissipation is obtained. The area penalty incurred is indicated by the number o literals in the precomputation loic and is 3% on the averae. The extra delay incurred is proportional to the number o levels in the precomputation loic and is quite small in most cases. It should be noted that it may be possible to use the other precomputation architectures or all o the examples presented here. Some o these examples are perhaps better suited to other architectures than the one we used do derive

7 the results, and thereore larer savins in power may be possible. Secondly, the inputs and outputs to be selected and the precomputation loic are determined automatically, makin this approach suitable or automatic loic synthesis systems. Finally, the sinicant power savins obtained or random loic circuits indicate that this approach is not restricted only to certain classes o datapath circuits. 7 Conclusions and Onoin Work We have presented a method o precomputin the output response o a sequential circuit one clock cycle beore the output is required, and exploited this knowlede to reduce power dissipation in the succeedin clock cycle. Several dierent architectures that utilize precomputation loic were presented. In a nite state machine there is typically a sinle reister, whose inputs are combinational unctions o the reister outputs. The precomputation architectures make no assumptions reardin eedback. For instance, R 1 and R 2 in Fiure 2 can be the same reister. Precomputation increases circuit area and can adversely impact circuit perormance. In order to keep area and delay increases small, it is best to synthesize precomputation loic which depends on a small set o inputs. Precomputation works best when there are a small number o complex unctions correspondin to the loic block A o Fiures 2 and 3. I the loic block has a lare number o outputs, then it may beworthwhile to selectively apply precomputation-based power optimization to a small number o complex outputs. This selective partitionin will entail a duplication o combinational loic and reisters, and the savins in power is oset by this duplication. Other precomputation architectures are bein explored, includin the architectures o Section 5, and those that rely on a history o previous input vectors. More work is required in the automation o a loic desin methodoloy that exploits multiplexor-based, combinational and multiple-cycle precomputation. 8 Acknowledements Thanks to Anantha Chandrakasan or providin us with inormation reardin power dissipation in reisters. J. Monteiro and S. Devadas were supported in part by the Deense Advanced Research Projects Aency under contract N J-1698 and in part by a NSF Youn Investiator Award with matchin unds rom Mitsubishi Corporation. Reerences [1] M. Alidina. Precomputation-Based Sequential Loic Optimization or Low Power. Master's thesis, Massachusetts Institute o Technoloy, May [3] R. Brayton, R. Rudell, A. Saniovanni-Vincentelli, and A. Wan. MIS: A Multiple-Level Loic Optimization System. In IEEE Transactions on Computer-Aided Desin, volume CAD-6, paes 1062{1081, November [4] R. Bryant. Graph-Based Alorithms or Boolean Function Manipulation. IEEE Transactions on Computers, C-35(8):677{691, Auust [5] A. Chandrakasan, T. Shen, and R. W. Brodersen. Low Power CMOS Diital Desin. In Journal o Solid State Circuits, paes 473{484, April [6] S. Devadas, A. Ghosh, and K. Keutzer. Loic Synthesis. McGraw Hill, New York, NY, [7] A. Ghosh, S. Devadas, K. Keutzer, and J. White. Estimation o Averae Switchin Activity in Combinational and Sequential Circuits. In Proceedins o the 29 th Desin Automation Conerence, paes 253{259, June [8] J. Monteiro, S. Devadas, and A. Ghosh. Retimin Sequential Circuits or Low Power. In Proceedins o the Int'l Conerence on Computer-Aided Desin, paes 398{402, November [9] J. Monteiro, S. Devadas, and B. Lin. A Methodoloy or Ecient Estimation o Switchin Activity in Sequential Loic Circuits. In Proceedins o the 31 st Desin Automation Conerence, paes 12{17, June [10] F. Najm. Transition Density, A Stochastic Measure o Activity in Diital Circuits. In Proceedins o the 28 th Desin Automation Conerence, paes 644{ 649, June [11] K. Roy and S. Prasad. SYCLOP: Synthesis o CMOS Loic or Low Power Applications. In Proceedins o the Int'l Conerence on Computer Desin: VLSI in Computers and Processors, paes 464{467, October [12] A. Shen, S. Devadas, A. Ghosh, and K. Keutzer. On Averae Power Dissipation and Random Pattern Testability o Combinational Loic Circuits. In Proceedins o the Int'l Conerence on Computer-Aided Desin, paes 402{407, November [13] C-Y. Tsui, M. Pedram, and A. Despain. Exact and Approximate Methods or Switchin Activity Estimation in Sequential Loic Circuits. In Proceedins o the 31 st Desin Automation Conerence, paes 18{23, June [2] P. Ashar, S. Devadas, and K. Keutzer. Path-Delay- Fault Testability Properties o Multiplexor-Based Networks. INTEGRATION, the VLSI Journal, 15(1):1{23, July 1993.

8 Circuit Oriinal Precompute Loic Optimized Lits Levels Power I Lits Levels Power % Reduction comp add comp / / / / max csa add max / / / / Table 1: Power Reductions or Datapath Circuits Circuit Oriinal Precompute Loic Optimized I O Lits Levels Power I Lits Levels Power % Reduction apex cht cm cm cmb comp cordic cps dalu duke e i majority misex misex mu pcle pcler sao seq spla term too lare unre Table 2: Power Reductions or Random Loic Circuits