Synthesis of Reversible Circuits Using Decision Diagrams
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1 Synthesis o Reversible Circuits Usin Decision Diarams Rol Drechsler Robert Wille Institute o Computer Science, University o Bremen, Bremen, Germany Cyber-Physical Systems, DFKI GmbH, Bremen, Germany {drechsle,rwille}@inormatik.uni-bremen.de Abstract Due to its promisin applications in domains like quantum computation or low-power desin, synthesis o reversible circuits has become an intensely studied topic. However, many synthesis methods are limited by non-scalable unction representations like truth tables. As an alternative, synthesis exploitin raph-based representations have been suested. The underlyin structure is a decision diaram (DD) that may vary reardin reduction methods, decomposition rules, or orderin restrictions. In this work, we review the proress o DD-based synthesis. It is shown that dedicated transormation rules can be applied to enerate circuits or unctions with a lare number o inputs. We discuss the eect o dierent decomposition types or typical DD improvements like complement edes and re-orderin. Furthermore, we describe how DD-based synthesis can be exploited to transer theoretical results known rom decision diarams into the domain o reversible circuits. Finally, urther directions or uture work are outlined. I. INTRODUCTION Reversible circuits realize n-input n-output unctions that map each possible input vector to a unique output vector (i.e. bijections). Althouh reversible loic siniicantly diers rom conventional (irreversible) loic (e.. an-out and eedback are not directly allowed), it has become an intensely studied research area in recent years. In particular, this is caused by the act that reversible loic is the basis or several emerin technoloies. Examples include applications in the domain o Low Power Computation, where the act that no inormation is lost in reversible computation can be exploited (see e.. [], [2], [3]), Adiabatic Circuits, a special low power technoloy to where reversible circuits are particularly suited or (see e.. [4]), Encodin and Decodin Devices, which always realize one-to-one mappins and, thus, inherently ollow a reversible computin paradim (see e.. [5]), Quantum Computation, which enables to solve many relevant problems siniicantly aster than conventional circuits and inherently is reversible (see e.. [6]), and Proram Inversion (see e.. [7]), as prorams based on a reversible computation paradim would allow an inherent and obvious proram inversion. Further applications o reversible loic can be ound in the domain o optical computin [8], DNA computin [2], and nano-technoloies [9]. However, or a lon time, synthesis o reversible circuits was limited. Exact (see e.. [], []) as well as heuristic (see e.. [2], [3], [4], [5], [6], [7]) methods have been proposed (see e.. [8] or a more detailed overview). But both are applicable only or relatively small unctions. Exact approaches reach their limits with unctions containin more than 6 variables [] while many heuristic methods are able to synthesize unctions with at most 3 variables [6]. Moreover, oten a siniicant amount o run-time is needed to achieve these results. These limitations are caused by the underlyin techniques. The existin synthesis approaches oten rely on truth tables (or similar descriptions like permutations) o the unction to be synthesized (e.. in [2], [3]). But even i more compact data-structures like DDs [5], positive-polarity Reed-Muller expansion [6], or Reed-Muller spectra [7] are used, the same limitations can be observed since all these approaches apply similar strateies (namely selectin reversible ates so that the choosen unction representation becomes the identity). In order to address this problem, an alternative based on decision diarams (DD) has been introduced in [9]. DDbased synthesis can cope with siniicantly larer unctions. The basic idea is thereby as ollows: First, or the unction to be synthesized a decision diaram [2] is built. This can eiciently be done or lare unctions usin existin welldeveloped techniques. Then, each node o the decision diaram is substituted by a cascade o reversible ates. Finally, all cascades are combined ormin the desired circuit. By this, a much more eicient data-structure has been exploited allowin or synthesis o reversible circuits or siniicantly larer unctions. Besides that, the concept o DD-based synthesis can be exploited to transer theoretical results known or decision diarams into the domain o reversible circuits. In this work, we review the eneral ideas and the proress on DD-based synthesis that has been made in the last years. We particularly describe the initial idea and discuss how dierent decomposition types as well as typical DD improvements like complement edes or re-orderin aect the size o the resultin circuits. Furthermore, how to transer theoretical results rom DDs to reversible circuits is described. Besides that, directions or uture work are outlined. II. BACKGROUND A. Reversible Circuits Reversible circuits are diital circuits with the same number o input sinals and output sinals. Furthermore, reversible circuits realize bijections only, i.e. each input assinment maps to a unique output assinment. Accordinly, computations can be perormed in both directions (rom the inputs to the outputs and vice versa). Reversible circuits are composed as cascades o reversible ates. Each reversible ate over the inputs X = {x,..., x n } consists o a (possibly empty) set C = {,..., k } X o control lines and a set T X \ C o taret lines. The most commonly used reversible ate is the Tooli ate T OF (C, x t ) [2], which consists o a sinle taret line x t X \ C whose value is inverted i all values on the control lines are set to or i C =, respectively. All remainin values are passed throuh the ate unaltered. Example : Fi. (a) shows a Tooli ate drawn in standard notation, i.e. control lines are denoted by, while the taret line is denoted by. A circuit composed o several Tooli ates is depicted in Fi. (b). This circuit maps e.. the input to the output and vice versa.
2 x x x 3 x 3 x (a) Tooli ate x = x = = x 2 = x 3 = x 3 = (b) Tooli circuit Fi.. Tooli ate and Tooli circuit To measure the cost o a reversible circuit, dierent metrics are applied (sometimes dependin on the addressed technoloy). In eneral, the number o circuit lines is an important criterion. In particular in the domain o quantum computation, the number o lines is equal to the number o qubits a restricted resource. Beyond that, the costs o the respective ates themselves are important, too. Since simply countin the number o ates does not adequately relect the eort to realize them, so called quantum costs are applied. They measure how many elementary quantum operations are needed in order to realize a reversible ate [6]. In the past, dierent methods have been introduced that convert a reversible ate into its equivalent quantum operations (see e.. [22], [23], [24]). Accordinly, dierent metrics or quantum costs are applied. B. Binary Decision Diarams A Boolean unction : B n B can be represented by a Decision Diaram (DD) [2]. A DD is a directed acyclic raph G = (V, E) where e.. a Shannon decomposition = xi= + xi= ( i n) is carried out in each node v V. The unctions xi= and xi= are the coactors o. In the ollowin, the node representin xi= ( xi=) is denoted by low(v) (hih(v)) while is called the select variable. A DD is called ree i each variable is encountered at most once on each path rom the root to a terminal node. A DD is called ordered i in addition all variables are encountered in the same order on all such paths. The size k o a DD is deined by the number o nodes. In the past, several techniques to optimize the size o DDs have been developed. In particular shared nodes [2], i.e. nodes v which have more than one predecessor, allow siniicant reductions. In particular, unctions : B n B m (i.e. unctions with more than one output) can be represented more compactly usin shared nodes. Further reductions can be achieved i complement edes [25] are applied. This enables the representation o a unction as well as o its neation by a sinle node only. Furthermore, the size o a DD siniicantly depends on the chosen orderin o its input variables [2]. Example 2: Fi. 2(a) shows a DD representin the unction = x x 3 x 4 + x x 3 x 4 + x x 3 x 4 + x x 3 x 4 as well as the respective co-actors resultin rom the application o the Shannon decomposition. III. DD-BASED SYNTHESIS In this section, we briely review DD-based synthesis o reversible circuits as introduced in [9] or Binary Decision Diarams [2]. This provides the basis or the remainin paper, where the application o optimization techniques or decision diarams to the synthesis approach is discussed. x 6 = x 3x 4 + x 3x 4 5 = x 3x 4 + x 3x 4 x x 3 x 4, 4 = x 3x 4 x 3 x 3 2 = x 3x 4 3 = x 4 x 4 x 4 = x 4 (a) BDD needs to preserve 2 (b) Resultin circuit Fi. 2. Example or BDD-based synthesis The aim o each synthesis approach is to determine a circuit realization or a iven Boolean unction. It is well known, that Boolean unctions can eiciently be represented by DDs [2]. Havin a DD G = (V, E), a reversible circuit can be derived by traversin the DD and substitutin each node v V with a cascade o reversible ates. The respective cascade o ates depends on the successors o the node v. Table I provides the cascades o Tooli ates or all possible scenarios o a DD node. Note that this sometimes requires an additional (constant) line. Based on these substitutions, a method or synthesizin a Boolean unction as a reversible circuit can be ormulated: First, a DD or unction to be synthesized is created. This can eiciently be done usin state-o-the-art DD packaes (e.. CUDD [26]). Next, the resultin DD G = (V, E) is traversed by a depth-irst search. For each node v V, cascades as depicted in Table I are added to the circuit. I the entire DD has been traversed, a circuit realizin has been obtained. Example 3: A circuit realizin the unction represented by the DD as shown in Fi. 2(a) is realized. First, the coactor can easily be represented by the primary input x 4. Havin the value o available, the co-actor 2 can be realized by the irst two ates depicted in Fi. 2(b). In this manner, respective sub-circuits can be added or all remainin co-actors until a circuit representin the overall unction results. The remainin steps are shown in Fi. 2(b). As a result, circuits are synthesized which realize the iven unction. Since, each node o the DD is only substituted by a cascade o ates, the proposed method has a linear worst case run-time and memory complexity with respect to the number o nodes in the DD. Note that an additional circuit line is added to preserve the values o x 4 and x 3 which are still needed by the co-actors 3 and 4, respectively.
3 TABLE I MAPPING SHANNON NODES TO REVERSIBLE CASCADES NODE CIRCUIT IV. IMPROVEMENTS For the irst time, DD-based synthesis allowed the automatic realization o lare reversible unctions, i.e. unctions with more than inputs. At the same time, optimization o decision diarams has heavily been considered by researchers in the past (usin e.. new decomposition types, complement edes, or reorderin strateies). This builds the basis or urther improvements o reversible circuit synthesis throuh decision diarams. In this section, some o the improvements, which have already been investiated, are briely discussed. Aterwards, urther research directions are outlined. A. Consideration o Alternative Decompositions Besides Shannon, urther decompositions o Boolean unctions exist. In particular, positive Davio and neative Davio decomposition deined by = xi= xi=2 = xi= xi=2 (pos. Davio) (ne. Davio) with xi=2 = xi= xi= have been established in the past 2. Considerin positive and neative Davio decomposition has several beneits or reversible circuit desin since or certain unctions they enable decomposin a iven unction into a smaller number o dierent sub-unctions, i.e. the size o the decision diaram is reduced, in many cases they enable more compact realizations as reversible circuits, and they enable the preservation o the values o some coactors without additional circuit lines so that the overall line count can be kept small. Consequently, smaller circuits may result i these alternative decompositions are applied. This has been investiated in detail in [28] or Kronecker Functional Decision Diarams [29]. To this end, urther substitutions or the respective decompositions have been developed. Table II lists the cases which additionally have to be considered. Example 4: Fi. 3(a) shows a decision diaram representin the unction = x x 3 x 4 + x x 3 x 4 + x x 3 x 4 + x x 3 x 4, where positive Davio decomposition is applied to each node. Traversin this decision diaram, irst the coactor is considered. This can be represented by the primary input x 4. Then, the co-actor 2 can be realized. Continuin this process until the depth irst-traversal is completed, a circuit as depicted in Fi. 3(b) results. As shown by the example, usin positive and neative Davio decomposition, a more compact reversible circuit can be realized or the considered unction. More precisely, in comparison to the resultin circuit rom Fi. 2 the number o lines is reduced by 2, the number o ates by 5, and the quantum cost by 7 or this simple example. B. Complement Edes Further reductions in DD sizes can be achieved i Complement Edes (CEs) [25] are applied. I a CE is applied, the output value o its connected node becomes inverted. This allows to represent a (sub-)unction as well as its neation by a sinle node only. The eect o CEs to the resultin circuit size has been investiated in [3]. Also here, proper substitutions have been determined which take the inversion by CEs into account. Based on this, it was shown that the consideration o CEs, in act, may lead to larer cascades in comparison to the substitution without CEs. However, the resultin reduction in the size o the decision diaram compensated this drawback in the majority o the cases. This demonstrates that exploitin optimization o decision diarams does not necessarily improve the resultin reversible circuits. C. Orderin o DDs Finally, the exploitation o dierent orderin strateies o decision diarams has been considered [3]. It is well known that the order o the variables has a hih impact on the size o the resultin DD [2]. Hence, several approaches 2 In act, it has been proven that Shannon, positive Davio, and neative Davio decomposition are suicient to eiciently decompose Boolean unctions [27].
4 TABLE II MAPPING DAVIO NODES TO REVERSIBLE CIRCUITS NODE CIRCUIT (POS. DAVIO) CIRCUIT (NEG. DAVIO) NODE CIRCUIT (POS. DAVIO) CIRCUIT (NEG. DAVIO) 4 = x 3x 4 x 3 x 4 Fi. 3. x x 3 x 4, x 3 = x 3x 4 x 3 x 3 2 = x 3 x 4 = x 4 x 4 (a) KFDD (b) Resultin circuit Example or synthesis exploitin Davio decomposition have been proposed to achieve ood orderins (e.. throuh sitin [3] or evolutionary alorithms [32]) or to determine exact results [33] in the past. As observed in [3], the selected orderin, in act, also has a stron eect on the size o the resultin circuits. Usually, an orderin which improves the DD size also improves the circuit size. However, also here examples have been ound showin that optimization or DDs not always leads to smaller circuits. D. Future Directions The improvements discussed above only represent the tip o the iceber o possible methods one can apply to improve DD-based synthesis. In act, DD-optimization is a very well investiated topic. Most o the presented methods have not yet been investiated or exploitation durin reversible circuit synthesis. Promisin directions to be considered include: Consideration o Entire Sub-trees: So ar, only sinle nodes o a decision diaram are solely mapped to reversible circuit cascades. However, it is very likely that much better results can be achieved i also requently occurrin sub-trees in the DD are substituted with correspondin cascades. Adjustin the Cost Function o the DD: So ar, all optimizations have been applied usin the number o nodes in the decision diaram as cost unction. However, it would be much more appropriate i instead the expected quantum costs or the expected number o lines (accordin to the mappins o Table I and Table II) would be applied. Then, e.. re-orderin would not try to minimize the number o nodes, but the actually desired result, i.e. the size o the resultin circuit. Extendin the Graph Structure: Due to the restrictions e.. with respect to orderin and decomposition, many Boolean unctions cannot eiciently be represented. Consequently, extended raph structures have been proposed in the past. Examples include e.. Read-k-times DDs, i.e. a eneralization o DDs in which variables may occur up to k times on each path [34], or Mod2OBDDs [35], where certain XOR nodes are exploited. Both techniques allow or a smaller representation o unctions which also can be exploited durin reversible circuit synthesis. Reducin the Number o Resultin Circuit Lines: DDbased synthesis particularly suers rom a lare number o additional lines in the resultin circuits (as observed in detail in [36]). An initial approach to reduce this number has been presented in [37]. However, more detailed investiations are still let or uture work. Consideration o Alternative DDs: Alternative DDs, e.. Quantum Multiple Valued Decision Diarams (QMDDs) [38], provide a more speciic data-structure or reversible unctions. Hence, developin synthesis based on these DDs seems plausible. First promisin results ollowin this direction have been presented in [39] where QMDDs have been exploited to realize lare unctions with the minimal number o circuit lines.
5 In order to realize these ideas, the implementation o the existin DD-based synthesis approaches available throuh RevKit [4] can be exploited. V. THEORETICAL CONSIDERATION Besides practical issues, also the theoretical backround o decision diarams has intensely been studied in the past (see e.. [4], [42], [43]). Since the results o DD-based synthesis as applied so ar are asymptotically bounded by the number o nodes in the decision diaram, these theoretical results can easily be transerred to the domain o reversible circuits. More precisely, i a unction with n primary inputs and represented by a DD o size k invokin Shannon decomposition only is synthesized, the resultin circuits are composed o at most k + n circuit lines (since besides the input lines, or each node at most one additional line is added) and 3 k ates (since or each node cascades o at most 3 ates are added accordin to the substitutions o Table I). Althouh this already allows some interestin conclusions (e.. each unction can be realized as reversible circuits with at most 3 2 n ates, symmetric unctions can always be realized with a quadratic number o ates, etc.), the underlyin upper bound is quite weak. It is very likely that many urther results (e.. tihter upper bounds or eneral unctions as well as or respective unction classes) can be derived. Hence, a detailed analysis o the theoretical results that can be obtained by the DD-based synthesis is a promisin research direction. VI. CONCLUSIONS In this work, we reviewed the eneral idea and the proress on DD-based synthesis that has been made in the last years. Besides that, we outlined urther directions that can be addressed in uture work. To this end, the implementation o the existin DD-based synthesis approaches available throuh RevKit [4] may provide a ood startin point. REFERENCES [] R. Landauer, Irreversibility and heat eneration in the computin process, IBM Journal o Research and Development, vol. 5, no. 3, pp. 83 9, 96. [2] C. H. Bennett, Loical reversibility o computation, IBM Journal o Research and Development, vol. 7, pp , 973. [3] B. Desoete and A. De Vos, A reversible carry-look-ahead adder usin control ates, Interation, vol. 33, no. 2, pp. 89 4, 22. [4] P. Patra and D. Fussell, On eicient adiabatic desin o MOS circuits, in Workshop on Physics and Computation, Boston, 996, pp [5] R. Wille, R. Drechsler, C. Oswald, and A. Garcia-Ortiz, Automatic desin o low-power encoders usin reversible circuit synthesis, in Desin, Automation and Test in Europe, 22, pp [6] M. Nielsen and I. L. Chuan, Quantum Computation and Quantum Inormation. Cambride University Press, 2. [7] R. Glück and M. Kawabe, A method or automatic proram inversion based on LR() parsin, Fundamenta Inormaticae, vol. 66, no. 4, pp , 25. [8] R. Cuykendall and D. R. Andersen, Reversible optical computin circuits, Optics Letters, vol. 2, no. 7, pp , 987. [9] R. C. Merkle, Reversible electronic loic usin switches, Nanotechnoloy, vol. 4, no., pp. 2 4, 993. [] W. Hun, X. Son, G. Yan, J. Yan, and M. Perkowski, Optimal synthesis o multiple output Boolean unctions usin a set o quantum ates by symbolic reachability analysis. IEEE Trans. on CAD, vol. 25, no. 9, pp , 26. [] D. Große, R. Wille, G. W. Dueck, and R. Drechsler, Exact multiple control Tooli network synthesis with SAT techniques, IEEE Trans. on CAD, vol. 28, no. 5, pp , 29. [2] V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, Synthesis o reversible loic circuits, IEEE Trans. on CAD, vol. 22, no. 6, pp , 23. [3] D. M. Miller, D. Maslov, and G. W. Dueck, A transormation based alorithm or reversible loic synthesis, in Desin Automation Conerence, 23, pp [4] D. Maslov, G. W. Dueck, and D. M. Miller, Tooli network synthesis with templates, IEEE Trans. on CAD, vol. 24, no. 6, pp , 25. [5] P. Kerntop, A new heuristic alorithm or reversible loic synthesis, in Desin Automation Conerence, 24, pp [6] P. Gupta, A. Arawal, and N. K. Jha, An alorithm or synthesis o reversible loic circuits, IEEE Trans. on CAD, vol. 25, no., pp , 26. [7] D. Maslov, G. W. Dueck, and D. M. Miller, Techniques or the synthesis o reversible Tooli networks, ACM Trans. Desin Automation Electronic Systems, vol. 2, no. 4, 27. [8] R. Drechsler and R. Wille, From truth tables to prorammin lanuaes: Proress in the desin o reversible circuits, in Int l Symp. on Multiple-Valued Loic, 2, pp [9] R. Wille and R. Drechsler, BDD-based synthesis o reversible loic or lare unctions, in Desin Automation Conerence, 29, pp [2] R. E. Bryant, Graph-based alorithms or Boolean unction manipulation, IEEE Trans. on Comp., vol. 35, no. 8, pp , 986. [2] T. Tooli, Reversible Computin, in Automata, Lanuaes and Prorammin, W. de Bakker and J. van Leeuwen, Eds. Spriner, 98, p [22] A. Barenco, C. H. Bennett, R. Cleve, D. P. DiVincenzo, N. Marolus, P. Shor, T. Sleator, J. A. Smolin, and H. Weinurter, Elementary ates or quantum computation, Physical Review A, vol. 52, no. 5, pp , 995. [23] D. M. Miller, R. Wille, and Z. Sasanian, Elementary quantum ate realizations or multiple-control Toolli ates, in Int l Symp. on Multiple- Valued Loic, 2, pp [24] Z. Sasanian, R. Wille, and D. M. Miller, Realizin reversible circuits usin a new class o quantum ates, in Desin Automation Conerence, 22, pp [25] K. S. Brace, R. L. Rudell, and R. E. Bryant, Eicient implementation o a BDD packae, in Desin Automation Conerence, 99, pp [26] F. Somenzi, CUDD: CU Decision Diaram Packae Release University o Colorado at Boulder, 2. [27] B. Becker and R. Drechsler, How many decomposition types do we need? in European Desin & Test Con., 995, pp [28] M. Soeken, R. Wille, and R. Drechsler, Hierarchical synthesis o reversible circuits usin positive and neative davio decomposition, in Int l Desin and Test Workshop, 2, pp [29] R. Drechsler, A. Sarabi, M. Theobald, B. Becker, and M. Perkowski, Eicient representation and manipulation o switchin unctions based on ordered Kronecker unctional decision diarams, in Desin Automation Conerence, 994, pp [3] R. Wille and R. Drechsler, Eect o BDD optimization on synthesis o reversible and quantum loic, Electr. Notes Theor. Comput. Sci., vol. 253, no. 6, pp. 57 7, 2. [3] R. Rudell, Dynamic variable orderin or ordered binary decision diarams, in Int l Con. on Computer-Aided Desin, 993, pp [32] N. Göckel, R. Drechsler, and B. Becker, Learnin heuristics or OKFDD minimization by evolutionary alorithms, in Asia and South Paciic Desin Automation Conerence, 997, pp [33] R. Drechsler, N. Drechsler, and W. Günther, Fast exact minimization o BDDs, IEEE Trans. on CAD, vol. 9, no. 3, pp , 2. [34] W. Günther and R. Drechsler, Implementation o read-k-times BDDs on top o standard BDD packaes, in VLSI Desin Con., 2, pp [35] C. Meinel and H. Sack, Mod2OBDDs - a BDD structure or probabilistic veriication, Electronic Notes in Theoretical Computer Science, vol. 22, 2. [36] R. Wille, O. Keszöcze, and R. Drechsler, Determinin the minimal number o lines or lare reversible circuits, in Desin, Automation and Test in Europe, 2, pp [37] R. Wille, M. Soeken, and R. Drechsler, Reducin the number o lines in reversible circuits, in Desin Automation Conerence, 2, pp [38] D. M. Miller and M. A. Thornton, QMDD: A decision diaram structure or reversible and quantum circuits, in Int l Symp. on Multiple- Valued Loic, 26, p. 3. [39] M. Soeken, R. Wille, C. Hilken, N. Przioda, and R. Drechsler, Synthesis o reversible circuits with minimal lines or lare unctions, in Asia and South Paciic Desin Automation Conerence, 22, pp [4] M. Soeken, S. Frehse, R. Wille, and R. Drechsler, RevKit: An Open Source Toolkit or the Desin o Reversible Circuits, in Reversible Computation 2, ser. Lecture Notes in Computer Science, vol. 765, 22, pp , RevKit is available at [4] H. Liaw and C. Lin, On the OBDD-representation o eneral Boolean unctions, in IEEE Trans. on Comp., vol. 4, 992, pp [42] I. Weener, Branchin prorams and binary decision diarams: theory and applications. Society or Industrial and Applied Mathematics, 2. [43] R. Drechsler and D. Sielin, Binary decision diarams in theory and practice, Sotware Tools or Technoloy Transer, vol. 3, pp. 2 36, 2.
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