Synthesis of Reversible Circuits Using Decision Diagrams

Size: px
Start display at page:

Download "Synthesis of Reversible Circuits Using Decision Diagrams"

Transcription

1 Synthesis o Reversible Circuits Usin Decision Diarams Rol Drechsler Robert Wille Institute o Computer Science, University o Bremen, Bremen, Germany Cyber-Physical Systems, DFKI GmbH, Bremen, Germany {drechsle,rwille}@inormatik.uni-bremen.de Abstract Due to its promisin applications in domains like quantum computation or low-power desin, synthesis o reversible circuits has become an intensely studied topic. However, many synthesis methods are limited by non-scalable unction representations like truth tables. As an alternative, synthesis exploitin raph-based representations have been suested. The underlyin structure is a decision diaram (DD) that may vary reardin reduction methods, decomposition rules, or orderin restrictions. In this work, we review the proress o DD-based synthesis. It is shown that dedicated transormation rules can be applied to enerate circuits or unctions with a lare number o inputs. We discuss the eect o dierent decomposition types or typical DD improvements like complement edes and re-orderin. Furthermore, we describe how DD-based synthesis can be exploited to transer theoretical results known rom decision diarams into the domain o reversible circuits. Finally, urther directions or uture work are outlined. I. INTRODUCTION Reversible circuits realize n-input n-output unctions that map each possible input vector to a unique output vector (i.e. bijections). Althouh reversible loic siniicantly diers rom conventional (irreversible) loic (e.. an-out and eedback are not directly allowed), it has become an intensely studied research area in recent years. In particular, this is caused by the act that reversible loic is the basis or several emerin technoloies. Examples include applications in the domain o Low Power Computation, where the act that no inormation is lost in reversible computation can be exploited (see e.. [], [2], [3]), Adiabatic Circuits, a special low power technoloy to where reversible circuits are particularly suited or (see e.. [4]), Encodin and Decodin Devices, which always realize one-to-one mappins and, thus, inherently ollow a reversible computin paradim (see e.. [5]), Quantum Computation, which enables to solve many relevant problems siniicantly aster than conventional circuits and inherently is reversible (see e.. [6]), and Proram Inversion (see e.. [7]), as prorams based on a reversible computation paradim would allow an inherent and obvious proram inversion. Further applications o reversible loic can be ound in the domain o optical computin [8], DNA computin [2], and nano-technoloies [9]. However, or a lon time, synthesis o reversible circuits was limited. Exact (see e.. [], []) as well as heuristic (see e.. [2], [3], [4], [5], [6], [7]) methods have been proposed (see e.. [8] or a more detailed overview). But both are applicable only or relatively small unctions. Exact approaches reach their limits with unctions containin more than 6 variables [] while many heuristic methods are able to synthesize unctions with at most 3 variables [6]. Moreover, oten a siniicant amount o run-time is needed to achieve these results. These limitations are caused by the underlyin techniques. The existin synthesis approaches oten rely on truth tables (or similar descriptions like permutations) o the unction to be synthesized (e.. in [2], [3]). But even i more compact data-structures like DDs [5], positive-polarity Reed-Muller expansion [6], or Reed-Muller spectra [7] are used, the same limitations can be observed since all these approaches apply similar strateies (namely selectin reversible ates so that the choosen unction representation becomes the identity). In order to address this problem, an alternative based on decision diarams (DD) has been introduced in [9]. DDbased synthesis can cope with siniicantly larer unctions. The basic idea is thereby as ollows: First, or the unction to be synthesized a decision diaram [2] is built. This can eiciently be done or lare unctions usin existin welldeveloped techniques. Then, each node o the decision diaram is substituted by a cascade o reversible ates. Finally, all cascades are combined ormin the desired circuit. By this, a much more eicient data-structure has been exploited allowin or synthesis o reversible circuits or siniicantly larer unctions. Besides that, the concept o DD-based synthesis can be exploited to transer theoretical results known or decision diarams into the domain o reversible circuits. In this work, we review the eneral ideas and the proress on DD-based synthesis that has been made in the last years. We particularly describe the initial idea and discuss how dierent decomposition types as well as typical DD improvements like complement edes or re-orderin aect the size o the resultin circuits. Furthermore, how to transer theoretical results rom DDs to reversible circuits is described. Besides that, directions or uture work are outlined. II. BACKGROUND A. Reversible Circuits Reversible circuits are diital circuits with the same number o input sinals and output sinals. Furthermore, reversible circuits realize bijections only, i.e. each input assinment maps to a unique output assinment. Accordinly, computations can be perormed in both directions (rom the inputs to the outputs and vice versa). Reversible circuits are composed as cascades o reversible ates. Each reversible ate over the inputs X = {x,..., x n } consists o a (possibly empty) set C = {,..., k } X o control lines and a set T X \ C o taret lines. The most commonly used reversible ate is the Tooli ate T OF (C, x t ) [2], which consists o a sinle taret line x t X \ C whose value is inverted i all values on the control lines are set to or i C =, respectively. All remainin values are passed throuh the ate unaltered. Example : Fi. (a) shows a Tooli ate drawn in standard notation, i.e. control lines are denoted by, while the taret line is denoted by. A circuit composed o several Tooli ates is depicted in Fi. (b). This circuit maps e.. the input to the output and vice versa.

2 x x x 3 x 3 x (a) Tooli ate x = x = = x 2 = x 3 = x 3 = (b) Tooli circuit Fi.. Tooli ate and Tooli circuit To measure the cost o a reversible circuit, dierent metrics are applied (sometimes dependin on the addressed technoloy). In eneral, the number o circuit lines is an important criterion. In particular in the domain o quantum computation, the number o lines is equal to the number o qubits a restricted resource. Beyond that, the costs o the respective ates themselves are important, too. Since simply countin the number o ates does not adequately relect the eort to realize them, so called quantum costs are applied. They measure how many elementary quantum operations are needed in order to realize a reversible ate [6]. In the past, dierent methods have been introduced that convert a reversible ate into its equivalent quantum operations (see e.. [22], [23], [24]). Accordinly, dierent metrics or quantum costs are applied. B. Binary Decision Diarams A Boolean unction : B n B can be represented by a Decision Diaram (DD) [2]. A DD is a directed acyclic raph G = (V, E) where e.. a Shannon decomposition = xi= + xi= ( i n) is carried out in each node v V. The unctions xi= and xi= are the coactors o. In the ollowin, the node representin xi= ( xi=) is denoted by low(v) (hih(v)) while is called the select variable. A DD is called ree i each variable is encountered at most once on each path rom the root to a terminal node. A DD is called ordered i in addition all variables are encountered in the same order on all such paths. The size k o a DD is deined by the number o nodes. In the past, several techniques to optimize the size o DDs have been developed. In particular shared nodes [2], i.e. nodes v which have more than one predecessor, allow siniicant reductions. In particular, unctions : B n B m (i.e. unctions with more than one output) can be represented more compactly usin shared nodes. Further reductions can be achieved i complement edes [25] are applied. This enables the representation o a unction as well as o its neation by a sinle node only. Furthermore, the size o a DD siniicantly depends on the chosen orderin o its input variables [2]. Example 2: Fi. 2(a) shows a DD representin the unction = x x 3 x 4 + x x 3 x 4 + x x 3 x 4 + x x 3 x 4 as well as the respective co-actors resultin rom the application o the Shannon decomposition. III. DD-BASED SYNTHESIS In this section, we briely review DD-based synthesis o reversible circuits as introduced in [9] or Binary Decision Diarams [2]. This provides the basis or the remainin paper, where the application o optimization techniques or decision diarams to the synthesis approach is discussed. x 6 = x 3x 4 + x 3x 4 5 = x 3x 4 + x 3x 4 x x 3 x 4, 4 = x 3x 4 x 3 x 3 2 = x 3x 4 3 = x 4 x 4 x 4 = x 4 (a) BDD needs to preserve 2 (b) Resultin circuit Fi. 2. Example or BDD-based synthesis The aim o each synthesis approach is to determine a circuit realization or a iven Boolean unction. It is well known, that Boolean unctions can eiciently be represented by DDs [2]. Havin a DD G = (V, E), a reversible circuit can be derived by traversin the DD and substitutin each node v V with a cascade o reversible ates. The respective cascade o ates depends on the successors o the node v. Table I provides the cascades o Tooli ates or all possible scenarios o a DD node. Note that this sometimes requires an additional (constant) line. Based on these substitutions, a method or synthesizin a Boolean unction as a reversible circuit can be ormulated: First, a DD or unction to be synthesized is created. This can eiciently be done usin state-o-the-art DD packaes (e.. CUDD [26]). Next, the resultin DD G = (V, E) is traversed by a depth-irst search. For each node v V, cascades as depicted in Table I are added to the circuit. I the entire DD has been traversed, a circuit realizin has been obtained. Example 3: A circuit realizin the unction represented by the DD as shown in Fi. 2(a) is realized. First, the coactor can easily be represented by the primary input x 4. Havin the value o available, the co-actor 2 can be realized by the irst two ates depicted in Fi. 2(b). In this manner, respective sub-circuits can be added or all remainin co-actors until a circuit representin the overall unction results. The remainin steps are shown in Fi. 2(b). As a result, circuits are synthesized which realize the iven unction. Since, each node o the DD is only substituted by a cascade o ates, the proposed method has a linear worst case run-time and memory complexity with respect to the number o nodes in the DD. Note that an additional circuit line is added to preserve the values o x 4 and x 3 which are still needed by the co-actors 3 and 4, respectively.

3 TABLE I MAPPING SHANNON NODES TO REVERSIBLE CASCADES NODE CIRCUIT IV. IMPROVEMENTS For the irst time, DD-based synthesis allowed the automatic realization o lare reversible unctions, i.e. unctions with more than inputs. At the same time, optimization o decision diarams has heavily been considered by researchers in the past (usin e.. new decomposition types, complement edes, or reorderin strateies). This builds the basis or urther improvements o reversible circuit synthesis throuh decision diarams. In this section, some o the improvements, which have already been investiated, are briely discussed. Aterwards, urther research directions are outlined. A. Consideration o Alternative Decompositions Besides Shannon, urther decompositions o Boolean unctions exist. In particular, positive Davio and neative Davio decomposition deined by = xi= xi=2 = xi= xi=2 (pos. Davio) (ne. Davio) with xi=2 = xi= xi= have been established in the past 2. Considerin positive and neative Davio decomposition has several beneits or reversible circuit desin since or certain unctions they enable decomposin a iven unction into a smaller number o dierent sub-unctions, i.e. the size o the decision diaram is reduced, in many cases they enable more compact realizations as reversible circuits, and they enable the preservation o the values o some coactors without additional circuit lines so that the overall line count can be kept small. Consequently, smaller circuits may result i these alternative decompositions are applied. This has been investiated in detail in [28] or Kronecker Functional Decision Diarams [29]. To this end, urther substitutions or the respective decompositions have been developed. Table II lists the cases which additionally have to be considered. Example 4: Fi. 3(a) shows a decision diaram representin the unction = x x 3 x 4 + x x 3 x 4 + x x 3 x 4 + x x 3 x 4, where positive Davio decomposition is applied to each node. Traversin this decision diaram, irst the coactor is considered. This can be represented by the primary input x 4. Then, the co-actor 2 can be realized. Continuin this process until the depth irst-traversal is completed, a circuit as depicted in Fi. 3(b) results. As shown by the example, usin positive and neative Davio decomposition, a more compact reversible circuit can be realized or the considered unction. More precisely, in comparison to the resultin circuit rom Fi. 2 the number o lines is reduced by 2, the number o ates by 5, and the quantum cost by 7 or this simple example. B. Complement Edes Further reductions in DD sizes can be achieved i Complement Edes (CEs) [25] are applied. I a CE is applied, the output value o its connected node becomes inverted. This allows to represent a (sub-)unction as well as its neation by a sinle node only. The eect o CEs to the resultin circuit size has been investiated in [3]. Also here, proper substitutions have been determined which take the inversion by CEs into account. Based on this, it was shown that the consideration o CEs, in act, may lead to larer cascades in comparison to the substitution without CEs. However, the resultin reduction in the size o the decision diaram compensated this drawback in the majority o the cases. This demonstrates that exploitin optimization o decision diarams does not necessarily improve the resultin reversible circuits. C. Orderin o DDs Finally, the exploitation o dierent orderin strateies o decision diarams has been considered [3]. It is well known that the order o the variables has a hih impact on the size o the resultin DD [2]. Hence, several approaches 2 In act, it has been proven that Shannon, positive Davio, and neative Davio decomposition are suicient to eiciently decompose Boolean unctions [27].

4 TABLE II MAPPING DAVIO NODES TO REVERSIBLE CIRCUITS NODE CIRCUIT (POS. DAVIO) CIRCUIT (NEG. DAVIO) NODE CIRCUIT (POS. DAVIO) CIRCUIT (NEG. DAVIO) 4 = x 3x 4 x 3 x 4 Fi. 3. x x 3 x 4, x 3 = x 3x 4 x 3 x 3 2 = x 3 x 4 = x 4 x 4 (a) KFDD (b) Resultin circuit Example or synthesis exploitin Davio decomposition have been proposed to achieve ood orderins (e.. throuh sitin [3] or evolutionary alorithms [32]) or to determine exact results [33] in the past. As observed in [3], the selected orderin, in act, also has a stron eect on the size o the resultin circuits. Usually, an orderin which improves the DD size also improves the circuit size. However, also here examples have been ound showin that optimization or DDs not always leads to smaller circuits. D. Future Directions The improvements discussed above only represent the tip o the iceber o possible methods one can apply to improve DD-based synthesis. In act, DD-optimization is a very well investiated topic. Most o the presented methods have not yet been investiated or exploitation durin reversible circuit synthesis. Promisin directions to be considered include: Consideration o Entire Sub-trees: So ar, only sinle nodes o a decision diaram are solely mapped to reversible circuit cascades. However, it is very likely that much better results can be achieved i also requently occurrin sub-trees in the DD are substituted with correspondin cascades. Adjustin the Cost Function o the DD: So ar, all optimizations have been applied usin the number o nodes in the decision diaram as cost unction. However, it would be much more appropriate i instead the expected quantum costs or the expected number o lines (accordin to the mappins o Table I and Table II) would be applied. Then, e.. re-orderin would not try to minimize the number o nodes, but the actually desired result, i.e. the size o the resultin circuit. Extendin the Graph Structure: Due to the restrictions e.. with respect to orderin and decomposition, many Boolean unctions cannot eiciently be represented. Consequently, extended raph structures have been proposed in the past. Examples include e.. Read-k-times DDs, i.e. a eneralization o DDs in which variables may occur up to k times on each path [34], or Mod2OBDDs [35], where certain XOR nodes are exploited. Both techniques allow or a smaller representation o unctions which also can be exploited durin reversible circuit synthesis. Reducin the Number o Resultin Circuit Lines: DDbased synthesis particularly suers rom a lare number o additional lines in the resultin circuits (as observed in detail in [36]). An initial approach to reduce this number has been presented in [37]. However, more detailed investiations are still let or uture work. Consideration o Alternative DDs: Alternative DDs, e.. Quantum Multiple Valued Decision Diarams (QMDDs) [38], provide a more speciic data-structure or reversible unctions. Hence, developin synthesis based on these DDs seems plausible. First promisin results ollowin this direction have been presented in [39] where QMDDs have been exploited to realize lare unctions with the minimal number o circuit lines.

5 In order to realize these ideas, the implementation o the existin DD-based synthesis approaches available throuh RevKit [4] can be exploited. V. THEORETICAL CONSIDERATION Besides practical issues, also the theoretical backround o decision diarams has intensely been studied in the past (see e.. [4], [42], [43]). Since the results o DD-based synthesis as applied so ar are asymptotically bounded by the number o nodes in the decision diaram, these theoretical results can easily be transerred to the domain o reversible circuits. More precisely, i a unction with n primary inputs and represented by a DD o size k invokin Shannon decomposition only is synthesized, the resultin circuits are composed o at most k + n circuit lines (since besides the input lines, or each node at most one additional line is added) and 3 k ates (since or each node cascades o at most 3 ates are added accordin to the substitutions o Table I). Althouh this already allows some interestin conclusions (e.. each unction can be realized as reversible circuits with at most 3 2 n ates, symmetric unctions can always be realized with a quadratic number o ates, etc.), the underlyin upper bound is quite weak. It is very likely that many urther results (e.. tihter upper bounds or eneral unctions as well as or respective unction classes) can be derived. Hence, a detailed analysis o the theoretical results that can be obtained by the DD-based synthesis is a promisin research direction. VI. CONCLUSIONS In this work, we reviewed the eneral idea and the proress on DD-based synthesis that has been made in the last years. Besides that, we outlined urther directions that can be addressed in uture work. To this end, the implementation o the existin DD-based synthesis approaches available throuh RevKit [4] may provide a ood startin point. REFERENCES [] R. Landauer, Irreversibility and heat eneration in the computin process, IBM Journal o Research and Development, vol. 5, no. 3, pp. 83 9, 96. [2] C. H. Bennett, Loical reversibility o computation, IBM Journal o Research and Development, vol. 7, pp , 973. [3] B. Desoete and A. De Vos, A reversible carry-look-ahead adder usin control ates, Interation, vol. 33, no. 2, pp. 89 4, 22. [4] P. Patra and D. Fussell, On eicient adiabatic desin o MOS circuits, in Workshop on Physics and Computation, Boston, 996, pp [5] R. Wille, R. Drechsler, C. Oswald, and A. Garcia-Ortiz, Automatic desin o low-power encoders usin reversible circuit synthesis, in Desin, Automation and Test in Europe, 22, pp [6] M. Nielsen and I. L. Chuan, Quantum Computation and Quantum Inormation. Cambride University Press, 2. [7] R. Glück and M. Kawabe, A method or automatic proram inversion based on LR() parsin, Fundamenta Inormaticae, vol. 66, no. 4, pp , 25. [8] R. Cuykendall and D. R. Andersen, Reversible optical computin circuits, Optics Letters, vol. 2, no. 7, pp , 987. [9] R. C. Merkle, Reversible electronic loic usin switches, Nanotechnoloy, vol. 4, no., pp. 2 4, 993. [] W. Hun, X. Son, G. Yan, J. Yan, and M. Perkowski, Optimal synthesis o multiple output Boolean unctions usin a set o quantum ates by symbolic reachability analysis. IEEE Trans. on CAD, vol. 25, no. 9, pp , 26. [] D. Große, R. Wille, G. W. Dueck, and R. Drechsler, Exact multiple control Tooli network synthesis with SAT techniques, IEEE Trans. on CAD, vol. 28, no. 5, pp , 29. [2] V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, Synthesis o reversible loic circuits, IEEE Trans. on CAD, vol. 22, no. 6, pp , 23. [3] D. M. Miller, D. Maslov, and G. W. Dueck, A transormation based alorithm or reversible loic synthesis, in Desin Automation Conerence, 23, pp [4] D. Maslov, G. W. Dueck, and D. M. Miller, Tooli network synthesis with templates, IEEE Trans. on CAD, vol. 24, no. 6, pp , 25. [5] P. Kerntop, A new heuristic alorithm or reversible loic synthesis, in Desin Automation Conerence, 24, pp [6] P. Gupta, A. Arawal, and N. K. Jha, An alorithm or synthesis o reversible loic circuits, IEEE Trans. on CAD, vol. 25, no., pp , 26. [7] D. Maslov, G. W. Dueck, and D. M. Miller, Techniques or the synthesis o reversible Tooli networks, ACM Trans. Desin Automation Electronic Systems, vol. 2, no. 4, 27. [8] R. Drechsler and R. Wille, From truth tables to prorammin lanuaes: Proress in the desin o reversible circuits, in Int l Symp. on Multiple-Valued Loic, 2, pp [9] R. Wille and R. Drechsler, BDD-based synthesis o reversible loic or lare unctions, in Desin Automation Conerence, 29, pp [2] R. E. Bryant, Graph-based alorithms or Boolean unction manipulation, IEEE Trans. on Comp., vol. 35, no. 8, pp , 986. [2] T. Tooli, Reversible Computin, in Automata, Lanuaes and Prorammin, W. de Bakker and J. van Leeuwen, Eds. Spriner, 98, p [22] A. Barenco, C. H. Bennett, R. Cleve, D. P. DiVincenzo, N. Marolus, P. Shor, T. Sleator, J. A. Smolin, and H. Weinurter, Elementary ates or quantum computation, Physical Review A, vol. 52, no. 5, pp , 995. [23] D. M. Miller, R. Wille, and Z. Sasanian, Elementary quantum ate realizations or multiple-control Toolli ates, in Int l Symp. on Multiple- Valued Loic, 2, pp [24] Z. Sasanian, R. Wille, and D. M. Miller, Realizin reversible circuits usin a new class o quantum ates, in Desin Automation Conerence, 22, pp [25] K. S. Brace, R. L. Rudell, and R. E. Bryant, Eicient implementation o a BDD packae, in Desin Automation Conerence, 99, pp [26] F. Somenzi, CUDD: CU Decision Diaram Packae Release University o Colorado at Boulder, 2. [27] B. Becker and R. Drechsler, How many decomposition types do we need? in European Desin & Test Con., 995, pp [28] M. Soeken, R. Wille, and R. Drechsler, Hierarchical synthesis o reversible circuits usin positive and neative davio decomposition, in Int l Desin and Test Workshop, 2, pp [29] R. Drechsler, A. Sarabi, M. Theobald, B. Becker, and M. Perkowski, Eicient representation and manipulation o switchin unctions based on ordered Kronecker unctional decision diarams, in Desin Automation Conerence, 994, pp [3] R. Wille and R. Drechsler, Eect o BDD optimization on synthesis o reversible and quantum loic, Electr. Notes Theor. Comput. Sci., vol. 253, no. 6, pp. 57 7, 2. [3] R. Rudell, Dynamic variable orderin or ordered binary decision diarams, in Int l Con. on Computer-Aided Desin, 993, pp [32] N. Göckel, R. Drechsler, and B. Becker, Learnin heuristics or OKFDD minimization by evolutionary alorithms, in Asia and South Paciic Desin Automation Conerence, 997, pp [33] R. Drechsler, N. Drechsler, and W. Günther, Fast exact minimization o BDDs, IEEE Trans. on CAD, vol. 9, no. 3, pp , 2. [34] W. Günther and R. Drechsler, Implementation o read-k-times BDDs on top o standard BDD packaes, in VLSI Desin Con., 2, pp [35] C. Meinel and H. Sack, Mod2OBDDs - a BDD structure or probabilistic veriication, Electronic Notes in Theoretical Computer Science, vol. 22, 2. [36] R. Wille, O. Keszöcze, and R. Drechsler, Determinin the minimal number o lines or lare reversible circuits, in Desin, Automation and Test in Europe, 2, pp [37] R. Wille, M. Soeken, and R. Drechsler, Reducin the number o lines in reversible circuits, in Desin Automation Conerence, 2, pp [38] D. M. Miller and M. A. Thornton, QMDD: A decision diaram structure or reversible and quantum circuits, in Int l Symp. on Multiple- Valued Loic, 26, p. 3. [39] M. Soeken, R. Wille, C. Hilken, N. Przioda, and R. Drechsler, Synthesis o reversible circuits with minimal lines or lare unctions, in Asia and South Paciic Desin Automation Conerence, 22, pp [4] M. Soeken, S. Frehse, R. Wille, and R. Drechsler, RevKit: An Open Source Toolkit or the Desin o Reversible Circuits, in Reversible Computation 2, ser. Lecture Notes in Computer Science, vol. 765, 22, pp , RevKit is available at [4] H. Liaw and C. Lin, On the OBDD-representation o eneral Boolean unctions, in IEEE Trans. on Comp., vol. 4, 992, pp [42] I. Weener, Branchin prorams and binary decision diarams: theory and applications. Society or Industrial and Applied Mathematics, 2. [43] R. Drechsler and D. Sielin, Binary decision diarams in theory and practice, Sotware Tools or Technoloy Transer, vol. 3, pp. 2 36, 2.

Exploiting Reversibility in the Complete Simulation of Reversible Circuits

Exploiting Reversibility in the Complete Simulation of Reversible Circuits Exploiting Reversibility in the Complete Simulation of Reversible Circuits Robert Wille Simon Stelter Rolf Drechsler Institute of Computer Science, University of Bremen, 28359 Bremen, Germany Cyber-Physical

More information

Quantified Synthesis of Reversible Logic

Quantified Synthesis of Reversible Logic Quantified Synthesis of Reversible Logic Robert Wille 1 Hoang M. Le 1 Gerhard W. Dueck 2 Daniel Große 1 1 Group for Computer Architecture (Prof. Dr. Rolf Drechsler) University of Bremen, 28359 Bremen,

More information

Reversible Logic Synthesis with Output Permutation

Reversible Logic Synthesis with Output Permutation Please note: Methods introduced in this paper are availabe at www.revkit.org. Reversible Logic Synthesis with Output Permutation Robert Wille 1 Daniel Große 1 Gerhard W. Dueck 2 Rolf Drechsler 1 1 Institute

More information

GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits

GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits GF(4) ased Synthesis o Quaternary Reversible/Quantum Logic Circuits MOZAMMEL H. A. KHAN AND MAREK A. PERKOWSKI Department o Computer Science and Engineering, East West University 4 Mohakhali, Dhaka, ANGLADESH,

More information

Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit

Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit 11 41st IEEE International Symposium on Multiple-Valued Logic Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit Md. Mazder Rahman, Anindita Banerjee, Gerhard W. Dueck, and Anirban

More information

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure Arighna Deb 1, Debesh K. Das 1, Hafizur Rahaman 2, Bhargab B. Bhattacharya 3, Robert Wille 4, Rolf Drechsler 4 1 Computer

More information

Checking Reversibility of Boolean Functions

Checking Reversibility of Boolean Functions Checking Reversibility of Boolean Functions Robert Wille 1,2, Aaron Lye 3, and Philipp Niemann 3 1 Institute for Integrated Circuits, Johannes Kepler University, A-4040 Linz, Austria 2 Cyber-Physical Systems,

More information

Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis

Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis Robert Wille 1 Rolf Drechsler 1,2 Christof Osewold 3 Alberto Garcia-Ortiz 3,4 1 Institute of Computer Science, University of Bremen,

More information

Synthesizing Reversible Circuits for Irreversible Functions

Synthesizing Reversible Circuits for Irreversible Functions Synthesizing Reversible Circuits for Irreversible Functions D. Michael Miller 1 Robert Wille 2 Gerhard W. Dueck 3 1 Department of Computer Science, University of Victoria, Canada 2 Group for Computer Architecture

More information

Exact SAT-based Toffoli Network Synthesis

Exact SAT-based Toffoli Network Synthesis Eact SAT-based Toffoli Network Synthesis ABSTRACT Daniel Große Institute of Computer Science University of Bremen 28359 Bremen, Germany grosse@informatik.unibremen.de Gerhard W. Dueck Faculty of Computer

More information

Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits

Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits echnology Mapping of Reversible Circuits to Clifford+ Quantum Circuits Nabila Abdessaied Matthew Amy Mathias Soeken Rolf Drechsler Cyber-Physical Systems, DFKI Gmb, Bremen, Germany Department of Computer

More information

A Compact and Efficient SAT Encoding for Quantum Circuits

A Compact and Efficient SAT Encoding for Quantum Circuits A Compact and Efficient SAT Encoding for Quantum Circuits Robert Wille Nils Przigoda Rolf Drechsler Institute of Computer Science University of Bremen 8359 Bremen Germany Cyber-Physical Systems DFKI Gmb

More information

Permission to copy without fee all or part of this material is granted, provided that the copies are not made or distributed for direct commercial

Permission to copy without fee all or part of this material is granted, provided that the copies are not made or distributed for direct commercial Precomputation-Based Sequential Loic Optimization or Low Power Mazhar Alidina, Jose Monteiro, Srinivas Devadas Department o EECS MIT, Cambride, MA Marios Papaethymiou Department o EE Yale University, CT

More information

Synthesis of Fredkin-Toffoli Reversible Networks

Synthesis of Fredkin-Toffoli Reversible Networks IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL.???, NO.???,??? 2004 1 Synthesis of Fredkin-Toffoli Reversible Networks Dmitri Maslov, Gerhard W. Dueck, Member, IEEE, and D. Michael

More information

CHAPTER 2 AN ALGORITHM FOR OPTIMIZATION OF QUANTUM COST. 2.1 Introduction

CHAPTER 2 AN ALGORITHM FOR OPTIMIZATION OF QUANTUM COST. 2.1 Introduction CHAPTER 2 AN ALGORITHM FOR OPTIMIZATION OF QUANTUM COST Quantum cost is already introduced in Subsection 1.3.3. It is an important measure of quality of reversible and quantum circuits. This cost metric

More information

Technical Report: Projects & Background in Reversible Logic

Technical Report: Projects & Background in Reversible Logic Technical Report: Projects & Background in Reversible Logic TR-CSJR1-2005 J. E. Rice University of Lethbridge j.rice@uleth.ca 1 Introduction - What is Reversible Logic? In order to discuss new trends and

More information

Direct Design of Reversible Combinational and Sequential Circuits Using PSDRM Expressions

Direct Design of Reversible Combinational and Sequential Circuits Using PSDRM Expressions International Journal of Research in Engineering and Science (IJRES) ISSN (Online): 2320-9364, ISSN (Print): 2320-9356 Volume 3 Issue 11 ǁ November. 2015 ǁ PP.59-67 Direct Design of Reversible Combinational

More information

Binary decision diagrams for security protocols

Binary decision diagrams for security protocols for Instytut Informatyki Teoretycznej i Stosowanej Politechnika Częstochowska 4 czerwca 2012 roku 1 2 3 4 Infrastructure with Intruder Threat template 5 References BDD definition Definition An BDD G

More information

Simpler Functions for Decompositions

Simpler Functions for Decompositions Simpler Functions or Decompositions Bernd Steinbach Freiberg University o Mining and Technology, Institute o Computer Science, D-09596 Freiberg, Germany Abstract. This paper deals with the synthesis o

More information

Logic Design 2013/9/26. Introduction. Chapter 4: Optimized Implementation of Logic Functions. K-map

Logic Design 2013/9/26. Introduction. Chapter 4: Optimized Implementation of Logic Functions. K-map 2/9/26 Loic Desin Chapter 4: Optimized Implementation o Loic Functions Introduction The combinin property allows us to replace two minterms that dier in only one variable with a sinle product term that

More information

Logic Synthesis for Quantum State Generation

Logic Synthesis for Quantum State Generation Logic Synthesis for Quantum State Generation Philipp Niemann Department of Computer Science, University of Bremen, D-8359 Bremen, Germany Email: pniemann@csuni-bremende Rhitam Datta Indian Institute of

More information

A Shared-cube Approach to ESOP-based Synthesis of Reversible Logic

A Shared-cube Approach to ESOP-based Synthesis of Reversible Logic FACTA UNIVERSITATIS (NIŠ) SER.: ELEC. ENERG. vol. 16, April 24, xx-xx A Shared-cube Approach to ESOP-based Synthesis of Reversible Logic N. M. Nayeem and J. E. Rice Abstract: Reversible logic is being

More information

A Multigrid-like Technique for Power Grid Analysis

A Multigrid-like Technique for Power Grid Analysis A Multirid-like Technique for Power Grid Analysis Joseph N. Kozhaya, Sani R. Nassif, and Farid N. Najm 1 Abstract Modern sub-micron VLSI desins include hue power rids that are required to distribute lare

More information

Quantum Multiple-Valued Decision Diagrams Containing Skipped Variables

Quantum Multiple-Valued Decision Diagrams Containing Skipped Variables Quantum Multiple-Valued Decision Diagrams Containing Skipped Variables DAVID Y. FEINSTEIN 1, MITCHELL A. THORNTON 1 Innoventions, Inc., 1045 Bissonnet Street, Houston, TX, USA Dept. of Computer Science

More information

Improved ESOP-based Synthesis of Reversible Logic

Improved ESOP-based Synthesis of Reversible Logic Improved ESOP-based Synthesis of Reversible Logic N. M. Nayeem Dept. of Math & Computer Science University of Lethbridge Lethbridge, AB, Canada noor.nayeem@uleth.ca J. E. Rice Dept. of Math & Computer

More information

Equivalence Checking of Reversible Circuits

Equivalence Checking of Reversible Circuits Please note: Methods introduced in this paper are availabe at wwwrevkitorg Equivalence Checking of Reversible Circuits Robert Wille Daniel Große D Michael Miller 2 Rolf Drechsler Institute of Computer

More information

Variable Reordering for Reversible Wave Cascades - PRELIMINARY VERSION

Variable Reordering for Reversible Wave Cascades - PRELIMINARY VERSION Variable Reordering for Reversible Wave Cascades - PRELIMINARY VERSION Dimitrios Voudouris, Marinos Sampson and George Papakonstantinou National Technical University of Athens, Greece. Abstract In this

More information

REMARKS ON THE NUMBER OF LOGIC NETWORKS WITH SAME COMPLEXITY DERIVED FROM SPECTRAL TRANSFORM DECISION DIAGRAMS

REMARKS ON THE NUMBER OF LOGIC NETWORKS WITH SAME COMPLEXITY DERIVED FROM SPECTRAL TRANSFORM DECISION DIAGRAMS REMARKS ON THE NUMBER OF LOGIC NETORKS ITH SAME COMPLEXITY DERIVED FROM SPECTRAL TRANSFORM DECISION DIAGRAMS Radomir S. Stanković Mark G. Karpovsky 1 Dept. of Computer Science, Faculty of Electronics,

More information

5. Network Analysis. 5.1 Introduction

5. Network Analysis. 5.1 Introduction 5. Network Analysis 5.1 Introduction With the continued rowth o this country as it enters the next century comes the inevitable increase in the number o vehicles tryin to use the already overtaxed transportation

More information

Optimized Reversible Programmable Logic Array (PLA)

Optimized Reversible Programmable Logic Array (PLA) Journal of Advances in Computer Research Quarterly ISSN: 28-6148 Sari Branch, Islamic Azad University, Sari, I.R.Iran (Vol. 4, No. 1, February 213), Pages: 81-88 www.jacr.iausari.ac.ir Optimized Reversible

More information

CpE358/CS381. Switching Theory and Logical Design. Class 7

CpE358/CS381. Switching Theory and Logical Design. Class 7 CpE358/CS38 Switchin Theory and Loical Desin Class 7 CpE358/CS38 Summer 24 Copyriht 24 236 Today Fundamental concepts o diital systems (Mano Chapter ) Binary codes, number systems, and arithmetic (Ch )

More information

Self-Inverse Functions and Palindromic Circuits

Self-Inverse Functions and Palindromic Circuits Self-Inverse Functions and Palindromic Circuits Mathias Soeken 1,2 Michael Kirkedal Thomsen 1 Gerhard W. Dueck 3 D. Michael Miller 4 1 Department of Mathematics and Computer Science, University of Bremen,

More information

Design of an Online Testable Ternary Circuit from the Truth Table

Design of an Online Testable Ternary Circuit from the Truth Table Design of an Online Testable Ternary Circuit from the Truth Table N. M. Nayeem and J. E. Rice Dept. of Math & Computer Science University of Lethbridge, Lethbridge, Canada {noor.nayeem,j.rice}@uleth.ca

More information

On Universality of Ternary Reversible Logic Gates

On Universality of Ternary Reversible Logic Gates On Universality of Ternary Reversible Logic Gates Pawel Kerntopf*, Marek A. Perkowski**, Mozammel H. A. Khan*** *Institute of Computer Science, Department of Electronics and Information Technology, Warsaw

More information

Grover Algorithm Applied to Four Qubits System

Grover Algorithm Applied to Four Qubits System www.ccsenet.org/cis Computer and Inormation Science Vol., No. ; May Grover Algorithm Applied to Four Qubits System Z. Sakhi (Corresponding author) Laboratory o Inormation Technology and Modelisation, and

More information

Categories and Quantum Informatics: Monoidal categories

Categories and Quantum Informatics: Monoidal categories Cateories and Quantum Inormatics: Monoidal cateories Chris Heunen Sprin 2018 A monoidal cateory is a cateory equipped with extra data, describin how objects and morphisms can be combined in parallel. This

More information

Work It, Wrap It, Fix It, Fold It

Work It, Wrap It, Fix It, Fold It 1 Work It, Wrap It, Fix It, Fold It NEIL SCULTHORPE University o Kansas, USA GRAHAM HUTTON University o Nottinham, UK Abstract The worker/wrapper transormation is a eneral-purpose technique or reactorin

More information

Available online at ScienceDirect. Procedia Computer Science 57 (2015 )

Available online at  ScienceDirect. Procedia Computer Science 57 (2015 ) vailable online at www.sciencedirect.com ScienceDirect Procedia Computer Science 57 (25 ) 99 28 3 rd International Conference on Recent Trends in Computin 25 (ICRTC - 25) Efficient desin and analysiss

More information

Generalized Tree Architecture with High-Radix Processing for an SC Polar Decoder

Generalized Tree Architecture with High-Radix Processing for an SC Polar Decoder Generalized Tree Architecture with Hih-Radix Processin or an SC Polar ecoder Tae-Hwan Kim Korea Aerospace University Santa Clara, CA 1 Outline Backround Polar codes SC decodin / decoder architecture Proposed

More information

arxiv: v1 [quant-ph] 20 Jul 2009

arxiv: v1 [quant-ph] 20 Jul 2009 An analysis of reversible multiplier circuits Anindita Banerjee and Anirban Pathak March 9, 2018 Jaypee Institute of Information Technology University, Noida, India arxiv:0907.3357v1 [quant-ph] 20 Jul

More information

DD representation, the equivalence chec or specication and implementation translates to the chec whether the corresponding DDs are identical. The most

DD representation, the equivalence chec or specication and implementation translates to the chec whether the corresponding DDs are identical. The most Technical Report 02, Albert-Ludwigs-University, Freiburg, May 998. Word-Level Decision Diagrams, WLCDs and Division Christoph Scholl Bernd Becer Thomas M. Weis Institute o Computer Science Albert{Ludwigs{University

More information

COMPRESSED STATE SPACE REPRESENTATIONS - BINARY DECISION DIAGRAMS

COMPRESSED STATE SPACE REPRESENTATIONS - BINARY DECISION DIAGRAMS QUALITATIVE ANALYIS METHODS, OVERVIEW NET REDUCTION STRUCTURAL PROPERTIES COMPRESSED STATE SPACE REPRESENTATIONS - BINARY DECISION DIAGRAMS LINEAR PROGRAMMING place / transition invariants state equation

More information

Binary Decision Diagrams

Binary Decision Diagrams Binary Decision Diagrams Logic Circuits Design Seminars WS2010/2011, Lecture 2 Ing. Petr Fišer, Ph.D. Department of Digital Design Faculty of Information Technology Czech Technical University in Prague

More information

Symmetrical, Dual and Linear Functions and Their Autocorrelation Coefficients

Symmetrical, Dual and Linear Functions and Their Autocorrelation Coefficients Symmetrical, Dual and Linear Functions and Their Autocorrelation Coefficients in the Proceedings of IWLS005 J. E. Rice Department of Math & Computer Science University of Lethbridge Lethbridge, Alberta,

More information

Tearing Based Automatic Abstraction for CTL Model Checking. Woohyuk Lee Abelardo Pardo Jae-Young Jang Gary Hachtel Fabio Somenzi

Tearing Based Automatic Abstraction for CTL Model Checking. Woohyuk Lee Abelardo Pardo Jae-Young Jang Gary Hachtel Fabio Somenzi Tearin Based Automatic Abstraction for CTL Model Checkin Woohyuk Lee Abelardo Pardo Jae-Youn Jan Gary Hachtel Fabio Somenzi University of Colorado ECEN Campus Box 425 Boulder, CO, 80309 Abstract In this

More information

The Ideal thermodynamic cycle for gas liquefaction is impractical and hence modified cycles are proposed.

The Ideal thermodynamic cycle for gas liquefaction is impractical and hence modified cycles are proposed. Earlier Lecture The Ideal thermodynamic cycle or as liqueaction is impractical and hence modiied cycles are proposed. An Ideal cycle is used as a benchmark and in eect, dierent ratios and unctions are

More information

The Method of Reversible Circuits Design with One-gate Prediction

The Method of Reversible Circuits Design with One-gate Prediction INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2018, VOL. 64, NO. 4, PP. 535-540 Manuscript received April 17, 2018; revised October, 2018. DOI: 10.24425/123556 The Method of Reversible Circuits Design

More information

Using πdds for Nearest Neighbor Optimization of Quantum Circuits

Using πdds for Nearest Neighbor Optimization of Quantum Circuits sing πdds for Nearest Neighbor Optimization of Quantum Circuits Robert Wille 1,2, Nils Quetschlich 3, Yuma Inoue 4, Norihito Yasuda 4, and Shin-ichi Minato 4 1 Institute for Integrated Circuits, Johannes

More information

High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex Family

High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex Family International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 11, Issue 04 (April 2015), PP.72-77 High Speed Time Efficient Reversible ALU Based

More information

On Nonpermutational Transformation Semigroups with an Application to Syntactic Complexity

On Nonpermutational Transformation Semigroups with an Application to Syntactic Complexity Acta Cybernetica 22 (2016) 687 701. On Nonpermutational Transormation Semiroups with an Application to Syntactic Complexity Szabolcs Iván and Judit Nay-Györy Abstract We ive an upper bound o n((n 1)! (n

More information

Functions. Introduction

Functions. Introduction Functions,00 P,000 00 0 y 970 97 980 98 990 99 000 00 00 Fiure Standard and Poor s Inde with dividends reinvested (credit "bull": modiication o work by Prayitno Hadinata; credit "raph": modiication o work

More information

Synchronous Machines: a Traced Category

Synchronous Machines: a Traced Category Synchronous Machines: a Traced Cateory Marc anol, Guatto drien To cite this version: Marc anol, Guatto drien. Synchronous Machines: a Traced Cateory. [Research Report] 2012. HL Id: hal-00748010

More information

Control gates as building blocks for reversible computers

Control gates as building blocks for reversible computers Control gates as building blocks for reversible computers A. De Vos 1, B. Desoete 2, F. Janiak 3, and A. Nogawski 3 1 Universiteit Gent and Imec v.z.w., B-9000 Gent, Belgium 2 Universiteit Gent, B-9000

More information

Synthesis of Reversible Circuits for Large Reversible Functions

Synthesis of Reversible Circuits for Large Reversible Functions Portland State University PDXScholar Electrical and Computer Engineering Faculty Publications and Presentations Electrical and Computer Engineering 12-2010 Synthesis of Reversible Circuits for Large Reversible

More information

Group Theory Based Synthesis of Binary Reversible Circuits

Group Theory Based Synthesis of Binary Reversible Circuits Group Theory Based Synthesis of Binary Reversible Circuits Guowu Yang 1,XiaoyuSong 2, William N.N. Hung 2,FeiXie 1, and Marek A. Perkowski 2 1 Dept. of Computer Science, Portland State University, Portland,

More information

Technology Mapping and Optimization for Reversible and Quantum Circuits

Technology Mapping and Optimization for Reversible and Quantum Circuits Technology Mapping and Optimization for Reversible and Quantum Circuits by Zahra Sasanian B.Sc., University of Tehran, 2006 M.Sc., Amirkabir University of Technology, 2008 A Dissertation Submitted in Partial

More information

A simple approximation for seismic attenuation and dispersion in a fluid-saturated porous rock with aligned fractures

A simple approximation for seismic attenuation and dispersion in a fluid-saturated porous rock with aligned fractures A simple approximation or seismic attenuation and dispersion in a luid-saturated porous rock with alined ractures Robert Galvin 1,, Julianna Toms 1, and Boris Gurevich 1, 1 Curtin University o Technoloy,

More information

Slowly Changing Function Oriented Growth Analysis of Differential Monomials and Differential Polynomials

Slowly Changing Function Oriented Growth Analysis of Differential Monomials and Differential Polynomials Slowly Chanin Function Oriented Growth Analysis o Dierential Monomials Dierential Polynomials SANJIB KUMAR DATTA Department o Mathematics University o kalyani Kalyani Dist-NadiaPIN- 7235 West Benal India

More information

No.6 Lower Bound Estimation o Hardware Resources 719 ILP ormulation to compute the lower bound on unctional units by considerin the interdependence o

No.6 Lower Bound Estimation o Hardware Resources 719 ILP ormulation to compute the lower bound on unctional units by considerin the interdependence o Vol.17 No.6 J. Comput. Sci. & Technol. Nov. 2002 Lower Bound Estimation o Hardware Resources or Schedulin in Hih-Level Synthesis Shen Zhaoxuan and Jon Chin Chuen School o Electrical and Electronic Enineerin

More information

Templates for Positive and Negative Control Toffoli Networks

Templates for Positive and Negative Control Toffoli Networks Templates for Positive and Negative Control Toffoli Networks Md Zamilur Rahman and Jacqueline E. Rice Department of Mathematics and Computer Science, University of Lethbridge, Lethbridge, AB, Canada {mdzamilur.rahman,j.rice}@uleth.ca

More information

Petri Nets, Discrete Physics, and Distributed Quantum Computation

Petri Nets, Discrete Physics, and Distributed Quantum Computation Petri Nets, Discrete Physics, and Distributed Quantum Computation Samson bramsky Oxord University Computin Laboratory This paper is dedicated to Uo Montanari on the occasion o his 65th birthday. bstract.

More information

Improvement of Sparse Computation Application in Power System Short Circuit Study

Improvement of Sparse Computation Application in Power System Short Circuit Study Volume 44, Number 1, 2003 3 Improvement o Sparse Computation Application in Power System Short Circuit Study A. MEGA *, M. BELKACEMI * and J.M. KAUFFMANN ** * Research Laboratory LEB, L2ES Department o

More information

Realization of 2:4 reversible decoder and its applications

Realization of 2:4 reversible decoder and its applications Realization of 2:4 reversible decoder and its applications Neeta Pandey n66pandey@rediffmail.com Nalin Dadhich dadhich.nalin@gmail.com Mohd. Zubair Talha zubair.talha2010@gmail.com Abstract In this paper

More information

Reversible Function Synthesis with Minimum Garbage Outputs

Reversible Function Synthesis with Minimum Garbage Outputs Reversible Function Synthesis with Minimum Garbage Outputs Gerhard W. Dueck and Dmitri Maslov Faculty of Computer Science University of New Brunswick Fredericton, N.B. E3B 5A3 CANADA Abstract Reversible

More information

( ) x y z. 3 Functions 36. SECTION D Composite Functions

( ) x y z. 3 Functions 36. SECTION D Composite Functions 3 Functions 36 SECTION D Composite Functions By the end o this section you will be able to understand what is meant by a composite unction ind composition o unctions combine unctions by addition, subtraction,

More information

Categorical Background (Lecture 2)

Categorical Background (Lecture 2) Cateorical Backround (Lecture 2) February 2, 2011 In the last lecture, we stated the main theorem o simply-connected surery (at least or maniolds o dimension 4m), which hihlihts the importance o the sinature

More information

arxiv:quant-ph/ v2 2 Mar 2004

arxiv:quant-ph/ v2 2 Mar 2004 The oic o Entanlement Bob Coecke Oxord University Computin aboratory, Wolson Buildin, Parks Road, OX QD Oxord, UK. coecke@comlab.ox.ac.uk arxiv:quant-ph/000v Mar 00 Abstract. We expose the inormation low

More information

BDD Based Upon Shannon Expansion

BDD Based Upon Shannon Expansion Boolean Function Manipulation OBDD and more BDD Based Upon Shannon Expansion Notations f(x, x 2,, x n ) - n-input function, x i = or f xi=b (x,, x n ) = f(x,,x i-,b,x i+,,x n ), b= or Shannon Expansion

More information

A Novel Synthesis Algorithm for Reversible Circuits

A Novel Synthesis Algorithm for Reversible Circuits A Novel Synthesis Algorithm for Reversible Circuits Mehdi Saeedi, Mehdi Sedighi*, Morteza Saheb Zamani Email: {msaeedi, msedighi, szamani}@ aut.ac.ir Quantum Design Automation Lab, Computer Engineering

More information

A Hybrid Synchronous Language with Hierarchical Automata

A Hybrid Synchronous Language with Hierarchical Automata A Hybrid Synchronous Lanuae with Hierarchical Automata Static Typin and Translation to Synchronous Code Albert Benveniste 1 Benoît Caillaud 1 Timothy Bourke 1,2 Marc Pouzet 2,1 1. INRIA 2. ENS, Paris 18th

More information

An Algorithm for Minimization of Quantum Cost

An Algorithm for Minimization of Quantum Cost Appl. Math. Inf. Sci. 6, No. 1, 157-165 (2012) 157 Applied Mathematics & Information Sciences An International Journal An Algorithm for Minimization of Quantum Cost Anindita Banerjee and Anirban Pathak

More information

IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING 1

IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING 1 IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING 1 Intervention in Gene Reulatory Networks via a Stationary Mean-First-Passae-Time Control Policy Golnaz Vahedi, Student Member, IEEE, Babak Faryabi, Student

More information

FPGA-Based Circuit Model Emulation of Quantum Algorithms

FPGA-Based Circuit Model Emulation of Quantum Algorithms FPGA-Based Circuit Model Emulation of Quantum Algorithms Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi Quantum Design Automation Lab Computer Engineering Department, Amirkabir niversity

More information

Multi-Objective Synthesis of Quantum Circuits Using Genetic Programming

Multi-Objective Synthesis of Quantum Circuits Using Genetic Programming Multi-Objective Synthesis of Quantum Circuits Using Genetic Programming Moein Sarvaghad-Moghaddam 1, Philipp Niemann 2,3, and Rolf Drechsler 2,3 1 Young Researchers and Elite Club, Mashhad Branch, Islamic

More information

Propagation Modes in Multimode Graded-Index Fibers

Propagation Modes in Multimode Graded-Index Fibers International Journal o Science and Research (IJSR) ISSN (Online): 319-7064 Index Copernicus Value (013): 6.14 Impact Factor (015): 6.391 Propaation Modes in Multie Graded-Index Fibers Zaman Hameed Kareem

More information

AN OSCILLATOR MODEL FOR HIGH-PRECISION SYNCHRONIZATION PROTOCOL DISCRETE EVENT SIMULATION

AN OSCILLATOR MODEL FOR HIGH-PRECISION SYNCHRONIZATION PROTOCOL DISCRETE EVENT SIMULATION 39 th Annual Precise Time and Time Interval (PTTI Meetin AN OSCILLATOR MODEL FOR HIGH-PRECISION SYNCHRONIZATION PROTOCOL DISCRETE EVENT SIMULATION Geor Gaderer Austrian Academ o Sciences Viktor Kaplan

More information

Design Automation and Design Space Exploration for Quantum Computers

Design Automation and Design Space Exploration for Quantum Computers Design Automation and Design Space Exploration for Quantum Computers Mathias Soeken 1 Martin Roetteler 2 Nathan Wiebe 2 Giovanni De Micheli 1 1 Integrated Systems Laboratory, EPFL, Lausanne, Switzerland

More information

Synthesis of Quantum Circuit for FULL ADDER Using KHAN Gate

Synthesis of Quantum Circuit for FULL ADDER Using KHAN Gate Synthesis of Quantum Circuit for FULL ADDER Using KHAN Gate Madhumita Mazumder West Bengal University of Technology, West Bengal ABSTRACT Reversible and Quantum logic circuits have more advantages than

More information

Model to predict the mechanical behaviour of oriented rigid PVC

Model to predict the mechanical behaviour of oriented rigid PVC Louhborouh University Institutional Repository Model to predict the mechanical behaviour o oriented riid PVC This item was submitted to Louhborouh University's Institutional Repository by the/an author.

More information

Design of a Compact Reversible Random Access Memory

Design of a Compact Reversible Random Access Memory Design of a Compact Reversible Random Access Memory Farah Sharmin, Md. Masbaul Alam Polash, Md. Shamsujjoha, Lafifa Jamal, Hafiz Md. Hasan Babu Dept. of Computer Science & Engineering, University of Dhaka,

More information

The Category of Sets

The Category of Sets The Cateory o Sets Hans Halvorson October 16, 2016 [[Note to students: this is a irst drat. Please report typos. A revised version will be posted within the next couple o weeks.]] 1 Introduction The aim

More information

Thermodynamic wetness loss calculation in a steam turbine rotor tip section: nucleating steam flow

Thermodynamic wetness loss calculation in a steam turbine rotor tip section: nucleating steam flow Journal o Physics: Conerence Series PAPER OPEN ACCESS Thermodynamic wetness loss calculation in a steam turbine rotor tip section: nucleatin steam low To cite this article: Joby Joseph et al 016 J. Phys.:

More information

A General Class of Estimators of Population Median Using Two Auxiliary Variables in Double Sampling

A General Class of Estimators of Population Median Using Two Auxiliary Variables in Double Sampling ohammad Khoshnevisan School o Accountin and inance riith University Australia Housila P. Sinh School o Studies in Statistics ikram University Ujjain - 56. P. India Sarjinder Sinh Departament o athematics

More information

On the Difficulty of Inserting Trojans in Reversible Computing Architectures

On the Difficulty of Inserting Trojans in Reversible Computing Architectures On the Difficulty of Inserting Trojans in Reversible Computing Architectures Xiaotong Cui, Samah Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri, Chongqing University, China

More information

V DD. M 1 M 2 V i2. V o2 R 1 R 2 C C

V DD. M 1 M 2 V i2. V o2 R 1 R 2 C C UNVERSTY OF CALFORNA Collee of Enineerin Department of Electrical Enineerin and Computer Sciences E. Alon Homework #3 Solutions EECS 40 P. Nuzzo Use the EECS40 90nm CMOS process in all home works and projects

More information

On The Complexity of Quantum Circuit Manipulation

On The Complexity of Quantum Circuit Manipulation On The Complexity of Quantum Circuit Manipulation Vincent Liew 1 Introduction The stabilizer class of circuits, introduced by Daniel Gottesman, consists of quantum circuits in which every gate is a controlled-not

More information

The Deutsch-Jozsa Problem: De-quantization and entanglement

The Deutsch-Jozsa Problem: De-quantization and entanglement The Deutsch-Jozsa Problem: De-quantization and entanglement Alastair A. Abbott Department o Computer Science University o Auckland, New Zealand May 31, 009 Abstract The Deustch-Jozsa problem is one o the

More information

Simple Optimization (SOPT) for Nonlinear Constrained Optimization Problem

Simple Optimization (SOPT) for Nonlinear Constrained Optimization Problem (ISSN 4-6) Journal of Science & Enineerin Education (ISSN 4-6) Vol.,, Pae-3-39, Year-7 Simple Optimization (SOPT) for Nonlinear Constrained Optimization Vivek Kumar Chouhan *, Joji Thomas **, S. S. Mahapatra

More information

An Improved Logical Effort Model and Framework Applied to Optimal Sizing of Circuits Operating in Multiple Supply Voltage Regimes

An Improved Logical Effort Model and Framework Applied to Optimal Sizing of Circuits Operating in Multiple Supply Voltage Regimes n Improved Loical Effort Model and Framework pplied to Optimal Sizin of Circuits Operatin in Multiple Supply Voltae Reimes Xue Lin, Yanzhi Wan, Shahin Nazarian, Massoud Pedram Department of Electrical

More information

Study of In line Tube Bundle Heat Transfer to Downward Foam Flow

Study of In line Tube Bundle Heat Transfer to Downward Foam Flow Proceedins o the 5th IASME/WSEAS Int. Conerence on Heat Transer, Thermal Enineerin and Environment, Athens, Greece, Auust 25-27, 7 167 Study o In line Tube Bundle Heat Transer to Downward Foam Flow J.

More information

EECS 219C: Computer-Aided Verification Boolean Satisfiability Solving III & Binary Decision Diagrams. Sanjit A. Seshia EECS, UC Berkeley

EECS 219C: Computer-Aided Verification Boolean Satisfiability Solving III & Binary Decision Diagrams. Sanjit A. Seshia EECS, UC Berkeley EECS 219C: Computer-Aided Verification Boolean Satisfiability Solving III & Binary Decision Diagrams Sanjit A. Seshia EECS, UC Berkeley Acknowledgments: Lintao Zhang Announcement Project proposals due

More information

Western University. Imants Barušs King's University College, Robert Woodrow

Western University. Imants Barušs King's University College, Robert Woodrow Western University Scholarship@Western Psycholoy Psycholoy 2013 A reduction theorem or the Kripke-Joyal semantics: Forcin over an arbitrary cateory can always be replaced by orcin over a complete Heytin

More information

Spectral Techniques for Reversible Logic Synthesis

Spectral Techniques for Reversible Logic Synthesis Spectral Techniques or Reersible Logic Synthesis D. Michael Miller Gerhard W. Dueck Department o Computer Science Faculty o Computer Science Uniersity o Victoria Uniersity o New Brunswick Victoria, BC,

More information

Mixture Behavior, Stability, and Azeotropy

Mixture Behavior, Stability, and Azeotropy 7 Mixture Behavior, Stability, and Azeotropy Copyrihted Material CRC Press/Taylor & Francis 6 BASIC RELATIONS As compounds mix to some deree in the liquid phase, the Gibbs enery o the system decreases

More information

Strong Interference and Spectrum Warfare

Strong Interference and Spectrum Warfare Stron Interference and Spectrum Warfare Otilia opescu and Christopher Rose WILAB Ruters University 73 Brett Rd., iscataway, J 8854-86 Email: {otilia,crose}@winlab.ruters.edu Dimitrie C. opescu Department

More information

DESIGN OF A COMPACT REVERSIBLE READ- ONLY-MEMORY WITH MOS TRANSISTORS

DESIGN OF A COMPACT REVERSIBLE READ- ONLY-MEMORY WITH MOS TRANSISTORS DESIGN OF A COMPACT REVERSIBLE READ- ONLY-MEMORY WITH MOS TRANSISTORS Sadia Nowrin, Papiya Nazneen and Lafifa Jamal Department of Computer Science and Engineering, University of Dhaka, Bangladesh ABSTRACT

More information

Technical Report: Considerations for Determining a Classification Scheme for Reversible Boolean Functions

Technical Report: Considerations for Determining a Classification Scheme for Reversible Boolean Functions Technical Report: Considerations for Determining a Classification Scheme for Reversible Boolean Functions 1 Introduction TR-CSJR2-2007 J. E. Rice University of Lethbridge j.rice@uleth.ca For many years

More information

Title. Citation Information Processing Letters, 112(16): Issue Date Doc URLhttp://hdl.handle.net/2115/ Type.

Title. Citation Information Processing Letters, 112(16): Issue Date Doc URLhttp://hdl.handle.net/2115/ Type. Title Counterexamples to the long-standing conjectur Author(s) Yoshinaka, Ryo; Kawahara, Jun; Denzumi, Shuhei Citation Information Processing Letters, 112(16): 636-6 Issue Date 2012-08-31 Doc URLhttp://hdl.handle.net/2115/50105

More information

Asynchronous Parallel Programming in Pei. E. Violard. Boulevard S. Brant, F Illkirch.

Asynchronous Parallel Programming in Pei. E. Violard. Boulevard S. Brant, F Illkirch. Asynchronous Parallel Prorammin in Pei E. Violard ICPS, Universite Louis Pasteur, Strasbour Boulevard S. Brant, F-67400 Illkirch e-mail: violard@icps.u-strasb.r Abstract. This paper presents a transormational

More information

Basing Decisions on Sentences in Decision Diagrams

Basing Decisions on Sentences in Decision Diagrams Proceedings of the Twenty-Sixth AAAI Conference on Artificial Intelligence Basing Decisions on Sentences in Decision Diagrams Yexiang Xue Department of Computer Science Cornell University yexiang@cs.cornell.edu

More information