Available online at ScienceDirect. Procedia Computer Science 57 (2015 )

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1 vailable online at ScienceDirect Procedia Computer Science 57 (25 ) rd International Conference on Recent Trends in Computin 25 (ICRTC - 25) Efficient desin and analysiss of N-bit reversible shift reisters. Majumder a, *, P.L. Sinh b,. Chowdhury b,.j. Mondal a, V. nand a a Department of ECE, NIT runachal Pradesh, Yupia 792, India b Department of CSE, NIT runachal Pradesh, Yupia 792, India bstract The biest motivation to study reversible technoloies is that, it is considered to be the best potential way to improve the enery efficiency than the conventional models. It has shown reater impact to have etensive applications in emerin technoloies such as uantum Computin, C, Nanotechnoloy and Low Power VLSI. In this paper, we have realized some new desins of several types of reisters includin universal shift reister up to N-bit and a dynamic reister. We have also analyzed the cost metrics of these structures in tabular form and also with some lemmas. While approachin for universal shift reisters we have demonstrated a novel desin of reversible multipleer which is discussed in terms of an alorithm. 25 The uthors. Published by by Elsevier.V..V. This is an open access article under the CC Y-NC-ND license Selection ( and/or peer-review under responsibility of the oranizers of the 3 rd International Conference on Recent Trends in Computin Peer-review under 25 (ICRTC responsibility - 25) of oranizin committee of the 3rd International Conference on Recent Trends in Computin 25 (ICRTC-25) Keywords: Reversible Loic; uantum Cost; Reversible D Flip-Flop; Reversible Reisters.. Introduction The world of computin is in transition. Technoloies are rowin eponentially in present era and as devices become more compact, the consumption of power and heat dissipation is becomin the major limitation of these devices. ccordin to the Rolf Landauer s principle [] iven in 96, the conventional loic ates or irreversible loic ates dissipates KTln2 joules of enery for the loss of -bit information where K is the oltzmann constant and T is the absolute temperature at which operation is performed. In irreversible loic computation, the amount of enery dissipate is directly proportional to the number of bits erased durin computation. ccordin to second law of thermodynamics, information once lost cannot be recovered by any methods [2]. Charles ennett [3] in 973, ave a solution to the problem of power dissipation in conventional * lak Majumder, ssistant Professor, Department of ECE, NIT runachal Pradesh, Yupia, India. Tel.: address: majumder.alak@mail.com The uthors. Published by Elsevier.V. This is an open access article under the CC Y-NC-ND license ( Peer-review under responsibility of oranizin committee of the 3rd International Conference on Recent Trends in Computin 25 (ICRTC-25) doi:.6/j.procs

2 2. Majumder et al. / Procedia Computer Science 57 ( 25 ) loic circuits. ennett proposed that in order to avoid the KTln2 joules of power dissipation loic circuit must be built from reversible circuit since there is no information loss occurs in reversible circuits. For the computation to be physically reversible not to dissipate any enery, computin enine should be made loically reversible and desined in physically reversible technoloy. ny system that does transition from state P to state is physically reversible if the state uniquely determines state P, that is, the transition is loically reversible and the enery is present to make the reverse transition which means the transition is made in physically reversible technoloy. Tommaso Toffoli [4] in 98, first predicted that any arbitrary loic function can be realized and any of computational work can be done usin reversible circuits as are used in irreversible loic circuits. Toffoli states that usin invertible loic ates, it is ideally possible to build a sequential computer with zero internal power dissipation. Fredkin has used this concept to propose the first desin of the reversible sequential circuit called the JK-latch [Fredkin and Toffoli 982] havin the feedback loop from the output. In this paper, we are presentin the desin of reversible reister circuit considerin important cost metrics in reversible loic circuits i.e. the quantum cost, delay and number of arbae outputs. lso, with some lemmas their efficiency has been featured. 2. asic Reversible Gates There are some reversible basic ates which we are oin to use in desin of Flip-Flops and are as follows. 2.. Reversible NOT Gate NOT ate is a simple input and output (*) reversible ate which performs inversion of input. It has quantum cost and unit delay. NOT ate and its quantum representation is shown in the fiure Feynman ate/cnot Gate Fi.. (a) NOT ate; (b) NOT ate quantum representation It is a 2 input and 2 output (2*2) reversible loic ate. CNOT Gate, also known as FEYNMN Gate, is widely used to overcome the fan-out problem since it can be used for copyin the information. CNOT ate has unit delay & unit quantum cost Peres Gate Not Gate Fi.2. (a) ate; (b) uantum representation of ate Peres ate is a 4-input and 4-output (4*4) reversible ate. It has a minimum quantum cost amon the 4*4 reversible ate and is equal to 4 and delay is 4Δ.

3 . Majumder et al. / Procedia Computer Science 57 ( 25 ) PG C C C V + V + V C 2.4. Proposed Reversible Modified Fredkin Gate Fi. 3. (a) PG ate; (b) uantum representation of PG ate s the name suests it is the proposed modified version of 3*3 Fredkin ate with a quantum cost of 4 and a delay of 4Δ. When =, it does the same as Fredkin Gate, but when =, and complement of C is swapped in the output. C MF 3. Proposed Reversible Multipleer Fi.4. (a) MF ate; (b) uantum representation of MF ate In this section, we are presentin proposed new desin of reversible multipleer usin reversible loic ate. multipleer is a loic circuit that accepts number of data input and produces a sinle output at a time. The selection of the sinle output from multiple inputs is controlled by select line. Generally, there are 2 n data input lines where n is select line whose bit combination select the output from the applied inputs. Multipleer is also called as multi-position, diitally controlled switch. 3.. Proposed Reversible 2: Multipleer It has 2 data input lines, one select line and one output line. Fiure 6 shows the proposed desin of reversible 2: mu. Fi.5. Reversible 2: Mu usin MF ate Fiure 5 shows the reversible 2: mu where and are the data inputs and s is select line. When S is hih (i.e. S=) then data input transmit to the output O and when S becomes low (i.e. S=) then data input transmit to the output. uantum cost (c) and delay (D) of 2: mu is 4 and arbae output (G) is Proposed Reversible 4: Multipleer C C S 2: C Mu (MF) V V V + C C The reversible 4: multipleer (2 2 : mu) has four data input lines, two select lines and one output line. It can be realized usin three 2: mu as shown in the followin fiure S b O S I3 I2 I I 2: Mu (MF) 2: Mu (MF) S b S S b 2: Mu (MF) S b O I3 I2 I I S S S 4: Mu S O

4 22. Majumder et al. / Procedia Computer Science 57 ( 25 ) Fi.6. (a) Proposed reversible 4: mu; (b) lock diaram of reversible 4: mu Fiure 6 shows the proposed desin of reversible 4: mu where I,I, I2 and I3 are the data input lines S and S are the select lines whose bit combination control the function of 4: mu with parameters c and D is 2 and G is 3. The function of S and S are as follow Table.. Function of S and S select lines S S Output (O) I I I2 I Proposed Reversible 2 n : Multipleer The 2 n : reversible multipleer has 2 n data input lines, n select lines and one output line. 2 n :reversible mu can be realize in a same way as 4: mu realized usin 2: mu. 2 n : mu can be realize usin two 2 n- : reversible mu and one 2: reversible mu as shown in the followin fiure S n- In n: mu In- S n 2: mu S n O I n: mu S n- I 4. Reversible Memory Element Fi.7. Proposed desin of reversible 2 n : multipleer usin MF ate In this section, we are presentin some new desin of reversible sequential circuits Flip-Flop () i.e. D- which will be used to desin reversible reister. 4.. Proposed Reversible D-Flip-Flop Characteristic equation of reversible D-Latch can be written as + =D where output is equal to its input value. The characteristic equation of clock enabled reversible D-Latch (D-) can be written as +=D.E+E. () E D MF E E D MF E

5 . Majumder et al. / Procedia Computer Science 57 ( 25 ) Fi.8.( a) Clock enabled D-latch; (b) D- with output and Fiure 8(a) shows the clock enable D-latch where output +=D for E= and output += for E= output remain in its previous state. For the input D= and =, the output of MF ate when E= is += which is applied to ate to provide feedback. Table 2. Comparison of Reversible D- with D- Comparison uantum Delay Garbae Cost (c) (D) Output(G) [Thapliyal and Rananathan 2][9] Proposed desin % improvement w.r.t. [9] The block diaram of a reversible D- is shown in fiure. 5. Proposed Reversible uffer Reister E D E D Fi.9. lock diaram of reversible D- uffer reister is one of the simplest kinds of shift reister used to store binary word. The binary word is applied to data input terminals. On application of clock pulse, the data input word transferred to the output terminals that is output word becomes same as the word applied at the input terminals. uffer reister is also known as the Parallel-in Parallel-out shift reister. 2 3 I D I2 D2 2 I3 D3 3 In Dn n Fi.. Proposed reversible buffer reister Fiure shows the desin of reversible buffer reister in which I I2 I3.In are the input data and 2 3..n are correspondin output then, on application of clock pulse the output becomes 2 3..n = I I2 I3.In (2) 4-bit PIPO shift reister has quantum cost (c) and delay (D) 2 and arbae output 4. Lemma I The minimum uantum cost (c) and delay (D) of n-bit reversible Ede triered PIPO shift reister is 5n. Proof For n-bit reversible PIPO shift reister it requires n- to store n-bit data. From fiure we can observe that n reversible D- is used to store n-bit data. Since each reversible D- has c of 5 and D of 5Δ, hence, we can calculate for n-bit reversible PIPO shift reister has total quantum cost and delay

6 24. Majumder et al. / Procedia Computer Science 57 ( 25 ) c/d = 5n (3) Lemma II n n-bit reversible Ede triered PIPO shift reister produces minimum arbae output (G)= n. Proof From fiure we can see that each reversible D flip-flop produces one arbae output. For n-bit reversible PIPO shift reister it require n-, hence, we can conclude that for n-bit PIPO shift reister total number of arbae output produced equal to G = n (4) 5.. Proposed Reversible Controlled uffer Reister Control buffer reister is shift reister in which output is controlled throuh a control input sinal. The followin fiure shows the desin of proposed reversible controlled buffer reister LOD I MF I2 MF I3 MF I4 MF D D2 2 D3 3 D4 4 Fi.. Desin of reversible controlled buffer reister for 4-bit LOD is control input which controls the output of buffer reister. When LOD sinal is HIGH then data inputs can appear at the input of the respective flip-flop, on the application of clock pulse reister loaded with the applied input data and output becomes as in equation (2). When LOD sinal oes LOW then the data inputs cannot appear at input terminal rather the output of each flip flop feedback to the its data input for each clock pulse applied i.e. data bits of buffer reister remain unchaned in spite of clock pulse. 6. Proposed Reversible Serial-in Serial-out Shift Reister Serial-in serial-out shift reister is used to store the data bits serially and produce output in serial form. The followin fiure shows the desin of reversible Serial-in Serial-out (SISO) shift reister I D D2 2 D3 3 Dn n Fi.2. Reversible SISO shift reister of n-bit Fiure 2 shows SISO shift reister of n-bit. D- is used for shift reister. In SISO shift reister data input is applied serially to the input terminal of first flip flop of shift reister and output is taken from the last flip flop of shift reister. When first clock pulse is applied the first bit stored in first flip-flop. For second clock pulse net bit is store in first flip flop and the previous bit shifted to net flip flop and the process of shiftin of bits continue till the all bits appear at the output. For n-bit SISO shift reister it requires n clock pulse to store all bits and n- clock pulse to produce output. 4-bit SISO shift reister has quantum cost, delay equal to 2 and arbae output equal to 4.

7 . Majumder et al. / Procedia Computer Science 57 ( 25 ) Lemma III The minimum uantum cost (c) and Delay (D) of reversible SISO shift reister is 5n. Proof For n-bit reversible SISO shift reister it requires n- to store n-bit data. From fiure 2 we can observe that n reversible D- is used to store n-bit data. Since each reversible D- has c of 5 and D of 5Δ, hence, we can calculate for n-bit reversible SISO shift reister has total quantum cost and delay c/d = 5n (5) Lemma IV n n-bit reversible Ede triered SISO shift reister produces minimum arbae output (G) n. Proof From fiure 2 we can see that each reversible D flip-flop produces one arbae output (). For n-bit reversible SISO shift reister it require n-, hence, we can conclude that for n-bit SISO shift reister total number of arbae output produced equal to G = n (6) 7. Proposed Reversible Serial-in Parallel-out Shift Reister This shift reister input is applied in serial form and output is taken in parallel form. The fiure 5 shows the desin of reversible serial-in Parallel-out shift reister. From fiure 3 it can be observed that input data is applied at the first flip flop of reister and first output of the Feynman ate is taken as the output of correspondin flip flop of shift reister and second output of Feynman ate is applied to net flip flop to shift the data 2 3 I D D2 D3 Dn n Fi.3. Desin of Reversible SIPO shift reister For 4-bit SIPO shift reister the quantum cost, delay is 23 and arbae output is 4. Lemma V The minimum required quantum cost (c) and delay (D) of n-bit reversible Ede triered SIPO shift reister is equal to 6n-. Proof From fiure 3 we can observe that reversible SIPO shift reister have D- (c=5 and D=5Δ) and Feynman ate (c= and D=Δ) for copyin the output of each reversible D- ecept last. For n-bit reversible SIPO shift reister it require n reversible D- and n- Feynman ate, hence, we can calculate the total c and D for n-bit reversible SIPO shift reister as c/d = 5n + n- (7) = 6n- Lemma VI n n-bit reversible Ede triered SIPO shift reister produces minimum arbae output (G) equal to n. Proof From fiure 3 we can observe that each flip-flop produces one arbae output. For 2-bit and 4-bit reversible shift reister it will produce 2=2 and 4=4 arbae output respectively. Hence, we can conclude that for n-bit reversible SIPO shift reister, the total arbae output is G = n (8)

8 26. Majumder et al. / Procedia Computer Science 57 ( 25 ) Proposed Reversible Parallel-in Serial-out Shift Reister Reversible parallel-in serial-out shift reister takes input in parallel form and produce output in serial form. Reversible multipleer is used to control the parallel load and serial output of data. Desin of reversible Parallel-in Serial-out (PISO) shift reister is shown in the followin fiure I D D2 2 D3 3 Dn n W/S 2 I2 mu I3 2 mu In 2 mu W/S Fi.4. Desin of Reversible PISO shift reister In the fiure 4 W/S is the control input of PISO shift reister. When W/S is put HIGH then multipleer load data parallel in shift reister and when W/S oes LOW then multipleer stop loadin data and start shiftin data from one flip-flop to net flip-flop. For 4-bit PISO shift reister the quantum cost and delay is 32 and arbae output is 7. Lemma VII The minimum required quantum cost (c) and delay (D) of n-bit reversible Ede triered PISO shift reister is equal to 9n-4. Proof From fiure 4 we can observe that reversible PISO shift reister have D- (c=5 and D=5Δ) and 2: multipleer (c=4 and D=4Δ) for controllin the operation of PISO shift reister ecept first. For n-bit reversible PISO shift reister it require n reversible D- and n- multipleer (2:), hence, c/d = 5n +4 (n-) = 9n-4 (9) Lemma VIII n-bit reversible Ede triered PISO shift reister produces minimum arbae output (G) equal to 2n-. Proof From fiure 4 we can observe that each flip-flop produces one arbae output and each multipleer produces one arbae output. Since n-bit PISO shift reister require n D- and n- multipleer, hence, we can conclude that for n-bit reversible PISO shift reister, the total arbae output is G = n + (n-) = 2n- () 9. Proposed Reversible Universal Shift Reister universal shift reister that has both shifts and parallel load capabilities, it is referred to as Universal shift reister. Universal shift reister can be realized usin reisters and multipleers. Fiure 7 shows the universal shift reister for n-bit storae. It consists of n-d flip flop and n- 4: multipleer. Multipleer have two common selection inputs S and S. S and S controls the operation of the universal shift reister and are listed in table.

9 . Majumder et al. / Procedia Computer Science 57 ( 25 ) n n- Dn Dn- D D S S Serial I/p for shift-riht R-4 Mu 3 2 R-4 Mu 3 2 R-4 Mu 3 2 R-4 Mu 3 2 Serial I/p for shift-left In In- I I Table.3. Function table of universal shift reister Fi.5. Desin of Reversible Universal shift reister S S Fuction No chane Shift Riht Shift Left Parallel Load. Proposed Reversible Dynamic Shift Reister ll shift reisters that we have shown in previous sections are Static shift reister. In dynamic shift reister storae is accomplished by continually shiftin the bits from one state to the net and re-circulatin the output of the last stae into the first stae. The data is continually circulates throuh the reister under the control of clock pulse. CS CSy PG W/R W R PG N-bit Shift Reister S/I MF PG Fi.6. Desin of Dynamic shift reister The process of reversible dynamic shift reister is iven in the followin table

10 28. Majumder et al. / Procedia Computer Science 57 ( 25 ) Table.4. Function table of Dynamic shift reister W/R CS CSy Fuction Write Re-circulate Re-circulate Re-circulate Read. Conclusion Reversible reisters may be considered as the brain of any computation as data is processed in us system throuh these and can replace the eistin ccumulator or other eneral purpose reisters available in processor architecture of the forthcomin quantum computers. In this paper, we have shown some novel architecture of several shift reisters includin universal shift reisters up to n-nit and dynamic shift reisters and analyzed them with some lemmas. efficient reversible realization of multipleer is discussed with the help of an alorithm. We are tryin to synthesis these structures usin Verilo HDL. The novel reversible reisters will play a bi role to reversible loic community to work further for the desin of a synchronous N- bit dual-port SRM array and DRM array for their application in FPG or Network-on-chip. References [] R. Landauer, Irreversibility and heat eneration in the computational process, IM Journal of Research. Dev. 5, 83-9, 96. [2] C. H. ennett, R. Landauer, The fundamentals physical limits of computation. [3] C. H. ennett, Loical reversibility of computation, IM Journal of Research. Devel. 7, , 973. [4] Tommaso Toffoli, Reversible Computin, utomata, Lanuaes and prorammin, 7 th Colloquium of Lecture Notes in Computer Science, vol. 85, pp ,98. [5]. Peres, Reversible loic and quantum computers, Phys. Rev., Gen. Phys. 32, 6, , 985. [6] H. Thapliyal, M.. Srinivas, M Zwolinski, beinnin in the reversible loic synthesis of sequential circuits. In proceedins of the Int. Conf. on the military & erospace Prorammable Loic devices, 25. [7] H. Thapliyal,. P. Vinod, Desin of reversible sequential elements with feasibility of transistor implementation In proceedins of the IEEE International Symposium on circuits and system, , 27. [8] M.L. Chuan, C.Y. Wan, Synthesis of reversible sequential elememts J. Emer. Technol. Comput. Syst. 3, 4, -9, 28 [9] H. Thapliyal and N. Rananathan Desin of Reversible Sequential Circuits Optimizin uantum Cost, Delay, and Garbae Outputs, CM Journal on Emerin Technoloies in Computer Systems, Vol. 6, No. 4, rticle4, Pub. Dec. 2. [] Michael a. Nielsen, Isaac L. Chuan, uantum Computation Information, Cambride University Press, New York, US 2. [] lak Majumder, Prasoon Lata Sinh, Nikhil Mishra, bir Jyoti Mondal, arnali Chowdhury, Novel Delay & uantum Cost Efficient Reversible Realization of 2 i j Random ccess Memory, International Conference on VLSI Systems, rchitecture, Technoloy and pplications (VLSI - ST 25), Sponsored by IEEE, anlore (ccepted). [2] Prasoon Lata Sinh, lak Majumder, arnali Chowdhury, Ranvijay Sinh, Nikhil Mishra, novel Realization of Reversible LFSR for its application in Cryptoraphy, SPIN 25, Sponsored by IEEE. (ccepted)