Spectral Techniques for Reversible Logic Synthesis

Transcription

1 Spectral Techniques or Reersible Logic Synthesis D. Michael Miller Gerhard W. Dueck Department o Computer Science Faculty o Computer Science Uniersity o Victoria Uniersity o New Brunswick Victoria, BC, Canada V8w 3P6 Fredericton, NB, Canada E3B 5A3 mmiller@csr.uic.ca gdueck@unb.ca ABSTRACT Reersible circuits can lead to low-power CMOS implementations and are also o interest in optical and quantum computing. In this paper, we consider the synthesis o reersible logic assuming a generalized Tooli gate. We make use o Rademacher-Walsh spectral techniques and in particular a spectral measure o unction complexity used as a metric in guiding the search or a solution. The synthesis procedure introduced deelops the circuit rom inputs to outputs and rom outputs to inputs simultaneously taking adantage o the best translation aailable at each step. No backtracking or lookahead is used. Preliminary results are gien or reersible and nonreersible unctions together with seeral ideas or uture work. 1. INTRODUCTION A digital circuit is reersible i it maps each input pattern to a unique output pattern. Landauer [9] proed that traditional irreersible gates lead to power dissipation in a circuit regardless o its implementation. Bennett [1] showed that or power not to be dissipated it is necessary that the circuit be build rom reersible gates. Reersible circuits are o interest because o their potential application in low-power CMOS design, quantum computation [12] and optical computing. Here we consider the synthesis o a reersible circuit as a composition o reersible logic gates. We do not elaborate on technology issues but do make the ollowing assumptions: (i) an-out is not permitted; (ii) loops are not permitted; and (ii) permutation o connections between gates is permitted. We assume a generalized Tooli gate which encompasses the NOT, Feynman [4], and 3*3 and 4*4 Tooli [19] gates. Fredkin [5] gates are not handled explicitly but can be identiied as a pair o identical Feynman gates with an appropriate interening Tooli gate. The work presented here is an extension to the work presented by the irst author in [13]. Synthesis o reersible logic is signiicantly dierent rom conentional logic synthesis. Since loops are not permitted, a reersible logic circuit can be speciied as a simple sequence o gates. Further since an-out is not permitted, and assuming an appropriate technology, a reersible logic circuit can realize the inerse speciication simply by applying the gates in the reerse order. Hence, synthesis can be carried out rom the inputs toward the outputs or rom the outputs toward the inputs. The method presented here synthesizes the circuit by working in both directions simultaneously, a signiicant improement to the method in [13] which worked only rom the outputs toward the inputs. In addition, as will be shown by example, it is adantageous to synthesize a circuit or a gien reersible speciication and also or the inerse speciication taking the solution to be the simpler o the two results. The paper is organized as ollows. Section 2 proides the necessary background on reersible logic, the Researcher-Walsh spectral domain, and the spectral measure o unction complexity used in this work. Section 3 describes output and input translation and presents the synthesis method. Reersible and irreersible examples are presented in Sections 4 and 5, respectiely. The paper concludes with obserations and suggestions or urther work in Section PRELIMINARIES 2.1 Reersible Logic Gates A reersible logic gate is a k-input, k-output (denoted k*k) deice that maps each possible input pattern to a unique output pattern. For the gates considered, not only is the circuit reersible, the orward and reerse mappings are identical. Many reersible logic gates hae been studied in the literature [2][4][5] [8][1][15][19]. Table 1 deines the reersible gates commonly considered in the literature. The bi-directional nature o these gates is emphasized by using conentional quantum logic notation [14] where the same labels are used on both sides o the gate. We use to denote the transormed side rather than a prime as oten used in the literature in order to aoid any conusion with complementation. One can readily eriy each o these gates is reersible. Feynman and 3*3 Tooli gates transorm a single ariable while the Fredkin gate transorm a pair o outputs.

2 Gate Type Functionality Gate Notation 1*1 Not x = x NOT(x) 2*2 Feynman [4] x = x y = x y 3*3 Tooli [19] x = x y = y z = xy z 3*3 Fredkin [5] x = x y = xy xz z = xz xy FEY(x,y) TOF3(x,y,z) FRE(x,y,z) Table 1: Reersible Logic Gates. The obious transormations apply regarding NOT and FEY. Further: FRE( xyz,, ) = FEY( yz, )TOF3( xzy,, )FEY( yz, ) (1) rom which it ollows that TOF3( xyz,, ) = FEY( zy, )FRE( xzy,, )FEY( zy, ) (2) The Tooli gate can be generalized to the n * n case in the obious way giing TOFn( x1, x2,..., xn 1, y) (3) x = x, y = x x... x y i i 1 2 n 1 From Table 1, we can see a Feynman gate is a TOF2 and a NOT gate can be interpreted as a TOF1 by treating the AND o an empty set o ariables as 1 and recalling 1 x = x. Equation (1) shows a Fredkin gate can be realized as a sequence o three generalized Tooli gates. Hence we shall concentrate on the use o generalized TOFn gates in our synthesis method. Note that higher order Tooli gates can be expressed as combinations o Tooli gates with ewer inputs by introducing constant inputs. For example, TOF4( wxyz,,, ) = TOF3( wxe,, ) TOF3( yez,, ) (4) where e is constant as input to the let TOF3. We assume complementation is internal to the generalized Tooli gate and will or example write TOF3(a',b',c) to mean c = a b c with a and b unaected as they pass through the gate. Our synthesis procedure does identiy some complementations which can not be absorbed into other gates. These we shall write as TOF1 gates. 2.2 Rademacher-Walsh Spectral Domain A completely-speciied Boolean unction ( xn,..., x2, x1) is deined by a column ector o 2 n s and 1 s denoted F. The Rademacher-Walsh spectrum [6] o the unction is gien by R = T F (5) n where the transorm matrix T is a Hadamard matrix deined as T = [ 1] p 1 p 1 T T (6) p T = p 1 p 1 T T Taking 1 as logic and 1 as logic 1, each row o the transorm matrix can be seen to correspond to the truth ector o the exclusie-or (EXOR) o a subset o x 1, x 2... x n. Each spectral coeicient thus measures the correlation o F to a particular EXOR unction and the spectral coeicients are identiied by subscripts indicating the ariables inoled, e.g. or n = 3, R = r r1 r2 r1,2 r3 r1,3 r2,3 r 1,2,3 (7) r denotes the EXOR o no ariables, i.e. the constant unction and can be seen to simply count the number o 1 s in F. All the other coeicients take alues in the range 2 n 1 denoting perect agreement with the corresponding EXOR unction and 2 n 1 denoting perect agreement with the complement o that EXOR unction. The coeicients r1, r2,..., r n are termed the irst-order coeicients. Each measures correlation to a single ariable. These are o particular importance to our method. Consider two unctions, and g with spectra R and R g, respectiely. Boolean operations can be perormed directly in the spectral domain [6] as shown in Table 1. NOT AND OR EXOR n n 2 1 g = g u u= r = 2 r ; r = r n r r r ( u is bit-wise ) g g g R = R R R g g g R = R R 2R Table 2: Logic Computations in the Spectral Domain. 2.3 Function Complexity One simple measure o unction complexity is a count o the number o adjacent s and adjacent 1 s on its Karnaugh map [7]. It has been shown [6], that this count is gien by 2

3 n 2 1 C 2 ( 1 n 1 ) 2 2 n n 2 2 = r (8) = where is the number o 1 s in the binary expansion o. Z ( R ), the number o zero coeicients in R, is a simple measure o the complexity o the spectrum o a unction but is not a direct measure o unction complexity since all EXOR unctions, including single ariables and their complements, hae 2 n 2 zero-alued coeicients. Howeer, all such unctions are equialent under linear translation [6][7], and hence amenable to implementation using Feynman gates, so Z ( R ) is o interest. In the synthesis procedure described below, we use the complexity metric D( ) = n2 n Z( R ) C( ) (9) D( ) gies a higher alue the greater the number o zeroalued spectral coeicients, and when that measure is equal, to unctions with higher adjacency count. Single ariables and their complements yield the maximum alue o D( ) or a gien n although they are not unique in that regard. 3. SYNTHESIS The synthesis approach presented here is an enhancement to the method presented by the irst author in [13]. In particular, the earlier method deeloped the circuit rom the outputs towards the inputs. Here we deelop the circuit in both directions. 3.1 Output Translation An output translation is the application o a TOFn gate across a set o unctions (outputs). In general, this can be expressed as TOF n ( α, α,...,, ) 2 αn 1 β (1) The single output β is aected. For example, Table 3 shows the application o the output translation TOF 3(, 1, 2) which results in 2 = 1 2. c b a 1 2 c b a (a) (b) Table 3: (a) beore translation (b) ater output translation. This simple translation interchanges two output patterns (emphasized in bold italics). In general, an output translation will interchange blocks o rows. The reersibility o the speciication is clearly presered. The synthesis method in [13] employed only this orm o translation. In our method the translation is perormed directly on the unction spectra. 3.2 Input Translation An input translation is similar but applies to the input side o the speciication. The general orm is TOF nx ( α, x,...,, ) 1 α x x 2 αn 1 β (11) Only input x β is aected. Table 4 illustrates application o the input translation TOF 2( bc, ) resulting in c = c b. c b a 1 2 c b a 1 2 c b a (a) (b) (c) Table 4: (a) beore translation (b) ater input translation (c) ater rearrangement. Table 4 (c) shows the result ater rearranging the input patterns into standard order. From this we see that an input translation in act interchanges blocks o output patterns. In general, as shown, the moement o output patterns resulting rom an input translation cannot be accomplished by an output translation. Also note that an input translation will generally aect more than one output, and oten all outputs, whereas an output translation always aects a single output. Input translations can be carried out directly in the spectral domain but except or TOF1 and TOF2, the operations are rather complex. Our current implementation perorms the translation in the unction domain and then transorms the results to spectra. 3.3 Synthesis Method Gien a reersible logic speciication expressed as a system o Boolean unctions i ( xn,..., x2, x1),1 i n, our method irst transorms each unction to the spectral domain giing the spectra R i,1 i n.. The irst phase o our method is the iteratie application o the ollowing procedure which or each iteration identiies a single generalized Tooli gate and input complementation pattern. The identiied gate corresponds to either an input or an output translation, whicheer is ound to be best in terms o improing the complexity measure D. Computations or output translation are carried out in the spectral domain using the rules in Table 2. Computations or input translations require conersion between the spectral and unctional domains. 3

4 Procedure Input: Spectra R i,1 i n. Output: One generalized Tooli gate and input permutation pattern, and transormed spectra R i,1 i n. Process: (a) Examine the eect o each input translation and select the translation (generalized Tooli gate and input complementation pattern) that results in the maximum positie change in D ( i ) summed across all the output unctions with no negatie change to any D ( i ). In the case o a tie, choose the one with ewest gate inputs and i there is more than one with maximum positie change and the same number o inputs, choose the one with the minimum number o input complementations. I there is still a tie, the irst encountered is arbitrarily chosen. Note that complementation o the ariable aected by a Tooli gate is neer considered. (b) Examine the eect o each aailable output translation and select the translation (generalized Tooli gate and input complementation pattern) that results in the maximum positie change in D ( i ) or the single output unction aected by the translation. Ties are resoled in the same manner as or input translations. Note that output translations are not considered that would aect an output that has already been translated to a single ariable or its complement. Once again, complementation o the ariable aected by the Tooli gate is not considered. (c) I neither (a) or (b) identiies a translation, the procedure terminates in error. Otherwise choose the translation rom (a) or (b) that results in the greatest improement. In the case o a tie, the input translation is chosen. (d) I an output translation is chosen in (c), R j = R j, j i, where i is the output aected by the selected gate. Ri is computed based on the chosen translation directly in the spectral domain. (e) I an input translation is chosen in (c), each o the Ri is transormed to the unctional domain, the unctional speciications are rearranged according to the input translation, and the Ri are then ound by transorming the permuted unctional speciications. The synthesis process is complete when the spectra R i each represent a unique ariable or its complement. At this point we hae an ordered list o possible interleaed input and output translations, each with an associated generalized Tooli gate and input complementation pattern. In the second phase o our procedure, the circuit is produced as an ordered sequence o generalized Tooli gates as ollows: (a) Each output unction that has been translated to the complement o an input ariable requires a TOF1 (NOT) gate as a inal output translation. (b) The output permutation pi,1 i n, is such that xp is i the ariable, or complemented ariable, identiied by R i. (c) The circuit begins with the Tooli gates rom input translations listed in the order they were identiied. (d) The circuits concludes with the Tooli gates rom output translations listed in reerse order to the order in which they were identiied. This set o Tooli gates begins with any TOF1 gates identiied in (a). The ariable labels or the Tooli gates associated with output translations including the TOF1 gates are relabeled according to the permutation identiied in (b). (e) The identiied circuit produces the originally speciied outputs in the permutation order identiied in (b). () As a inal step, Fredkin gates can be inserted by applying (1). Other optimizations can be applied such as inerter reduction. The circuit is produced as a sequence o Tooli gates rom the input side to the output side. O course, applying the sequence in reerse transorms the output side to the input side. The synthesis procedure described here is a signiicant extension to the one described in [13] as it uses input translation as well as output translation. In addition, the procedure has been extended to generalized Tooli gates. The work in [13] considered only up to TOF4 gates. Finally, the procedure described here uses a dierent rule or breaking ties. Preerence is here gien to maximizing the improement in the unction complexity metric whereas in [13] preerence was gien to minimizing the gate width. Experimentation has shown the scheme used here in general yields better results. 4. REVERSIBLE EXAMPLES For each example, the speciication is gien as an ordered set o decimal numbers which deine the truth table speciication o the reersible logic problem to be realized. To illustrate, the speciication or Example 1 deines a Fredkin gate as speciied in Table 5. The circuit is gien as an ordered sequence o reersible gates. Read rom let to right they transorm the let side o the speciication to the right side. The output permutation is not noted i it is the identity. Example 1: Veriication o realizing a Fredkin gate using two Feynman gates and a Tooli gate. Speciication: [,1,2,3,4,6,5,7] (corresponds to Table 5) Circuit: TOF2(b,a) TOF3(c,a,b) TOF2(b,a) 4

5 c b a c b a Table 5 Fredkin Gate Speciication. Example 2: This is a second example o the interchange o two positions in the speciication. Note the analogous structure to that o the Fredkin gate realization the right pair o TOF2 gates can be reersed to better show the expected symmetry. The circuit gien by our method is identical to a solution proided by Perkowski [16]. Speciication: [,1,2,4,3,5,6,7] Circuit: TOF2(c,b) TOF2(c,a) TOF3(b,a,c) TOF2(c,b) TOF2(c,a) Example 3: The our input extension o Example 2. The right three TOF2 gates can be permuted to better show the symmetry. Speciication: [,1,2,3,4,5,6,8,7,9,1,11,12,13,14,15] Circuit: TOF2(d,c) TOF2(d,b) TOF2(d,a) TOF4(c,b,a,d) TOF2(d,c) TOF2(d,b) TOF2(d,a) Example 4: This is increment mod 2 n or n = 3. Speciication: [1,2,3,4,5,6,7,] Circuit: TOF3(b,a,c) TOF2(a,b) TOF1(a) Example 5: This is the 4 input extension o Example 4. Note the generalization to the structure o the solution or the n = 3 case. The structure generalizes in the same manner or higher alues o n. Speciication: [1,2,3,4,5,6,7,8,9,1,11,12,13,14,15,] Circuit: TOF4(c,b,a,d) TOF3(b,a,c) TOF2(a,b) TOF1(a) Example 6: This example is taken rom [17]. Speciication: [3,11,2,1,,7,1,6,15,8,14,9,13,5,12,4] Circuit: TOF1(c) TOF1(b) TOF2(a,d) TOF2(c,d) TOF3(a',d,c) TOF2(c,d) TOF2(c,a) TOF3(a',d',b) The three underlined gates in the aboe solution can be replaced with the single Fredkin gate FRE(a',c,d). The outputs o the circuit are the permuted order (c,a,d,b). Note that (d,c,b,a) is the standard unpermuted order. The solution is comparable to the solution gien in [17]. Example 7: This is the inerse to the speciication in Example 6. This shows the importance o applying our synthesis method to both a speciication and the corresponding inerse (except when the speciication is sel-inerse) and choosing the better o the results. Speciication: [4,6,2,,15,13,7,5,9,11,3,1,14,12,1,8] Circuit: TOF3(c',b',a) TOF2(c,b) TOF2(c,d) TOF1(b) TOF1(a) TOF3(b,d,c) TOF2(c,b) In this case, the output permutation is (c,b,a,d). Comparing the solution or Examples 6 and 7 shows the importance o applying the synthesis method to a problem and its inerse. The resulting circuit can be quite dierent. One can o course choose between the solution to a problem or its inerse, since reading a solution in reerse gies a circuit or the inerse problem due to the reersibility o the gates. For example, reading the solution or example 6 rom right to let is a solution or Example 7, and reading the solution or Example 7 rom right to let is a solution or Example IRREVERSIBLE EXAMPLES An arbitrary combinational circuit composed o irreersible gates can be mapped to a reersible circuit typically with the addition o some number o constant inputs and garbage outputs [14]. Here our interest is to synthesize a reersible circuit rom an irreersible speciication and not the transormation o a irreersible circuit to a reersible one. To apply our synthesis method, an irreersible speciication must irst be transormed to a reersible one. We assume the gien speciication is totallyspeciied. 5.1 Single-Output Functions A single-output unction inoling input ariables x1, x2,..., xn is transormed to a speciication with n 1 inputs and n 1 outputs by: i) adding a new input ariable x n 1, ii) replacing the output by x n 1, iii) adding n outputs each equal to one o the original inputs x1, x2,..., x n. It is easily eriied that the speciication constructed in this way assigns a unique output pattern to each input pattern and is thereore reersible. By setting x n 1 = on input, the original output is realized. Example 8: This procedure or transorming a single-output unction is illustrated or the simple example o the 2-input AND unction in Table 6. The resulting circuit is the single gate TOF3(b,a,c) which realizes the AND o a and b when c is on input. b a c b a c b a (a) (b) Table 6: (a) 2-input AND (b) reersible speciication deried rom 2-input AND. 5

6 Example 9: The two o ie checker unction has ie inputs and a single output which is 1 i, and only i, two o the inputs are 1. Transorming this unction to a reersible speciication as described aboe and then applying our synthesis procedure yields the circuit: TOF3(b',a',) TOF4(d',c',a,) TOF4(e',c',b',) TOF6(e,d',c',b,a,) TOF6(e',d',c,b',a,) TOF6(e',d,c',b,a',) TOF6(e,d,c,b',a',) TOF5(e',d',c,a',) TOF5(e,d',c',a',) with output permutation (,e,d,c,b,a). Variable is the desired output and should be set to on input. This solution uses two more Tooli gates than the solution ound by Dueck and Maslo [3]. Their algorithm uses exhaustie ealuation at each stage including two-step look-ahead to choose the best generalized Tooli gate. Example 1: To illustrate this process is equally eectie or a non-symmetric unction, consider the 5-input, single output unction which is 1 or the ie input patterns e'd'c'b'a, e'd'c'ba, e'd'cba, e'dcba and edcba. Our approach identiies the simple circuit TOF6(e,d,c,b,a,) TOF5(e',c,b,a,) TOF5(e',d',c',a,) where again ariable is the desired output and should be set to on input. 5.2 Multiple-Output Functions The approach described aboe or an extension to it is applied or multiple-output unctions. In this case, the number o outputs to be added is at least log2 m where m is the maximum number o times a single output pattern appears in the gien speciication [11]. Additional outputs and also additional inputs may be required to ensure the deried speciication has the same number o inputs and outputs, a requirement or it to be reersible. The transormation o the gien speciication must be done in such a way as to yield a reersible speciication without introducing undue complexity. Example 11: Table 7 is a reersible speciication deried rom a ull adder speciication shown in bold italics. Two outputs must be added, as the output patterns 1 and 1 each appear 3 times in the speciication o the ull adder. The resulting circuit is TOF2(b,c) TOF2(a,c) TOF1(d) TOF2(c,d) TOF4(c',b',a',d) TOF4(c,b,a,d) which can be simpliied by replacing TOF1(d) TOF2(c,d) by TOF2(c',d). Applying our synthesis method to the inerse o the speciication in Table 7, yields the similar complexity circuit: TOF2(b,c) TOF2(a,c) TOF2(c,d) TOF4(c,b',a',d) TOF4(c',b,a,d) d c b a d c b a Table 7: Reersible speciication deried rom the ull adder (bold italics). The simpler circuit TOF2(b,a) TOF2(a,c) TOF3(c,a,d) TOF3(b',a',d) TOF1(d) is ound by changing the speciication in Table 7 so that a = a b. This deinition or a is taking into account that a b is a useul subunction in the realization o the sum and carry unctions o the ull adder. Knowledge o the decomposition structure o the target unctions is o considerable beneit in choosing a reersible speciication. Applying our synthesis approach to the inerse o the latter speciication yields: TOF2(a,c) TOF2(b,a) TOF2(c,d) TOF4(c,b',a',d) TOF4(c',b,a,d) which is more complex. This latter circuit is interesting to compare to the circuit ound rom considering the inerse o the original speciication in Table 7. Example 11: As a inal example we consider the benchmark unction RD53. This unction has 5 inputs and 3 outputs. The outputs are the binary encoding o the weight o the input pattern i.e. the number o 1's in the input pattern. For example, input yields output, input 1 yields output 1 and input yields output 11. The maximum output pattern multiplicity is 1 so at least 4 garbage outputs must be added giing a total o at least 7 outputs. That in turn requires two inputs be added. We thus hae a speciication with inputs gedcba,,,,,, and outputs g,, e, d, c, b, a where edcbaare,,,, the original inputs. Let h 2, h 1, h be the original outputs with h 2 the most signiicant bit o the binary representation o the weight. A reersible speciication can be deried using the principles outlined aboe by setting g = h2 g, = h1, e = h, (12) d = e, c = d, b = c, a = b. 6

7 Setting g = = yields the desired outputs. Applying our synthesis method to this speciication yields the circuit TOF4(e,b,a,g) TOF2(e,a) TOF2(d,a) TOF2(c,a) TOF2(b,a) TOF1() TOF6(a,e',d',c',b,) TOF6(a',e,d,c',b', TOF5(a,e',d',b',) TOF4(a',e,d,) TOF2(a,) TOF6(a',e,d',c,b,) TOF6(a,e',d,c',b',) TOF6(a',e',d,c,b,) TOF6(a,e,d',c',b',) TOF2(a,) TOF6(a',e',d',c',b',) TOF6(a,e,d,c,b, TOF6(a',e',d,c,b,g) TOF6(a,e,d',c',b,g) TOF5(a',e,d,c,g) with output permutation (g,,a,e,d,c,b). The underlined TOF1 gate can be remoed by replacing the underlined TOF2 gate by TOF2(a',). The sequence TOF2(e,a) TOF2(d,a) TOF2(c,a) TOF2(b,a) in the aboe circuit is an indication that parity plays an important role in RD53. Changing the speciication in (12) so that d = e d c b and applying our synthesis procedure yields a circuit with 15 generalized Tooli gates. That circuit shows some urther parity dependency. This led us to consider the ollowing reersible speciication: g = h2 g, = h1, e = h, d = e d c b, c = d c b, (13) b = c b, a = b. Applying our synthesis algorithm yields the circuit TOF5(e,d,c,a,g) TOF2(b,c) TOF2(c,d) TOF2(d,e) TOF2(e,a) TOF3(e,a,) TOF3(c',b,) TOF3(d',c,) TOF3(e',d',) TOF1() TOF5(a',e,d',b,g) TOF5(a',d,c',b,g) with output permutation (g,,a,e,d,c,b). This circuit requires 12 Tooli gates as opposed to 2 or the initial reersible speciication. Far ewer input complementations are needed and the width o the required gates is greatly reduced. Note that the TOF1 gate can be remoed by complementing in (13). This assumes a constant 1 can be used as an input in the inal circuit implementation. The circuit ound by our method in that case uses 11 Tooli gates, whereas the method in [3] requires 13 Tooli gates with higher input counts. This example clearly shows the beneit o taking properties o the target unctions and an initial circuit realization into account when constructing and reining the reersible speciication. 6. CONCLUSION Results to date show the spectral-based synthesis method does indeed hae promise. We are currently deeloping a ormal proo that the method will terminate giing a circuit or any completely-speciied reersible speciication. The preliminary implementation o our synthesis method is in C and represents unctions and their spectra as ectors o length 2 n although ast transorm methods [6][18] are used in the implementation rather than the matrix transormation method. Execution time on a 75 MHz PC is reasonable or the examples shown, about 3 minutes or RD53. A decision diagram implementation is under deelopment so the method can be applied to larger problems. Preliminary work has shown that input and output translations can be carried out directly on unctional or spectral decision diagrams. In particular, input translations can be perormed as local translations on a decision diagram proided the ariables inoled are adjacent. While our synthesis method does not require extensie lookahead or back-tracking techniques, it does require the ull consideration o the possible Tooli gates and input complementation patterns at each stage o the synthesis. We are currently inestigating spectral criteria to reduce this searching. Lastly, we are examining how to ormalize the transormation o a nonreersible speciication to a reersible one. In particular, we are examining how spectral criteria that may aid this process. REFERENCES [1] Bennett, C., Logical Reersibility o Computation, IBM Jour. o Research and Deelopment, 17, 1973, pp [2] De Vos, A., Towards Reersible Digital Computers, Proc. European Con. Circuit Theory & Design, 1997, pp [3] Dueck, G. W., and D. Maslo, Reersible Function Synthesis with Minimum Garbage Outputs, submitted to RM-23. [4] Feynman, R., Quantum Mechanical Computers, Optics News,11, 1985, pp [5] Fredkin, E., and T. Tooli, Conseratie Logic, International Jour. Theoretical Physics, 1982, pp [6] Hurst, S. L., D. M. Miller, and J. C. Muzio, Spectral Techniques in Digital Logic, Academic Press, [7] Karposky, M. G., Finite Orthogonal Series in the Design o Digital Deices, John Wiley and Sons, [8] Kerntop, P., On Eiciency o Reersible Logic (3,3) Gates, Proc. 7th Intl. Con. MIXDES, 2, pp [9] Landauer, R., Irreersibility and Heat Generation in the Computational Process, IBM Journal o Research and Deelopment, 5, 1961, pp [1] Margolus, N., Physics and Computation, Ph. D. Thesis, Massachusetts Institute o Technology, [11] Maslo, D., and G. W. Dueck, Garbage in Reersible Designs o Multiple-Output Functions, submitted to RM-23. [12] Milburn, Gerard J., The Feynman Processor, Perseus Books, [13] Miller, D. M., Spectral and Two-Place Decomposition Techniques in Reersible Logic, Proc. Midwest Symposium on Circuits and Systems, on CD-ROM, August 22. [14] Nielsen, M. A., and I. L. Chuang, Quantum Computation and Quantum Inormation, Cambridge Uni. Press, 2. [15] Peres, A., Reersible Logic and Quantum Computers, Physical Reiew A, 32, 1985, pp [16] Perkowski, M. Priate communication. [17] Perkowski, M., et al., A General Decomposition or Reersible Logic, Proc. Fith Reed-Muller Workshop, 21, pp [18] Thornton, M. A., R. Drechsler and D. M. Miller, Spectral Techniques in VLSI CAD, Kluwer, 22. [19] Tooli, T., Reersible Computing, in Automata, Languages and Programming, Springer-Verlag, pp , 198. Acknowledgements: This work was supported in part by research grants rom the Natural Sciences and Engineering Research Council o Canada. This work was completed while the irst author was on sabbatical at the Uniersity o New Brunswick. 7