Unified Architecture Level Energy-Efficiency Metric

Transcription

1 Uniied Architecture Leel nergy-iciency Metric Victor Zyuban BM Research Diision, T.J. Watson Research Center, Yorktown Heights, Y zyuban@us.ibm.com ABSTRACT The deelopment o power-eicient microprocessors presents the need to consider power consumption at early stages o design, particularly at the SA and microarchitecture deinition stages, where the potential or power saings is more signiicant than at lowerleel stages, and the opportunity or making power-perormance tradeos is the largest. Design modiications to the SA and microarchitecture, howeer, aect most (i not all) parameters o the design, including architectural speed, code density, clocking rate and power. A reliable metric is required to make knowledgeable power-perormance tradeos in this multi-dimensional space. This paper deries a uniied energy-eiciency metric or ealuating SA and microarchitecture eatures, which subsumes other commonly used power-perormance metrics as special cases o a more general equation. This new metric is deried based on an analysis o a multi-dimensional power optimization problem, and the resulting ormula inoles only relatie changes in the characteristics o a processor, enabling its application at the early stages o the design. Categories and Subject Descriptors C.1.0 [Processor Architectures]: General; C.5.3 [Microcomputers]: Microprocessors; B.7.1 [Types and Design Styles]: Microprocessors and microcomputers,vls; C.0 [General]: Modeling o computer architecture; C.1.3 [Other Architecture Styles]: Pipeline processors General Terms Design, Perormance Keywords nergy, power, perormance, energy-eiciency, metric, architecture, microarchitecture 1. TRODUCTO The opportunity or power-perormance tradeos is the largest at the early stages o microprocessor deelopment, particularly at Permission to make digital or hard copies o all or part o this work or personal or classroom use is granted without ee proided that copies are not made or distributed or proit or commercial adantage and that copies bear this notice and the ull citation on the irst page. To copy otherwise, to republish, to post on serers or to redistribute to lists, requires prior speciic permission and/or a ee. GLSVLS 0, April 18-19, 00, ew York, ew York, USA Copyright 00 ACM /0/ $5.00. the instruction set and microarchitecture deinition stages. At this leel, een minor modiications to the design may result in signiicant changes to the power-perormance characteristics o the processor. To draw a conclusion about the eectieness o some existing or proposed architectural eature, one needs to ealuate its eect on the architectural speed o the processor (PC), its power, maximum clocking rate and cost. Certain architectural eatures that improe the architectural speed, may be ery costly in terms o power dissipation, whereas others may impact the clocking rate. A proper power-perormance metric is needed to combine all these eects. n order to be useul at early design phases, such a powerperormance metric has to deal with relatie changes in the architectural perormance o the processors, such as PC and dynamic instruction count, and physical characteristics, such as the clocking rate and power dissipation. an architectural eature under ealuation improes the power-perormance metric, it is considered energy-eicient according to this metric; that is, it results in a better design point in the power-perormance optimization space. A number o power-perormance metrics hae been proposed [5, 7, 6,, 11, 1, 9, 3, 8], and some o them hae been used to compare dierent products on the market. The MPS per Watt metric, which can be reduced to the reerse o energy-per-operation [4], has been used or comparing low-end products. t has also been used as a power perormance metric in the ixed throughput mode [4]. This paper shows that, depending on certain actors, metric MPS per Watt may or may not lead to a power-optimized design or the ixed throughput mode. Furthermore, we show in section.1.1 that MPS per Watt is a special case o a more general ormula, deried in this work, that coers both the ixed throughput and ixed power modes. Sometimes the MPS per Watt metric is also used or analyzing high perormance processors, when such a processor cannot be set to operate at its ull speed because its power exceeds the powerdissipating capabilities o the package. n this case, howeer, the power-perormance metric can be more accurately expressed as MPS at maximum power which is substantially dierent rom MPS per Watt, as will be shown in Section.1. o this paper. The energy-delay product, whose inerse can be reduced to the MPS square per Watt, is a more reasonable metric [7] or comparing a midrange class o microprocessors. Formulas placing more emphasis on perormance by raising the exponent o MPS hae also been used or comparing high-end serer microprocessors; metric MPS 3 Watt is an example o this []. All the metrics mentioned aboe are diicult to use or ealuating the energy eiciency o architectural eatures at early stages o design, or two reasons. First, absolute power and perormance data are typically unaailable. Second, it is hard to reach an agree-

2 ment between architects and circuit designers on the appropriate alue o γ in the power-perormance ormula MPS γ Watt [13]. n this paper, we derie a new metric that combines relatie changes in the architectural speed, dynamic instruction count, aerage energy dissipated per executed instruction, and maximum clocking rate o the processor, resulting rom design modiications at the architectural and microarchitectural leels. This metric will allow designer to ealuate the energy-eiciency o architectural eatures beore making them part o the design, and to compare architectural alternaties in the power-perormance design space. The organization o the paper is as ollows: Sections deries the energy-eiciency metric or three types o processor implementations: ideal clock gating, ree running clock, and partial clock gating. Section 3 considers the eect o technology characteristics and circuit style on the deried metric. Section 4 gies examples o applying the metric to ealuate the energy eiciency o some architectural eatures. Section 5 discusses the limitations o the deried metric and summarizes the paper.. POWR-PRFORMAC OPTMZATO Consider the problem o optimizing the power-perormance characteristics o a processor in the space o two ariables: architectural complexity and power supply oltage. To allow a mathematical analysis o the problem, we introduce a discrete ariable ξ that represents a measure o the architectural complexity o a processor. The domain o this ariable can be deined by ordering all possible architectural alternaties, and assigning a numeric alue to each o them. Then, any architectural modiication to the processor results in an increment or decrement in the alue o ξ. xamples o ariations in architectural complexity include the addition o instructions to the SA, modiying the deinitions o existing instructions, or, at the microarchitecture leel, changing the pipeline latency, adding or remoing hardware unctionality such as bypasses, unctional unit, access read or write ports to arious structures, changing the width o the datapath, and so on. We will treat the architectural complexity as an independent ariable in the optimization process. Power supply oltage will be treated as the second independent ariable in the optimization process, based on the assumption that, to achiee the desired power and perormance characteristics, the power supply oltage can be set to any alue rom the range or which the technology is qualiied. Then, the perormance and power characteristics o a processor can be iewed as unctions o the independent ariables ξ and, where is a continuous and ξ is a discrete ariable: dynamic instruction count = (ξ) architectural speed (PC) = (ξ) maximum clocking rate = (ξ;) energy per istruction = (ξ;) (1) n these and all ollowing ormulas, is the total number o dynamic instructions executed on a gien benchmark suite; is the aerage number o instructions completed per clock cycle by the processor, calculated on the same benchmark suite; is the aerage energy per instruction, calculated as = i w i i,where i is the aerage energy dissipated on the execution o instruction i rom the instruction set, and w i is the normalized dynamic requency o the corresponding instructions in the benchmark suite. To a irst approximation, and depend only on the architectural complexity ξ, and are independent o the supply oltage. The clocking rate,, and the aerage energy per instruction,, depend both on the architectural complexity ξ and the supply oltage. Then, the processor perormance P on the gien benchmark suite can be expressed as ollows: P(ξ;)= (ξ;)(ξ) : () (ξ) The expression or power dissipation W(ξ;) depends upon the implementation details o the processor. We will consider two extreme cases: ideal clock gating and ree-running clock implementations, and a more realistic case o partial clock gating..1 deal Clock Gating Under an ideal clock gating model, the only resources that dissipate power are those accessed by executed instructions, and all unused hardware is gated-o, using the inest-grain clock gating mechanism or some sort o transition barrier mechanism 1,ora combination o both. n this case, the aerage power is directly proportional to the aerage number o instructions executed per cycle and the aerage energy dissipated per completed instruction: W(ξ;)= (ξ;)(ξ)(ξ;); (3) wherein is the aerage energy per executed instruction, as deined aboe. otice that i expression 3 is applied to a speculatie issue processor, then the energy dissipated by instructions rom mispredicted paths that are etched, and possibly executed but not committed, has to be included in..1.1 Constant-Perormance Optimization n this subsection we consider the problem o minimizing the aerage power dissipation, gien a perormance requirement, P = const. The designer is allowed to modiy the architecture (both SA and microarchitecture) and adjust the clocking rate o the processor, by changing the power supply oltage within certain limits, to satisy the perormance requirement at minimum power dissipation. This sort o optimization problem is typical or the design o low-power microprocessors, application speciic, real time processors and DSPs. n mathematical terms, the problem o power minimization can be reduced to the problem o minimizing the unction W(ξ;) inthespace o twodesignariables ξ and, under the constraint P(ξ;)=const. we use inite dierence notation or the discrete ariable ξ, 4F(ξ;) = F(ξ+;), F(ξ;) ; (4) wherein F(ξ;) is any unction o ariables ξ and, inoled in the analysis, and neglect the second-order terms, then the constraint condition can be expressed in dierential orm as 4P + P 4 = 0; (5) where 4 is the adjustment in the supply oltage needed to compensate or perormance loss or gain, resulting rom the architectural modiication. Here, and in the remainder o the paper, we neglect the secondorder terms o the orm F (4) and 4 F 4,whereF is any unction inoled in the analysis, such as W, P,,,. Thus, all ormulas and conclusions in this section are only alid or small 1 Transition barriers are placed beore unctional units (FU) to preent switching in unused FUs, or portions o FUs without the oerhead o duplicating the operand latches.

3 ariations to the architecture, such that the resulting relatie increments in all inoled unctions, and in their deriaties, are small ( 4F F 1, 4F 0 F 1) and relatie changes in the supply oltage, 0, needed to compensate or the perormance loss or gain, resulting rom architectural modiications, are also small, ( 4 1). mplications arising rom these assumptions are considered in section 5. Under the aboe assumptions, the problem o establishing the energy eiciency o a particular modiication to the architecture, can be reduced to that o inding a relation between relatie changes in processor characteristics in (1) or which = P=const + W 4 < 0: (6) P=const Using () and (3) and the assumptions stated aboe, we can calculate the inite dierences and partial deriaties in the constraint ormula (5) as ollows: 4P = 4 + P = 4, 4 ; (7) = ; (8) where is the dimensionless partial deriatie o the maximum clocking rate with respect to the supply oltage, = : (9) The alue o can be estimated empirically or a selected technology, supply oltage and the selected circuit style. To ealuate it, the designer can simulate the dependence o the delay through the hardware blocks that are expected to be on the critical path upon the supply oltage. xamples o the ealuation o are considered in the next section. Substituting expressions (7) and (8) into the constraint condition (5), we arrie at the ollowing expression or the ratio o inite dierences 4 and subject to the constraint P(ξ;)=const: 4 =, 4 P=const, : (10) The remaining terms in the energy-eiciency ormula (6) are calculated as ollows: = ; (11) W = ( + ); (1) where is the dimensionless partial deriatie o the aerage energy dissipated per instruction with respect to the supply oltage, = : (13) The alue o or CMOS circuits is typically close to, since the energy o the charged capacitance is proportional to the square o the supply oltage, = CV. A more accurate estimate or the alue o or a selected technology and circuit style can be obtained by simulating representatie circuits oer a range o supply oltages. xamples o the ealuation o are gien in the next section. Substituting (11), (1) and (10) into (6), and grouping terms in ront o the partial deriaties, we arrie at the ollowing criterion or energy eiciency:, 4, < 0 (14) The increments o all quantities in (14) appear in relatie orm and, thus are dimensionless. This eature makes this ormula easy to use as a negotiation basis between architects and circuit designers. For example, i = =, then i some microarchitectural enhancement (say adding a bypass) increases the aerage energy per instruction by 5%, and potentially increases the delay on the critical path by %, without any eect on the dynamic instruction count, then it will be energy eicient only i the resulting increase in the architectural speed is at least 7%. More examples on using the deried energy eiciency criterion are gien in Section 4. For some combinations o the alues o and, the deried energy-eiciency criterion can be iewed upon as a dierential orm o one o the conentional power-perormance metrics. For example, i = and = 1, then (14) is reduced to, 4, < 0; (15) which is a dierential orm o the well-known MPS-cube per Watt ormula, S = P 3 = W, assuming relations () and (3) or 3 perormance and power hold true. ndeed, according to the MPScube per Watt metric, processor A with the MPS-cube per Watt rating S = S A is considered a better design point than processor B with the MPS-cube per Watt rating S = S B i and only i S A, S B > 0. we denote 4 = A, B, 4 = A, B, 4 = A, B,and4 = A, B, then the inequality can be re-written as 1+ 4 B 1+ 4 B B > B B (16) all 4 s are suiciently small, then the aboe expression is equialent to (15) to the accuracy o the second-order terms. Similarly, i = and =, then the energy-eiciency criterion (14) is reduced to, 4, < 0; (17) which, in a similar way, can be shown to be equialent to the dierential orm o the MPS-square per Watt metric, proided that all assumptions stated earlier hold. Finally, i, (14) is reduced to < 0; (18) which, under the same assumptions, is equialent to the dierential orm o the MPS per Watt metric. Thereore, the MPS per Watt metric that is commonly used or power analysis under the ixed throughput mode [4] leads to an energy-optimized design only i. Thus, the MPS per Watt, MPS-square per Watt, MPScube per Watt, and other similar MPS to the power o γ per Watt metrics are special cases o the energy-eiciency criterion, deried in this paper. Adantages o the new metric are its generality and the ability to calculate the parameter γ or eery particular case, taking into account technology and circuit characteristics..1. Constant-Power Optimization The energy-eiciency ormula (14) appears to be also alid or the reerse problem o perormance maximization, subject to the

4 constant power constraint, W = const. To show this, let us assume that, similarly to the preious case, the designer is allowed to change both the architectural complexity ξ and the power supply oltage to achiee the maximum perormance, while keeping the aerage power at the required leel. This optimization goal is typical o the high-perormance microprocessor design targeted at achieing the highest perormance, without exceeding the power budget set by packaging. To achiee this goal, the designer needs to ealuate i a particular modiication to the architecture will result in higher perormance, assuming that the clocking rate will be adjusted to meet the power budget and the power supply oltage will be adjusted accordingly, to enable the processor hardware to operate at the desired clocking rate. Then, the optimization problem can be ormulated in mathematical terms as the problem o maximizing the unction P(ξ;) in the space o two design ariables ξ and, under the constraint W(ξ;)=const which, under the assumptions stated earlier, can be expressed in the inite dierence orm as + W 4 = 0: (19) Determining the energy eiciency o a particular modiication to the architecture can then be reduced to inding a condition or which 4P = 4P W=const + P 4 > 0: (0) W=const Substituting (11) and (1) into (19), we derie the ollowing expression or the ratio o inite dierences 4 and, under the constraint (19): 4 =, 1 4 W=const : (1) Substituting (7) and (8) into the energy-eiciency equation (0), we arrie at (14). Thus, the energy-eiciency criterion (14) is also alid or the alternatie ormulation o the power-perormance optimization problem, where the goal is to maximize perormance without exceeding the power budget. Thereore, metric (14) should be used (instead o MPS per Watt ) or optimizing high perormance clock gated processors, when such a processor cannot be set to operate at its ull speed because o the power constraint. The next subsection deries an energy-eiciency metric or processors that do not use any clock gating.. Worst-Case Power Analysis The energy-eiciency criterion (14) deals with the aerage power o a processor, assuming that the aerage power is proportional to the weighted aerage number o instructions executed per cycle. n this subsection we derie a special ersion o the energy-eiciency criterion tailored or processors that do not use any clock gating. The power-perormance optimization analysis in this special case ollows the same path as in case o ideal clock gating. The expression or the aerage power in the absence o clock gating is written as W(ξ;)= (ξ;)(ξ;); () where is the aerage energy dissipated per cycle. The expression or perormance () holds. Consequently, we only need to re-write ormulas inoling the power term, (11) and (1), as ollows: = ; (3) W = ( + ): (4) Repeating the analysis or the constant-perormance power optimization in subsection.1.1, we arrie at the ollowing energyeiciency criterion:, 4, < 0: (5) t is easy to eriy that, or the ree-running clock implementation, the constant-power optimization, described in subsection.1., leads to the same ormula (5). Compared to the corresponding expression or the ideal clock gating implementation (14), ormula (5) has a larger weight in ront o the term 4. This is a consequence o the assumption that the aerage power is independent o the number o instructions executed per cycle. otice that expression (5) also holds or the worst-case power analysis in clock-gated microprocessors, i is interpreted as worstcase energy dissipated per cycle. Thereore, i a processor is constrained by the worst-case sustained power that may be dissipated during the execution o a loop o power-intensie instructions with high degree o LP, combined with high switching actors in the data bits, then metric (5) should be used or both clock-gated and non-gated implementations o the processor. t is easy to show, ollowing the reasoning in the preious subsection, that the MPS per Watt, MPS-square per Watt, MPScube per Watt, and other MPS-to-the-power-o-γ per Watt metrics are special cases o the energy-eiciency criterion (5), written in the integral orm. For example, = ; = 1leadsto MPScube per Watt ; = ; = leads to MPS-square per Watt ; leads to MPS per Watt, while = ; = 0:5 leads to MPS-power-5 per Watt..3 Partial Clock Gating n the design o real processors, clock gating may be applied to only some portion o the processor resources, or the granularity o clock gating may be coarser than assumed in subsection.1. Then, a linear combination o the energy-eiciency criteria (14) and (5), deried under the assumptions o the ideal clock gating and zero clock gating, leads to:, 1 4 F + 1,, κ < 0; (6) where κ is the power-weighted portion o hardware coered by the clock gating, 0 < κ < FFCT OF CRCUT AD TCHOLOGY CHARACTRSTCS The proposed energy-eiciency metric is dependent on the characteristics o technology and circuits, through the parameters and, deined in (9) and (13). As shown in the preious section, dierent combinations o alues o and may lead to dierent conclusions about the eectieness o the same architectural eatures. Theoretical ormulas could be used to determine and.alternatiely, a more practical way to calculate the alues o these coeicients is to simulate representatie circuits oer a range o power supply oltages. For the ealuation o, it is important to select

5 unctional block that can potentially be on the critical path, on the other hand, or the ealuation o the most signiicant power consumers should be simulated. As an illustration, a representatie set o blocks in a typical microprocessor was selected, including an inter-unit star-connect data bus; a synthesized ASC 3-bit integer adder; a ull-custom 16-bit multiplier; the critical read path o the 4read/4write - port ull custom register ile (just simulation), described in [1]; and a read - write 16-entry semi-custom register ile built o latches and multiplexors, all implemented in a 0.13um technology. For the energy analysis, all blocks were simulated with PowerMill, applying random patterns to the inputs with a switching actor o 0.3, or 00 to 500 cycles (depending on the size o the circuit). A clocking rate o 100MHz was used in power simulations or all alues o Vdd. PathMill static timer was used or delay analysis. All deriaties were calculated by the 3-point ormula. = (*ddelay)/(delay*d) data bus integer adder multiplier (custom) 4r/4w port reg ile r/w port reg ile aerage supply oltage, V = ( d)/( d) data bus integer adder multiplier (custom) 4r/4w port reg ile aerage CV cure supply oltage, V Figure 1: Simulation results or =. Fig 1 shows simulation results or. The cures on the graph correspond to the blocks described aboe. A cure, corresponding to the = CV dependence is also plotted, as a reerence. Fig. 1 shows that, or all the blocks, the alue o is higher than the alue o two that corresponds to the = CV dependence. This super-vdd-square dependence o energy on the supply oltage is partially explained by short circuit power which grows aster than the square o [10], and higher glitching actiity at higher supply oltages. Those blocks that hae more signiicant glitching actors also demonstrate higher alues o, especially at high supply oltages. Detailed discussions o the actors aecting the dependence o on are beyond the scope o this paper. Fig shows simulation results or. The cures on the graph correspond to the preiously described blocks. For all blocks, increases rapidly or low alues o Vdd, especially as Vdd approaches the transistor threshold oltage. For high alues o Vdd, drops below unity because o the elocity saturation eect. For customdesigned blocks, tends to be smaller than or ASC-synthesized blocks, especially at low alues o Vdd, because o the (selectie) use o low-threshold deices in custom circuits, and low-oltage circuit styles (e.g. smaller transistor stacks). The thick lines on the graphs, marked with circles, represent the aerages oer all simulated blocks, calculated or unity weight actors. For the analysis o a real microprocessor, and o dierent blocks should be aeraged with appropriate weights. Figure : Simulation results or =. 4. XAMPL OF USG TH RGY-FFCCY CRTRO n practice, a simpliied orm o equations (14), (5) and (6) can be used or comparing architectural alternaties, where s are omitted rom the ormulas. Then, or example, (14) is reduced to:, 4, < 0: (7) t is important to note that, or calculating the inite increments 4 and 4, the meaning o partial deriaties with respect to the architectural complexity be presered, as deined in (4). Particularly, the designer needs to assume a ixed supply oltage when calculating the increments in those quantities. To illustrate the practical use o the energy eiciency criterion, let us consider examples o two hypothetical microprocessors: lowpower microprocessor A that uses the ine-grain clock gating, coering close to 100% o the hardware, and high perormance dynamicissue microprocessor B that does not use any clock gating. Assume that microprocessors A and B are targeted to operate at Vdd=1:0V, and 1:7V, respectiely. Then, by looking at the cures or the aerage and in Fig. and Fig. 1, we determine that = 1:7, = :1 or processor A, and = 0:75, = :31 or processor B. As a irst example, let us ealuate the energy eiciency o the execution bypass o the register ile in processor A. Suppose that architectural-leel simulation results show that, on a gien set o = 1:6%. Since adding the bypass does not aect the 4 = 0. Substituting these alues, and the alues o and, estimated aboe, into (14) or (7), we get (, 4, 4PC )+ 4 = 1:3(0:05,0:07)+0:016 < 0. The energy-eiciency criterion indicates that or the stated assumptions, adding the bypass improes the energy eiciency o proces- benchmarks, the increase in the architectural speed (PC) resulting rom adding the bypass is 4 = 7%. Moreoer, suppose that hardware analysis reeals that the critical path delay increases by 5%, 4 =,5%, because the register ile read access happens to be on the critical path, and the aerage energy dissipated by instructions that read the register ile increases % because o the bypass. 80% o dynamic instructions read operands rom the register ile, then the aerage energy dissipated by an executed instruction increases 4 dynamic instruction count,

6 sor A. otice, howeer, that the same eature would not be energyeicient i processor A were targeted to operate at Vdd = 0:7V or lower. As a second example, consider a proposal to add one extra read port to the multiported integer register ile in processor B, which will remoe some restrictions on the issue o store instructions in parallel with arithmetic instructions. Suppose that simulations showed that this eature would improe the architectural perormance by 0:5%. Assume that the register ile access in not on the critical path, so that adding an extra read port does not impact the clocking rate. Assume also that the increase in the power dissipated in the register ile (which is not clock gated) is 10%, and the integer register ile is responsible or 15% o the total CPU power. Then, the increase in the aerage energy dissipated per cycle is 4 = 1:5%. Substituting these alues, and the alues or and, estimated aboe, into (5), we get, ( + ) =,4:080:005+0:015 < 0. Thus, according to the energy-eiciency criterion or microprocessors without clock gating, adding an extra read port improes the energy eiciency o processor B. Thesame eature, howeer, would not be energy-eicient i processor B were targeted to operate at Vdd= 1:V,orbelow. These examples demonstrate the useulness and conenience o the proposed energy-eiciency metric. n both examples, the relatie changes in the characteristics o the processors were small, so that the assumptions, or which the ormulas were deried, were satisied. 5. COCLUSOS A new architectural-leel energy-eiciency metric was deried that subsumes other commonly used power-perormance metrics as special cases o a more general equation. An adantage o the deried metric is that it takes into account the characteristics o circuits and technology to draw a conclusion about the energy eiciency o an architectural eature. n spite o being ery general, the new ormula is easy to use because it only inoles relatie changes in the characteristics o the processor, which can be ealuated een at early stages o the processor deelopment. For those who eel more comortable using the integral metric o the orm MPS γ Watt, this work proides a consistent and reliable method or calculating parameter γ, γ = +. xamples hae been proided that illustrate the application o the proposed metric to a low-end and a high-perormance processors. For the alidity o the deried ormulas, the relatie dierences in the processor characteristics, corresponding to architectural alternaties under ealuation must be small, a 10% limit can be used or most practical purposes. Special care is needed, i the criterion is to be used to ealuate the energy eiciency o architectural eatures that result in signiicant changes in processor characteristics, such as increasing the issue width, or changing the width o data. Also, the conclusion may be misleading, i the ormulas are used to compare dierent products on the market, especially those built in dierent technologies. Another limitation o the deried criterion is that it does not consider other important actors, such as the code size, ease o programming, or compilability o an architecture. Also, in order to be useul or uture technologies, the ormulas need to be extended to take into account the leakage power. These are among the targets o our current and uture work. Acknowledgment The author would like to thank his colleagues J. Moreno, A. Zaks, U. Shadron, P. Bose and A. Kudriatse or useul discussions; and K. Warren or the management support. 6. RFRCS [1] A. Alandpour et al. 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