Z transform elements Part 1:

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1 Z nsform elements Part 1: About the writer: Harey Morehouse is a conctor/consultant with many years of experience using circuit analysis programs. His primary actiities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harey.annie@erizon.net. Simple questions regarding my articles for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!! Summary: This document will be in seeral parts, where this is part 1. Difference equations inole expressions that hae meaning at discrete time interals sampled data systems. Generally this inoles the use of A/D conerters, digital processing functions, and D/A conerters. It is also useful in describing switched capacitor systems. To deelop models that enable one to analyze such systems in a (SPICE) continuous time domain (nsient analysis) is one goal, and also in the frequency (AC analysis) with one set of models is the goal. Here we deelop one deice model for the z -1 function. Sampled Data Systems: There are seeral different ways to sole difference (not differential) equations. These implementations often are combined in a system with analog circuitry. It would be useful to be able to able to accommodate both sampled data and continuous time circuitry analysis within one solution enironment such as SPICE. And with the proper Z nsform elements this is possible and feasible. Like the familiar Laplace s nsform, the Z nsform element can also be used within SPICE. Z nsform definition: A sampled data system is usually described as an equation or set of equations in nt. The nsformation of this system into the Z domain is accomplished by means of the following equation. Interesting as this might be, to those who are interested, it really tells us nothing. What is needed is a means to relate the V(z) expressions into a form that SPICE can use. And there is. The z ariable can be shown to be equialent to: z = e st

2 Now the e -st function can be shown to be a delay in the time domain. The function delays the associated product of this function by time T. So we can associate z -1 with a time delay of T seconds. But what is the inerse of a time delay? What is the meaning of z? Now we get inoled with the quasi-function deised by P.A.M. Dirac, who inented quantum mechanics, the so-called Dirac delta function. This function is defined as: δ(t-a) = 1/e as This function is equal to zero when t a, one when t = a. It is of infinitesimally when it is at zero argument time and infinitely large in amplitude at time t = a, howeer its integral is equal to one. Remember now that we are dealing with sampled data systems whose alues are only meaningful at the instant of sampling time. With that restriction, a simple delay represents the z -1 operator. Now often sampled data systems are written in terms of powers of z or z n, as well as in powers of z -1 or z -n. Without attempting to describe what the inerse of a Dirac delta function looks like, we can note two things for now. The first is that one can always conert a system written in terms of z n to one in terms of z -n rather easily, And secondly there is a function that will allow a solution to the ratio of two polynomials in z n, the Discrete Time Transfer Function. z -1 deice modeling 1 The first deice to be created is based on a lossless delay line implementation. The circuit to do this is shown in Figure 1 following. in 2 V1 SIN T1 4 out R1 Zm1 test circuit1 Figure 1 In Figure 1 a simple delay line and a buffer amplifier is used to create a z -1 deice model. The parameters passed to the delay line are shown in Figure 2.

3 Circuit 1 passed parameters Figure 2 The important parameters to be passed are those noted. (In order to create this part the alue of frequency should be set to its default alue of zero.) The nsmission delay is set equal to the reciprocal of the sampling frequency. The alue shown corresponds to a 10Kc sampling rate. A nsient graph of the circuit performance is shown in Figure 3.

4 1.00 Z test1 ckt_transient_6_graph 800m 600m 400m 200m in -200m -400m -600m -800m m 600m 400m 200m out -200m -400m -600m -800m 50u 100u 150u 200u 250u time 300u Circuit1 zm1 circuit nsient graph Figure 3 350u 400u 450u 500u In Figure 3 it is seen that the circuit does indeed perform as intended. Now it is desired that the circuit model work in an AC analysis also. An AC frequency sweep was performed on the circuit. The results are shown in Figure 4. Now it is desired to see how this will react to an AC sweep. A sweep was performed with 1 as the AC signal source. The results are shown in Figure 5.

5 Z test1 ckt_small Signal AC_6_Graph db_out ph_deg_out k k k k k k k k k k k k k k k k k 100k 1000 FREQ zm1 AC sweep Figure 4 Here it is seen that the output gain is uniform oer from zero to about zero to infinity frequency range. Howeer, just out of curiosity, let us separate the two cures. This is shown in Figure 5 following. Z test1 ckt_small Signal AC_6_Graph db_out ph_deg_out db_out 1000u 800u 600u 400u 200u -200u -400u -600u -800u -1000u -1200u -1400u -1600u -1800u -2000u ,000 ph_deg_out -1,500-2,000-2,500-3,000-3, k 100k 1000k FREQ zm1 AC sweep2 Figure 5

6 This is a most interesting set of cures! Until one notices that the db output is essentially constant at zero db. Now what we are looking at is the small signal gain at particular frequencies, it must be remembered. At all frequencies there is no effectie attenuation, howeer with increasing frequency the delayed output is seeing more and more time delay per cycle, an effectie phase shift. If there is a phase shift, there must be a gain change as the output signal real and complex parts are not perfectly in synchronism due to numerical errors and SPICE solution parameters that indicate an acceptable solution has been found. This is alidated by a plot of the real and imaginary parts of out, shown in Figure 6 following. Z test1 ckt_small Signal AC_10_Graph re_out imag_out re_out imag_out m 6000m 4000m 2000m -2000m -4000m -6000m -8000m m 6000m 4000m 2000m -2000m -4000m -6000m -8000m k 100k 1000 FREQ zm1 AC sweep3 Figure 6 The next circuit we wish to examine is the effect of cascading these elements. Refer to Figure 7 following.

7 in 2 T1 4 3 out T2 6 V1 SIN R1 R2 7 out2 E1 E2 Cascade zm1 circuit 2 Figure 7 Figure 7 is sightforward. Deices E1 and E2 are unity gain buffers to eliminate circuit loading. The nsient graph of this circuit is shown in Figure 8. in m 600m 400m 200m -200m -400m -600m -800m Z test1 ckt2_transient_16_graph out 800m 600m 400m 200m -200m -400m -600m -800m 800m 600m out2 400m 200m -200m -400m -600m -800m 100u 200u 300u 400u 500u time 600u 700u Cascade zm1 circuit 2 cascade connection Figure 8 800u 900u 1.00m The circuits do not interact and the delays of each stage accumulate. We are not done with this circuit yet, but first we will create another realization for the function. z -1 deice modeling 2 B2Spice contains a model for a discrete time nsfer function. This consists of simulating the nsfer function of the ratio of two polynomials in z n. This is a hard coded function in C, and not directly accessible for modification. Could this function be used to create a z -n as well as a z n function? We will first consider making a z -n function,

8 as the result of the internal expression equaling (1)/(z). Consider the circuit of Figure 9 following. X2 4 +in -in 6 5 Vin SIN R1 1out E1 zm1 circuit 2 deice model Figure 9 The circuit is sight forward, with the nsmission line of the preious model replaced by X2, a discrete time nsfer function model. Now this deice is unusual, in that to get to the parameter settings, then after the Edit window opens, click the Edit model button. This is shown in Figure 10. zm1 circuit 2 deice model Figure 10

9 The X2 numerator is set to unity, ( 0 0 1) and the denominator to z, (1 0 0). The sampling frequency is set to 5K, or a period of 100 usec. Note that the creator of the circuit used half periods of delay for his realization. Thus, a denominator of (0 1 0) would correspond to a half delay of the input frequency period, or e s*/2f. A nsient graph of this circuit is shown in Figure Z test2 circuit1_transient_1_graph 8000m 6000m 4000m 2000m 1out -2000m -4000m -6000m -8000m 8000m 6000m 4000m 2000m inp -2000m -4000m -6000m -8000m 1000u 2000u 3000u 4000u 5000u time 6000u 7000u 8000u 9000u 1.000m zm1 circuit 2 deice nsient test Figure 11 The circuit behaes nicely. Now that we hae two working models, they may be compared. This is done in the circuit of Figure 12. inp1 7 Vin SIN X2 +in -in 6 R1 5 1out E1 inp2 V1 SIN 2 T1 4 R2 3 2out E2 zm1 circuit 2 test2 comparison test Figure 12 In Figure 12 the two delay circuits are brought together for a comparison test. The results of a nsient test are shown in Figure 13.

10 Z test2 circuit2_transient_32_graph 1out 2out inp1 inp m m m m m m m m u u u u u u u time zm1 circuit 2 test3 nsient comparison test Figure u u m There is no apparent difference in the results. Figure 14 shows the results of an AC sweep comparison test. Z test2 circuit2_small Signal AC_35_Graph db_1out db_2out dbdiff 1000u 500u db_1out -500u -1000u -1500u -2000u 1000u 500u db_2out -500u -1000u -1500u dbdiff k 100k 1000k FREQ zm1 circuit 2 test3 sweep comparison test Figure 14

11 In Figure 14 it is seen that the difference between the two outputs is 234 db less than the input, which is zero for all purposes. The question now remains which of the two implementations should be used to create the z -1 deice? The answer is that the nsmission line based model is simpler and more trouble free and so it will be used. We will create two ersions of the circuit, with slightly different topologies. One is floating, and the other is grounded. These are shown in Figure 14 following. Passed parameters: Td - time delay zo characteristic impedance note: leae other alues as show, 0 for frequency and 0 for init conditions and 1 for mormalized length INp INn INp INn T1 R2 7 5 R1 {zo} OUTp E1 OUTn OUTp OUTn 10Meg Zminus1 deice to be modeled Passed parameters: Td - time delay zo characteristic impedance note: leae other alues as show, 0 for frequency and 0 for init conditions and 1 for mormalized length INp T2 INp 4 OUTp OUTp R3 {zo} E2 Zm1 deice to be modeled z -1 deice model circuits Figure 14 The aboe circuits were turned into parameterized subcircuit deices and embedded in a circuit as shown in Figure 15.

12 inp2 V1 SIN T1 4 R2 3 out1 E2 2 U1 INp OUTp 5 out2 INn OUTn U2 INp OUTp 13 out3 z -1 deice model circuit3 Figure 15 Passed parameters are z0 = and Td = 0.1ms. (Actually, the alue passed for z0 is meaningless, as the internal nsmission lines are assumed perfectly terminated in the models.) The two deices perform almost identically, howeer there are ery ery slight differences due to the floating implementation used for U1. The zmimus1 netlist (of deice U1) is: ************************ * B2 Spice Subcircuit ************************ * Pin # Pin Name * INp INp * INn INn * OUTp OUTp * OUTn OUTn.Subckt Zminus1 INp INn OUTp OUTn ***** main circuit R e+002 T1 INp INn 5 7 z0 = 1k td = e-004 nl = 1 ic = 0 E1 OUTp OUTn R2 INn 7 10Meg.ends The zm1 netlist (of deice U2) is: ************************ * B2 Spice Subcircuit ************************ * Pin # Pin Name * INp INp * OUTp OUTp.Subckt Zm1 INp OUTp

13 ***** main circuit T2 INp z0 = 1k f = 0 td = {Td} nl = 1 ic = 0 R3 4 0 E2 OUTp ends Conclusions: Two ersions of a z nsform delay element are presented, howeer the reader must by cautioned that in the sampled data domain the alues hae meaning only at the sample times.