Spanning Tree Based State Encoding for Low Power Dissipation

Transcription

1 Sannin Tree Based State Encodin or Low Power Dissiation Winried Nöth and Reiner Kolla Lehrstuhl ür Technische Inormatik, Universität Würzbur, Würzbur, Germany Abstract In this aer we address the roblem o state encodin or synchronous inite state machines. The rimary oal is the reduction o switchin activity in the state reister. At the beinnin the state transition rah is transormed into an undirected rah where the edes are labeled with the state transition robabilities. Next a maximum sannin tree o the undirected rah is constructed, and we ormulate the state encodin roblem as an embeddin o the sannin tree into a Boolean hyercube o unknown dimension. At this oint a modiication o Prim s maximum sannin tree alorithm is resented to limit the dimension o the hyercube or area constraints. Then we roose a olynomial time embeddin heuristic, which removes the restriction o revious works, where the number o state bits used or encodino a k-state FSM was enerally limited to dlo 2 ke. Next a more sohisticated embeddin alorithm is resented, which takes into account the state transition robabilities not covered by the sannin tree. The resultin encodins o both alorithms oten exhibit a lower switchin activity and ower dissiation in comarison with a known heuristic or low ower state encodin. 1. Introduction The synthesis o circuits with reduced ower consumtion has rown more and more imortant over the last years. One drivin orce behind low ower circuit desin is the demand or loner battery lie o ortable comuters and telecommunication equiment. Another one results rom the excessive ower consumtion o hih erormance micro rocessors, which is currently the limitin actor in interation density o sinle- and multi-chi modules. This ower consumtion oten leads to reliability roblems due to overly hih oeratin temeratures. The rowin need or hih erormance comuters however can be exected to urther raise the imortance o ower related research in the uture. Research activity on low ower circuit desin is widesread and ranes rom voltae scalin and rocess otimization to hih level aroaches like instruction set desins and hardware/sotware codesin. This aer ocusses on minimizin the ower consumtion o synchronous inite state machines (FSMs), which orm an imortant art o many VLSI roducts. Since the circuit realization o a FSM is mostly determined by the state encodin, the encodin can be justly assumed to have a reat inluence on ower dissiation. Our rimary oal is the reduction o switchin activity in the state reister, but we will show that our encodins oten also lead to a reduced overall ower dissiation o the circuits enerated by SIS [10]. Research on FSM state encodin was irst tareted at minimization o circuit area and delay. For two level circuits De Micheli et al. devised alorithms or symbolic minimization and bit minimal state encodin [4], while Devadas et al. [5] develoed the MUSTANG state assinment system taretin multilevel networks. Power related research was irst aimed at recise comutation o switchin activity in sequential circuits [9][11]. Since then several low ower state encodin alorithms have been roosed. Tsui et al. [12] interated cost unctions or state reister and transition loic activity, while Benini et al. [1] develoed alorithms tradin o accuracy vs. comutational comlexity. Chen et al. [2] already ormulated the encodin roblem as a hyercube embeddin roblem. Common to these and other aroaches however is the limitation to a redetermined number o bits or the state encodin, which will be removed in this aer. We have just received notice that simultaneously to this work Molitor et al. [6] develoed a similar state encodin alorithm taretin the size o the BDD reresentation. The aer is oranized as ollows. Section 2 contains an examination o ower related issues in FSM synthesis. In section 3 we describe the connection o state encodin and hyercube embeddin and resent a modiication o Prim s alorithm or sannin tree comutation as well as two alorithms or sannin tree directed state encodin. Section 4 contains results and conclusions. 2. Power dissiation in FSMs FSMs are reresentations o sequential boolean unctions. They are conveniently described by a state transition rah (STG), where nodes reresent the states, and directed edes, labeled with inuts and oututs, describe the transition relation between states. When imlemented in hardware, FSMs

2 enerally are realized by an architecture shown in iure 1. Each state corresonds to a binary vector stored in the state reister. The combinational loic comutes the next state and outut unction based on the current state and inut values. The binary values o the inuts and oututs o a FSM are usually determined by external requirements, while the state encodin is let to the desiner. inuts combinational loic state reister Fi. 1: FSM hardware realization oututs In a sequential circuit o this tye, ower is dissiated in the state reister as well as in the combinational loic. This rimarily results rom chanin values o circuit sinals, where caacitances are chared or dischared (dynamic ower dissiation). The dynamic ower dissiation in the combinational art o the circuit is very diicult to estimate, even ater the state encodin is determined. At the beinnin there are already several dierent realizations to choose rom, deendin on what kind o technoloy will be used. Later, when the ate level imlementation is known, the exact comutation o the dynamic ower dissiation includin litches is oten intractable, since it requires the examination o all ossible airs o inut atterns o the combinational loic. Due to these diiculties the research in this aer ocusses on the minimization o the exected state reister switchin activity described below. This aroach still leads to a ood circuit in terms o ower consumtion, i a low switchin activity in the latch oututs corresonds to a low switchin activity in the combinational loic. The averae dynamic ower dissiation o the state reister P sb can be described by ollowin exression: P sb = 1 2 V 2 dd X i2sb C(i) E(i) where is the clock requency o the state machine, C(i) is the caacitance o the latch storin state bit i and E(i) is the exected switchin activity o the latch. Notice, that C(i) is not necessarily the same or all bits, since it includes the caacitance o the latch anout into the combinational art. Since this anout cannot be determined beore the state encodin is known, we simliy by assumin an overall state reister caacity C sr and introduce an exected reister switchin activity E sr : P sb 1 2 V 2 dd C sr E sr Let S be the set o all states. For an ininitely lon series o state transitions, E sr can be exressed by E sr = X i;j2s (i $ j) h(i; j) (1) where (i $ j) is the robability o a transition between states i and j, andh(i; j) is the hammin distance o the state codes o i and j. (i $ j) can be determined stochastically by assumin equirobability o all inut atterns o the FSM and solvin the Chaman Kolmoorov equations [3]. Alternatively they can be obtained statistically by alyin a suiciently lon series o inut atterns until the state occurrence and transition robabilities convere towards discrete values [9]. For the urose o minimizin (1), a FSM reresentation is suicient, which contains only the state to state transition robabilities. We will thereore transorm the initial STG by collasin all directed edes between any air o states into an undirected ede. The undirected edes are then weihted with their corresondin transition robability. Since the robabilities concerned are unconditional, the sum o all ede weihts includin sel loos equals one. From now on this undirected weihted rah will be reerred as the robability attraction rah (PAG, iure 2) st1 st st2 st Fi. 2: PAG o dk15 3. Hyercube embeddins A state encodin can always be ormulated as an embeddin o the STG or PAG into a (Boolean) hyercube. A hyercube o dimension n is a rah with 2 n nodes, where every node is labeled with an unique binary value rom 0 to 2 n, 1. Furthermore, every node v has n edes labeled 1 :::n, which lead to all nodes whose labels have hammin distance 1 rom v. Consequently, the hammin distance o any two nodes in the hyercube equals the lenth o the shortest ath between the nodes. An embeddin o a rah G into a host rah H is an injective main o the nodes o G to the nodes o H, so that every ede in G corresonds to the shortest ath between the mains o its terminal nodes in H. The dilation o an ede o G is deined as the

3 lenth o the corresondin ath in H. More detailed inormation on embeddin roblems can be ound in works on arallel comutin [8][13]. Since most roblems concernin embeddins o eneral rahs are NP comlete, we will only ive an inormal discussion on what could be a ood hyercube embeddin with resect to ower dissiation: (A) Reardin equation (1) it is desirable to embed with small dilation, since the dilation o an ede (v; w) corresonds directly to the hammin distance o the encodins o v and w, and the hammin distance determines the reister switchin activity or a iven state transition. The best obvious solution or our urose would be an embeddin with dilation 1 or all edes. Grahs with such an embeddin are called cubical. Unortunately it can be shown that there is no dilation-1 embeddin or many rahs (e.. rahs containin odd cycles). Furthermore, the roblem o indin an embeddin with minimum overall dilation is NP comlete or eneral rahs [13]. For most cubical rahs it is also diicult to determine their cubical dimension, which is the dimension o the smallest hyercube, where they can be embedded with dilation 1. (B) Reardin overall ower dissiation, it is also desirable to embed into a hyercube with low dimension, since the dimension o the hyercube corresonds to the number o bits o the state encodin, and unnecessary lare state reisters may increase ower consumtion. Area restrictions may even limit the number o state bits available or encodin. Without boundaries to dilation it is always ossible to embed a rah with k nodes into a hyercubeo dimension dlo 2 ke. Unortunately this will oten lead to a hih state reister switchin activity or many state transitions. While most research has concentrated on B with A as a side issue, we will try to ind a solution to A, with B as a secondary criterion. For that we have to embed G into a hyercube H, so that dilation o edes o G with hih weiht is minimized while the dimension o H is ket small. Obviously it is ineasible to otimally embed an arbitrary rah G(V;E), but the roblem can be simliied by embeddin a subrah G 0 (V;E 0 ), so that dilation > 1 occurs only on edes (v; w) with (v; w) 2 E and (v; w) 62 E 0.Thatis,i we construct a cubical subrah o G, which contains the edes with the hihest weihts, a dilation-1 embeddin o this subrah would intuitively lead to a low switchin activity in the state reister. Such a subrah is the maximum sannin tree o the PAG. SPANNING TREES Let G(V;E) be a weihted connected rah. A sannin tree o G is a subrah T (V;E 0 ) o G, sothatt is connected and #E 0 =#V,1.LetT be the set o all sannin trees o G. Amaximum sannin tree T max (V;E max ) o G is a sannin tree, so that 8 T (V;E 0 ) 2T: X (v;w)2emax W (v; w) X (v;w)2e 0 W (v; w) A maximum sannin tree can be constructed in time O(#E lo #V ) e.. by Prim s alorithm [7], and it is unique by construction, i no two edes o G have the same weiht. Furthermore, all trees are cubical, and while the exact determination o their cubical dimension cd is NP hard, some lower and uer bounds o cd are known. Let T (V;E) beatreeandletk be the maximum deree o any node v 2 V.Then max(dlo 2 #V e;k)cd(t ) #V, 1 Both lower and uer bounds o this inequation are attained by certain tyes o trees. A ath rah T P o lenth #V,1 e.. can be embedded by a Gray code with cd(t P )= dlo 2 #V e, while the star rah T S with k =#V,1or the center node has cd(t S )=k=#v,1. Since the dimension o the embeddin is stronly connected to the deree o nodes in the tree, we have modiied Prim s alorithm to accet a arameter d max limitin the deree o any node in the resultin sannin tree: modiied rim(rah G(V;E), int d max ) V T := one initial v init 2 V E T := ; cut := (v init ;w)2e do #V, 1 times (u; v) := select ede(cut, d max ) where u 2 V T ;v 2VnV T E T := E T [ (u; v) V T := V T [ v remove edes containin v rom cut cut := cut [(v; w) j w 2 V nv T return T (V T ;E T ) In the oriinal version, select ede simly selects the ede with the hihest weiht rom the cut. The new rocedure selects the hihest weihted ede (u; v), which does not increase the deree o the node u 2 V T above d max,i this is ossible. Subsequent tests with our embeddin alorithms showed, that or d max = lo 2 #V +1all benchmarks could be embedded into a hyercube o dimension 2 lo 2 #V or less with no siniicant enalty in switchin activity. The resultin sannin tree, which in most cases is a maximum sannin tree, roved to be a ood structure or directin a hyercube embeddin. TREE EMBEDDINGS For a iven tree T (V;E) our embeddins bein always at subsets o nodes and edes V C ;E C o T, which orm the center o the tree with resect to lonest aths. This is a direct way to construct Gray code embeddins with loarithmical dimensions or simle aths. Besides, or a well balanced tree the subtrees connected by the center o the tree can be embedded with about the same dimension, so that a

4 divide and conquer aroach should ind an embeddin o low overall dimension. V C and E C are deined as ollows: Let or = v 0 ;::: ;v k ath o T be () =kthe number o edes on. Then V C = v b k 2 c ;v d k 2 e is the set o nodes in the center o. We now deine the center o the tree as V C := [ :()=k maximum V C The center o the tree has the ollowin roerty: V C = \ :()=k maximum V C Proo: It is suicient to rove the exression or any air o lonest aths. Assume there are two lonest aths = v 0 :::v k and q = u 0 :::u k. The size o the ath centers exclusively deend on k,sothat: #V q C =#V C Assume urther, that there are nodes v i 2 V C and u j 2 V q C, with v i 62 V q C and u j 62 V C. Let c be the ath between v i and u j. Then there are subaths 0 ;q 0 o ; q o maximum lenth, which end in v i ;u j, so that ollowin equations hold: We will now show, that 0 \ q 0 = ; 0 \ c = v i q 0 \ c = u j ( 0 c q 0 )=( 0 )+(c)+(u 0 )>k (2) The equation on the let is true, since c has one node in common with each 0 and q 0. For the inequation on the riht there are two dierent cases to be examined: 1. \ q = ;: In this case ( 0 ) = (q 0 ) = d k e, because 2 the lonest subaths o ; q to a node in their ath centers contain at least hal o the edes o ; q. Since (c) 1, here (2) is valid. See iure 3 or illustration. q q vi c uj Fi \ q = V 0 6= ;: In this case c contains a node v 0 2 V 0, thereore (c) 2. Since at least one o the subaths rom a terminal node o ; q to v i ;u j does not contain nodes rom V 0, ( 0 ) = (q 0 ) = b k c, and (2) is valid aain. This is 2 illustrated in iure 4. q u j q v i v c Fi. 4 Exression (2) already imlies, that neither nor q are lonest aths, i they have dierent centers. E C is deined as the set o edes in the center o lonest aths. Here we have to distinuish between two cases or the lenth k o lonest aths: 1. k is even: We know rom our deinition above, that #V C =1. E C is now deined by E C := (v; w) j v 2 V C ^ 9 = v;w;::: ;u : 2. k is odd: Here #V C =2and consequently ()= k 2 E C := (v; w) j v 2 V C ^ w 2 V C ^ v 6= w V C and E C can be eiciently comuted by a sinle ass over the tree: Our alorithm iteratively removes the set o leas rom the tree, until #V 2. V C remains unchaned durin this oeration, since 1. no lea is in V C,i#V > 2,and 2. any lonest ath looses both terminal nodes. thereore the ath centers do not move. Ater the last iteration, V C consists o the nodes remainin in V,andE C is either the inal ede in E or the set o edes, which were removed last rom the tree: et tree center(t (V;E);E C ;V C ) V leas := v 2 V j deree(v) =1 E leas := ; while #V > 2 E leas := (v; w) 2 E jv; w\v leas 6= ; V := V nv leas E := EnE leas V leas := v 2 V j deree(v) =1 V C := V i #E >0 E C := E else E C := E leas

5 We will now resent olynomial time divide and conquer alorithms, which construct dilation 1 embeddins o trees into a hyercube by dividin the trees at the center deined above. FAST EMBEDDING ALGORITHM We have shown that the removal o an ede o E C breaks u a lonest ath at or near it s center, leavin two subtrees o unknown size and structure. Since both subtrees are to be embedded recursively, it would be best to balance the subtree embeddins with resect to dimension to minimize the dimension o the overall embeddin. It is however diicult to determine in advance, what dimension a subtree embeddin will have. Our irst alorithm thereore selects an ede (v; w) 2 E C, whose removal rom E leads to the most evenly sized subtrees T 0 and T 00 with resect to the number o edes o the subtrees. Then an index i 2 N corresondin to the ede label in the host hyercube is assined to (v; w), which means that the labels o the nodes connected by e dier exactly in osition i. Now (v; w) is removed rom the tree, slittin it u into two subtrees. The alorithm then recursively rocesses the subtrees T 0 and T 00 : embed tree ast(tree T (V;E), int i) et tree center(t;v C ;E C ) select ede (v; w) 2 E C connectin most balanced subtrees (v; w).idx := i remove (v; w) rom E et subtrees T 0 (V 0 ;E 0 );T 00 (V 00 ;E 00 ) i #E 0 > 0 embed tree ast(t 0, i +1) i #E 00 > 0 embed tree ast(t 00, i +1) The alorithm starts with embed tree ast(t;1) and it terminates, when all edes have indices assined. Overall runtime is o the order o O(#V 2 ) o the oriinal rah, since the rocedure is called once or every ede, while an eicient imlementation o et tree center runs in O(#V ). To derive an encodin rom the embedded tree a code is irst assined to one o the nodes. Then the codes o adjacent nodes are comuted by tolin the bit adressed by the index o the connectin ede. This rocedure is iterated, until all nodes are encoded. Since there are no cycles, the overall encodin is uniquely determined by the code o any node. By incrementin the index arameter i durin the recursion, the embeddin rocedure ensures, that or any deth the index o the ede (v; w) selected rom E C is not aain used in one o the subtrees connected by (v; w). This ensures, that any ath rom one subtree to another traverses at least one ede with an unique label i. Thereore all state codes o nodes in dierent subtrees dier at least in osition i. Since any air o nodes is somewhere in the recursion slitted u and assined to dierent subtrees, the encodin is injective. GREEDY EMBEDDING ALGORITHM The above alorithm is very ast, since it only embeds edes rom the sannin tree without reard to costs rom other edes in the PAG. Our second alorithm tries to take into account those edes o lower weiht, too. This however is only ossible between nodes, which are connected by a ath o already embedded edes in T. The new rocedure thereore always maintains a reion o encoded nodes Venc, which are connected by edes with known indices. Venc is initialized with a node v 2 V C o the center o the overall tree. Every time an index is assined to an ede (v; w), where one o the nodes, say v, is already encoded, the encoded reion is exanded by w and others, which are connected to w by reviously embedded edes: embed tree reedy(tree T (V;E), int i) et tree center(t;v C ;E C ) i Venc = ; v init := v 2 V C v init.code := 0 Venc := v init or all (v; w) 2 E C (v; w).idx := select index(t;venc;i) i:= i +1 remove (v; w) rom E exand reion(venc) or all T 0 (V 0 ;E 0 ) subtree o T i #E 0 > 0 embed tree reedy(t 0, i) There are two urther main dierences to the ast alorithm. First, the index to be assined to an ede is determined by a secial reedy rocedure select index, whichis described below. Second, all edes in E C are embedded within the actual call without selection. This usually leads to a aster rowth o the encoded reion in comarison with the revious alorithm. For the same reason the subtrees are rocessed in the inal loo, so that subtrees containin encoded nodes are embedded irst. This also immediately increases the encoded reion, the size o which determines the accuracy o the index selection, as ollows: For an ede (v; w) not connected to the encoded reion Venc select index simly returns the maximum index value, which corresonds to the ede index assined in the ast embeddin alorithm. I however (v; w) is connected to Venc, the node w 62 Venc can be encoded, and select index or all ossible indices i comutes the new code rom the code o v by tolin bit i. Then the switchin

6 costs between w and all other encoded nodes are determined rom the roduct o hammin distance and transition robability rom the PAG. I the actual i leads to a code that is already used or another node, cost is set to 1. Finally the index leadin to the lowest switchin costs amon the encoded nodes is selected: int select index(ede (v; w), node set Venc, int i max ) i v 62 Venc and w 62 Venc return i max nn assume v 2 Venc and w 62 Venc or all i 21;::: ;i max w.code := v.code toled in ith bit cost(i) := 0 or all u 2 Venc i u.code = w.code cost(i) :=1 i (u; w) 2 attraction rah cost(i) :=cost(i)+h(u; w) W (u; w) i cost(i) <cost(i min ) i min := i return i min The reedy alorithm is considerably slower than the ast one, since or every ede O(#V ) indices have to be tested, and or every index all codes rom the subset o encoded nodes may be examined. It is however still olynomial, and easible at least or medium sized roblems, since all benchmark embeddins were enerated within ew minutes. 4. Results We have run our ast and reedy encodin alorithms on a set o MCNC FSM examles in kiss2 ormat. As a reerence the O(#V #E) encodin alorithm ow3 resented by Benini [1] was selected, since it comutes a minimum lenth encodin taretin low state reister activity in a comarable small runtime. The results are summarized in table I. Columns 1 and 2 contain the circuit name and the number o states ater elimination o unreachable and unleavable states. The ollowin six columns in rous o three resent inormation about state reister size and exected reister activity or each o the alorithms tested. The inal three columns dislay the estimated ower consumtion in W o the circuit enerated by SIS ater extraction o sequential don t cares and otimization with scrit.rued [10]. The runtimes o the three encodin alorithms are not rinted, since bein in the order o seconds or minutes they were always dominated by the recedin Chaman Kolmoorov and the ollowin sequential otimization scrit. An asterisk is rinted where the otimization scrit did not terminate within several hours. As we can see, or 28 out o 44 examles the exected switchin activity E sr is reduced with resect to ow3 either by the ast alorithm or by the reedy alorithm, and it is increased by both in only three cases. Reduction varies rom 2% to 28% with an averae o about 13 ercent, while the state reister size is always ket at or below 2 lo 2 #V. Sometimes a reduction in switchin activity is achieved without a enalty in the size o the state reister. For the ower consumtion ater synthesis, as estimated by SIS, the results can be summarized as ollows. Out o 37 circuits, where SIS otimization terminated or all encodins, 26 o our best circuits are better in terms o ower consumtion than those encoded by ow3, while only six are worse. Here imrovement varies rom 1% u to 29% with an averae o about 17 ercent. It is also shown in table I, that or 26 out o 37 circuits imrovements were achieved either or both reister switchin activity and ower consumtion or or neither o them. This as well as many articular results conirm our assumtion, that reister switchin activity and ower consumtion are hihly correlated. Comarison o state reister size and ower consumtion however reveals no clear correlation. Sometimes circuits with larer state reister dissiate more ower, but there are also cases, where the overall ower dissiation is reduced desite a larer state reister and hiher switchin activity in the state reister. This robably comes rom larer sequential don t cares leadin to better otimization by SIS. This aer addressed the FSM state assinment roblem tareted towards low ower dissiation. The roblem was ormulated as a hyercube embeddin roblem, where the embeddin rocess is directed by a maximum sannin tree o the robability attraction rah o the FSM. We roosed a modiication o Prim s alorithm to limit the deree o the sannin tree and alon with it the dimension o the embeddin. Then two dierent state embeddin alorithms were resented, which in about two out o three cases roduced encodins with lower switchin activity and ower consumtion than a known heuristic o comarable comlexity. Due to the olynomial runtimes o our alorithms they are alicable to many lare FSMs, where the states can be exlicitly enumerated. It is also worth mentionin, that the roosed heuristics can be used or any state encodin roblem, where the costs can be described by an ede weiht unction o the STG. Reerences [1] L. Benini and G. DeMicheli: State Ass. or Low Power Diss. IEEE Journ. on Solid State Circ., 11(4): 32-40, March 1994 [2] Chen, Sarrazadeh, Yea: State Enc. o FSMs or Low Power Desin. To aear in VLSI Desin. [3] D.R. Cox and H.D. Miller: The Theory o Stochastic Processes. Chaman Hall, 1965 [4] DeMicheli, Brayton, Saniovanni: Otimal State Ass. or FSMs. IEEE Trans. on CAD, 4(3): , July 1985

7 circuit #V #bits E sr SIS ower (W ) ow3 ast reedy ow3 ast reedy ow3 ast reedy bbara bbsse bbtas beecount cse dk dk dk dk dk dk donile dvram ex ex ex ex ex ex etch keyb kirkman lion lion lo * mark mc nucwr ous lanet * * * ram test * * rie s * * 721 s sand * sc shitre sse styr * * * sync tav tbk * * 1121 train train [5] Devadas, Ma, Newton, Saniovanni: MUSTANG - State Ass. o FSMs Taretin Multilevel Loic Imlementations. IEEE Trans. on CAD, 12(11): , December 1988 [6] Forth, Molitor, Vot: State Encodin o FSMs Taret. BDD Reres. Priv. Comm. Univ. Halle, Germany, March 1998 [7] T. Lenauer: Combinatorial Alorithms or Interated Circuit Layout. Teubner Verla, 1990 [8] Livinston, Stout. Embeddins in Hyercubes. Mathematical and Comutational Modellin. 11: , 1988 [9] Najm, Goel, Hajj: Power Estimation in Sequential Circuits. Proc. o the 32th DAC, , Table I [10] Sentovich, Sinh, Brayton, Saniovanni: SIS - A System or Sequential Circuit Synth. Tech. Re., UC Berkeley, [11] Tsui, Pedram, Desain: Exact and Aroximate Methods or Calculatin Sinal and Transition Probabilities in FSMs. Proc. o the 31th DAC, 18-23, 1994 [12] Tsui, Pedram, Desain: Low Power State Assinment Taretin Two- and Multilevel Loic Imlementations. Proc. o the 31th DAC, 82-87, 1994 [13] Waner, Corneil: On the Comlexity o the Embeddin Problem or Hyercube Related Grahs. Discrete Alied Mathematics, 43:75-95, 1993