Digital Electronics Paper-EE-204-F SECTION-A

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1 B.Tech 4 th Semester (AEIE) F Scheme, May 24 Diital Electronics Paper-EE-24-F Note : Attempt five questions. Question is compulsory and one question from each of the four sections.. What is a loic ate? Explain each loic ate. 5x4 a. With truth table and loic symbol. b. Implement the followin usin MUX i. AND ate ii. OR ate c. Explain rin counter d. Desin the circuit of HA usin ROM SECTION-A 2. Minimise the followin function usin the GM method. 5x4 a. Y= m(,,3,7,,4) b. Convert the followins: i. (268.75) to binary ii. (.) 2 to octal iii. (36) 8 to hexadecimal c. Minimise the followin usin K-Map i. Y = m(4,5,,5) ii. Y=πM(3,6,9,4,5) d. Explain the procedure form eneration matrix in binary cycle codes 3. (a) Write in detail about various error detectin and correctin codes. 5 (b) Find the 9 s and s complement of the followin numbers 5 (i). 25 (ii) 55 (iii) 333 (iv) 982 SECTION-B 4. (a) Desin the circuit of full adder usin 8: MUX (b) Desin a full subtractor usin half subtractors. 5. Give the truth table and loic diaram of: a. 3:8 decoder b. Implement the function F(A,B,C) = m(,3,5,6) usin decoder 5 c. Desin a binary to ray code converter. SECTION-C 6. (a) Give the excitation table of the followins flip-flop (i) D FF (ii) JK FF (iii) T FF

2 (iv) SR FF b. Desin,,2,3, counter usin D FF c. Explain the workin of Master-Slave JK FF d. Explain the workin of Serial-in-Serial-out reister 7. Desin synchronour decade counter usin:, a. JK Flip-Flop b. Give the difference between the followin i. Decoder and De-Multiplexer ii. Ripple counter and Synchronous counter iii. Latch and Flip-Flop SECTION-D 8. (i) Desin the circuit of Half Adder usin PLA (ii) Desin BCD to XS-3 code converter usin PLA 9. (a) Realise the followin function usin ROM i. F= m(,,2,3) ii. F= m(,2,5) b. With the help of state table and state diaram desin a Mod-4 up/down counter.

3 SOLUTION B.Tech 4 th Semester (AEIE) F Scheme, May 24 Diital Electronics Paper-EE-24-F Note : Attempt five questions. Question is compulsory and one question from each of the four sections.. What is a loic ate? Explain each loic ate. 5x4 a. With truth table and loic symbol. Solution: Loic ates are the basic buildin blocks of any diital system. It is an electronic circuit havin one or more than one input and only one output. The relationship between the input and the output is based on a certain loic. Based on this, loic ates are named as AND ate, OR ate, NOT ate etc. THE OR GATE The OR ate produces a HIGH output when any or all of the inputs is HIGH. Fiure shows the symbol for an OR and its truth table. The operation function sin for the OR ate is + THE AND GATE The AND ate produces a HIGH output when all of the inputs are HIGH. The AND operation is denoted by a dor (.)..AND ate is shown in fiure below alon with the associated Truth Table. NOT GATE An inverter or NOT ate produces the complement of the input i.e. if the input if the output produces is and vice versa. The inverter symbol and truth table is shown below:

4 b. Implement the followin usin MUX i. AND ate ii. OR ate AND ate The truth table of AND ate is shown below: A B Y = A. B SOP eqn for AND ate function Y = Y = A B + A B + AB + AB The function Y=A.B can be implemented by usin a 4 x MUX with the select lines as AB and multiplexer output Y ivin the output Y=A.B OR ate implementation The truth table of OR ate is shown below: A B Y = A. B

5 SOP eqn for Y = A B + A B + AB + AB The function Y=A + B can be implemented by usin a 4 x MUX with the select lines as AB and multiplexer output Y ivin the output Y=A + B c. Explain rin counter A rin counter is constructed usin the serial-in serial-out reister whose output is fed back as input. Thus the bits from one stae to another is shifted with the arrival of every clock pulse. A 4-bit rin counter is shown in the followin fiure. The rin counter output is shown in the followin table d. Desin the circuit of HA usin ROM A B Sum Cy

6 The SP equations for the Sum and Carry (Cy) are iven below: Sum = A.B + A.B Cy = A.B The output are stored at the correspondin input combinations which for a ROM act as the address lines. The complete implementation is shown below: SECTION-A 2. Minimise the followin function usin the GM method. 5x4 a. Y= m(,,3,7,,4) Minterm M M M3 M7 M M4 Binary No. of s Rewritin the minterms by roupin them as per no. of s contained in their binary value. Then comparin and chekin every mineterm from one roup with adjacent roup for one bit chane. No of s Minterm Binary checked Pair m m,m - m m,m3-2 m3 m3,m7 - m m,m4-3 m7 m4 We see that after first level of pairin no further roupin are possible. So the final equation uses all the four minterms on the riht column. Y= A B C + A B D + A CD + ACD Final we draw the PI chart as shown below:

7 The final solution contain only the three essential prime implecants. Y = A B C + A CD + ACD b. Convert the followins: i. (268.75) to binary ii. (.) 2 to octal iii. (36) 8 to hexadecimal Solution: i = ii. (.) 2 to octal Binary to Octal is quite easy, we can take roup of three bits from riht (LSB) and write the equivalent octal of binary combination. (.) 2 = (453.7) 8 iii. (36) 8 to hexadecimal Octal to hex is also easy. First convert Octal to binary by writin 3-bit binay code of each octal diit. (36) 8 = () 2

8 Now roup the bits in 4-bit each roup and write the equivalent hex diit. So the answer is: () 2 = (F) 6 c. Minimise the followin usin K-Map i. Y = m(4,5,,5) ii. Y=πM(3,6,9,4,5) d. Explain the procedure form eneration matrix in binary cycle codes A code C is cyclic if (i) C is a linear code; (ii) any cyclic shift of a codeword is also a codeword, i.e. whenever a, a n - ϵ C, then also a n - a a n 2 ϵ C. Theorem Suppose C is a cyclic code of codewords of lenth n with the enerator polynomial(x) = + x + + r x r. Then dim (C) = n - r and a enerator matrix G for C is G r... 2 r r r

9 Proof (i) All rows of G are linearly independent. (ii) The n - r rows of G represent codewords (x), x(x), x 2 (x),, x n -r - (x) (*) (iii) It remains to show that every codeword in C can be expressed as a linear combination of vectors from (*). Indeed, if a(x) Î C, then a(x) = q(x)(x). Since de a(x) <n we have de q(x) < n - r. Hence q(x)(x) = (q + q x + + q n -r - x n -r - )(x) = q (x) + q x(x) + + q n -r - x n -r - (x). Example: The task is to determine all ternary codes of lenth 4 and enerators for them. Factorization of x 4 - over GF(3) has the form x 4 - = (x - )(x 3 + x 2 + x + ) = (x - )(x + )(x 2 + ) Therefore there are 2 3 = 8 divisors of x 4 - and each enerates a cyclic code. Generator polynomial Generator matrix I 4 x x + x 2 + (x - )(x + ) = x 2 - (x - )(x 2 + ) = x 3 - x 2 + x - [ - - ] (x + )(x 2 + ) [ ] x 4 - = [ ] 3. (a) Write in detail about various error detectin and correctin codes. 5 Different Error detectin and correctin codes are described below: i. Parity Method ii. Lonitudinal Redundancy Check (LRC)

10 iii. Hammin Code iv. Cyclic Redundancy Check (CRC) Parity Check: Parity system is a ood method of error detectin codes. It is a simple method of findin -bit error in transmitted code. In this an additional bit is appended with the code at the transmittin end such that the number of s become odd or even and accordin parity named as odd parity or even parity. At the receivin end the same parity as sent from the transmittin end is aain checked. Only problem with this code is that if more than -bit chane occur durin transmission then this is not suitable method. Example of odd parity Lonitudinal Redundancy Check (LRC ): In this system a two dimensional parity is enerated for a block of codes. HRC horizontal parity is appended with every code word and also vertical parity is appended with every column for a roup of codes. Then this whole block is transmitted. At the receivin end the block is checked for any chane in horizontal and vertical parity. Coordinates of the bit in error ives the exact code in which error occurred. As an example, if the characters RAVI is to be sent whose ASCII codes are Code ASCII Binary With Odd Parity R 52h A 4h V 56h I 49h Vertical Parity -> Now suppose this code is transmitted and the received code with -bit error is iven below. The error can be easily found by checkin the horizontal parity of each code and also vertical parity. The location of error is wron parity in row and column. With Odd Parity

11 X X So we find that the error is in row 2 and column 3 from riht(bit shown in bold). It can be corrected by simply complementin this bit. Hammin Code: Hammin code is used to detect error in RAMs. In this code k parity bits are added to form the n-bit data word, formin a new code word of n+k bit. Those positions as power of 2 are reserved for parity bits and the remainin bits are the data word. For example, consider a code word to be transmitted. It is first appended with parity bits at positions at power of 2 i.e. at positions,2,4,8,. As shown below: P8 P4 P2 P The parity bits are then calculated as: P: bits = ++++ = for even parity P2:bits = ++++= for even parity P4: bits = +++ = for even parity P8: bits = +++ = for even parity So the code becomes as : P8 P4 P2 P The code to be transmitted is: Cyclic Redundancy Check (CRC): In this code the polynomial (M(x)) is appended with the as many zeros as the deree of the divisor polynomial(p(x)) (step-). The alorithm at the sendin and the receivin end is iven below: Sendin. Multiply M(x) by x n 2. Divide x n M(x) by P(x) 3. Inore the quotient and keep the reminder C(x) 4. Form and send F(x) = x n M(x)+C(x) Receivin

12 . Receive F (x) 2. Divide F (x) by P(x) 3. Accept if remainder is, reject otherwise (b) Find the 9 s and s complement of the followin numbers 5 (i). 25 (ii) 55 (iii) 333 (iv) s and s complement are the sined representation is decimal system (BCD). We append to represent +ve number; and 9 to represent ve number. The 9 s complement of a number is found by (( n -) N) where n is the number of diits in the number N Decimal Number 9 s Complement I 25 = 25 (( n - ) N) = (( 3 - ) 25) = = 975 Here MSD( 9 ) indicate ve number Ii 55= 55 (( n - ) N) = (( 4 - ) 55) = = 9844 Here MSD( 9 ) indicate ve number Iii 333 = 333 (( n - ) N) = (( 4 - ) 333) = = 9666 Here MSD( 9 ) indicate ve number iv 982 = 982 (( n - ) N) = (( 4 - ) 982) = = 97 Here MSD( 9 ) indicate ve number s Complement = 9 s Complment + (( n - ) N) + = = = 976 Here MSD( 9 ) indicate ve number (( n - ) N) + = =9844+ = 9845 Here MSD( 9 ) indicate ve number (( n - ) N) + = = = 9667 Here MSD( 9 ) indicate ve number (( n - ) N) + = = 97 + = 98 Here MSD( 9 ) indicate ve number SECTION-B 4. (a) Desin the circuit of full adder usin 8: MUX

13 Solution: The truth table for the full adder is shown below: A B C Sum Carry Write the SOP equations Sum= m (,2,4,7) Carry = m(3,5,6,7) (b) Desin a full subtractor usin half subtractors. The truth table for full subtractor is shown below: A B C Diff Borrow

14 The SOP equations for the Diff and Borrow is iven below: Diff = m (,2,4,7) = A B C + A BC + AB C + ABC Borrow= m(,2,3,7) = A B C + A BC +A BC +ABC Solvin the above equations alebraically we et: Diff = A B C + A BC + AB C + ABC = A (B C + BC ) + A( B C + BC) = A xor B xor C Borrow = A B C + A BC +A BC +ABC = (A B C + A BC) + (A BC +ABC) = A C(B + B). C+ B (A C + AC) = A C + (AxnorC).B Lookin at the simplified equation aain: We find that there are two half subtractors hidden in these two equations and have been circled clearly. We can now construct the full subtractor usin two Half Subtractor.

15 5. Give the truth table and loic diaram of: a. 3:8 decoder 5 A decoder is a circuit that chanes a code into a set of sinals. It is called a decoder because it does the reverse of encodin.a common type of decoder is the line decoder which takes an n- diit binary number and decodes it into 2 N output lines. The truth table of a 3:8 decoder is shown below: C B A O O O2 O3 O4 O5 O6 O7 There are 8 output and hence 8 independent minterms. These can be implemented by a simple AND ate array connected to various input combinations as shown in the fiure.

16 b. Implement the function F(A,B,C) = m(,3,5,6) usin decoder 5 c. Desin a binary to ray code converter. Truth Table for Binary to Gray code converter Decimal Binary Input Gray Output Decimal B2 B B G2 G G

17 Loical Equations: G2 = B2B'B'+B2B'B + B2BB' + B2BB G = B2'BB' + B2'BB + B2B'B' + B2B'B G = B2'B'B + B2'BB' + B2B'B +B2BB' Simplification: G2 = B2B'(B' + B) + B2B(B' + B) = B2B' + B2B = B2(B' +B) = B2 G = B2'BB' + B2'BB + B2B'B' + B2B'B = B2'B(B' + B) + B2B'(B' + B) = B2'B + B2B' = B2 B G = B2'B'B + B2'BB' + B2B'B + B2BB' = B2'(B'B + BB') + B2(B'B + BB') =(B'B + BB') (B2' + B2) = B B Loic Desin of a 3-bit binary to ray code converter Fiure-: A 3-bit Binary to Gray Code Converter SECTION-C 6. (a) Give the excitation table of the followins flip-flop I. D FF II. JK FF III. T FF IV. SR FF

18 Excitation Tables: an excitation table shows the minimum inputs that are necessary to enerate a particular next state (in other words, to "excite" it to the next state) when the current state is known. They are similar to truth tables and state tables, but rearrane the data so that the current state and next state are next to each other on the left-hand side of the table, and the inputs needed to make that state chane happen are shown on the riht side of the table. The various excitation tables are shown below: b. Desin,,2,3, counter usin D FF Answer is bein prepared c. Explain the workin of Master-Slave JK FF Answer is bein prepared d. Explain the workin of Serial-in-Serial-out reister Answer is bein prepared 7. Desin synchronour decade counter usin:

19 a. JK Flip-Flop Answer is bein prepared b. Give the difference between the followin i. Decoder and De-Multiplexer ii. Ripple counter and Synchronous counter iii. Latch and Flip-Flop Answer is bein prepared SECTION-D 8. (i) Desin the circuit of Half Adder usin PLA Answer is bein prepared (ii) Desin BCD to XS-3 code converter usin PLA Answer is bein prepared 9. (a) Realise the followin function usin ROM i. F= m(,,2,3) ii. F= m(,2,5) Answer is bein prepared b. With the help of state table and state diaram desin a Mod-4 up/down counter.

20 Answer is bein prepared

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)