CHAPTER 7 REAL TIME IMPLEMENTATION OF SINGLE ELECTRON TRANSISTOR IN SPARTAN 3AN

Transcription

1 95 CHAPTER 7 REAL TIME IMPLEMENTATION OF SINGLE ELECTRON TRANSISTOR IN SPARTAN 3AN 7.1 Introduction In computer science and physics, quantum information theory is basic entity to gathering quantum information in the state of a quantum system and quantum information processing is using in engineering techniques to manipulated quantum information. Classical information can be analyzed with the mathematics of computer science, processed with digital computers, manipulated with algorithms, transmitted from place to place and quantum information is applied in analogous concepts. Quantum computers deals studies of quantum computing in theoretical computation systems such as superposition and entanglement make direct use of quantum-mechanical phenomena and to perform operations on data. Digital computers are very different from Quantum computers, fully based on transistors and encoded and computing information in form of binary digits or bits, two definite states (0 or 1) and allocate superposition of states for uses quantum bits (qubits). Quantum computers share theoretical concepts with probabilistic computers and non-deterministic. A quantum computer with spins as quantum bits was also formulating for use as a quantum space time. Both theoretical and practical research continues in nowadays also to development of actual quantum computers. Military agencies and a many national governments are funding quantum computing research to develop quantum computers for business, civilian, national security purposes such as cryptanalysis and trade. The advancements in the field of CMOS technology have promoted a continuous increase in the density of integration as well as in the frequency of operation of the VLSI ICs.

2 96 Quantum computers will solve certain problems more quickly than any classical computer, upon currently using algorithms in different application, and integer factorization using Shor's algorithm and exist quantum algorithms, such as Simon's algorithm, probabilistic classical algorithm. A classical computer to simulate any quantum algorithm with sufficient computational resources, and does not violate the Church Turing thesis. Quantum logic gates can implement all Boolean functions using only reversible gates (ex-toffoli gate), it perform all operations of Boolean functions. This gate has a quantum equivalent circuits can perform all operations, with low power consumption. Quantum circuit specifically using in quantum computing, operation on a small number of qubits. A quantum logic gate is a basic quantum circuit with the building blocks as like classical logic gates of digital circuits. An unitary matrices describes the quantum gates by 2 2 or 4 4 matrices, so quantum gates are represented by unitary matrices and operate on spaces of one or two qubits. Classical Logic vs Quantum are quantum models for computation, to research reversible models, an exploration of the ultimate limits of computation and the motivation was mostly academic at the time. Quantum computing not introduce until 1994, Shor announced his algorithm for factoring large numbers with greater efficiency unparallel by any classical algorithm. In cryptography, encrypt messages with help of factoring large numbers; the time of factoring problem is arose in classical design flow. Therefore, quantum computing made the feasibility on factoring problem. Here we will address the issues in quantum computing, that of qualitative differences between quantum and the classical models for computation and a quantum model for computation. Shor s quantum algorithm achieved factoring numbers through quantum computation and researcher works on arbitrary unitary operations to down into simpler ones. A quantum logic gates operate on qubits, which are able to simulate arbitrary unitary operations like classical logic. A property of unitary matrices having a product

3 97 of unitary logic gate and two of them remains unitary. We introduce the universal quantum logic gates, the XOR, the NOT gate and the Walsh- Hadamaard gates. Shor's algorithm can implemented in the number of elementary operations is polynomial in the length of its input measured in bits and factoring a binary number of N-bits, which scales exponentially with the input size. Shor s algorithm introduces to overcome multiplying of large prime numbers, due to absence of inefficient classical algorithm for the factorization of large number. The performance of quantum circuit operations is increasing importance to calculate a factor; we conform to which type of computer suitable to execute factorial functions in quantum computation, for example, cryptograph and RSA-896, etc. A classical algorithm needs the quadratic equation by using the sieve (exp (( ) (lnn) )) to scale input size bits exponentially. On a quantum computer, Shor's algorithm executes multiplication sequence in polynomial time in log N, to factor an integer N. A modular exponentiation increase efficiency of Shor s algorithm by squaring repeated manner and similarly quantum Fourier transform are also squared. It is well known that factoring N can be reduced to the task of choosing at random an integer m relatively prime to N, and then determining it s modulo N multiplicative order P, i.e., to finding the smallest positive integer P such that m P = 1 mod N. Let N = {0, 1, 2, 3,.} denote the set of natural numbers. Shor s algorithm provides a solution to the prime factorization problem. Shor s algorithm consists of five steps (steps 1 through 5), with only step 2 requiring the use of quantum computer. The remaining four steps of the algorithm are to be performed on a classical computer. Step 1: Choose a random positive integer m. Use the polynomial time Euclidean algorithm [is O (ln(n)) ] to compute the greatest common

4 98 divisor gcd (m,n) of m and N. If the greatest common divisor gcd (m, N) 1, then non trivial factor of N is found. If, on the other hand, gcd (m, N ) = 1 then proceed to next step. Step 2: Use a quantum computer to determine the unknown period P of the function. Where, N and a m a mod N Step 3: If p is an odd integer, then go to step 1. [ The probability of P being odd is (1/2) k, where k is the number of distinct prime factors of N] is Pis even, then proceed to next. Step 4: If P is even, then ( m p/2-1) ( m p/2 +1) = m P -1 = 0 mod N. If m p/2 +1 = 0 mod, then go to step 1. If m p/ mod N, then proceed to step 5. Step 5: Use the Euclidean algorithm to compute d = gcd( m p/2-1, N). Since m p/ modn, it says that d is a non trival factor of N. Exit with the result of d. To implement digital circuits with low power is most important consideration for VLSI designer at chip level and performance of design with power dissipation are important factor. A dynamic power and Static power being the main parameters to determining the power consumption in CMOS design circuits. Reversible logic introduce in the promising analysis of circuit style and has found its applications in low power CMOS style, digital signal process, cryptography, optical scientific discipline and engineering and economically implemented in all combinational and sequential circuits (one clock cycle) as like conventional logical gates. In future, to increasing operations speed of portable devices, technology advances in all level of design circuits to measure its power and latency and its execution over fast algorithms and noise in high speed ICs. To implement reversible logic gates within the sense to synthesize any whimsical mathematician functions through the gates

5 99 planned to form all functions. In recent years, Reversible logic has received good attention in low power VLSI style with ability dissipation of energy and increase demand on wide applications in low power CMOS and polymer computing, quantum computation, Optical informatics and engineering science. Over the few decades, researchers are concentrate on power consumption of VLSI chips has been continuously increasing. The need for low-power design is becoming an essential parameter in high-performance digital systems. Irreversible logic hardware computation ends up in data loss due to energy dissipation attribute. The hardware quality of gates is a smaller amount and needs just one clock cycle by compared to the conventional ones. Gates is wont to understand any non-mandatory Boolean perform and consequently universal. The quantum realization is simply high value and preparation are been used in current engineering science. An ancient combinatory logic style approaches different from reversible logic style; the amount of input lines and the amount of output lines are equal and the ensuing circuit should be acyclic and every output are used just the once. A garbage outputs are find in square measure, that don't seem to be used in the output lines and difficult tasks is to cut back these garbage s. Any reversible gate realizes utterly that Boolean functions don't seem to be reversible and value realizes square measure reversible. Before realizing reversible logic functions, we first remodel those irreversible functions into reversible one and using transformation formula that converts Irreversible perform to a reversible one followed input lines that square measure set to zero within the circuit s input, measure inputs square as constant inputs. To achieve economical design circuits reversible logic style ought to constant inputs and minimize the garbage s. Computing systems amendment from positive and negative with voltage levels and binary form of bits from 1 to 0 and amendment reversible circuit components can bit by bit move charge from one node to ensuing, within the type of heat, instead of dynamical

6 100 voltages to new levels and expect to lose a moment quantity of energy on every transition. Digital logic styles powerfully designed with help of reversible computing to minimize the power and energy consumption. Reversible logic components applied the state of inputs from the outputs and component required square measure to calculate recover values from inputs to outputs, which great impact on high-level programming languages and instruction sets. Eventually, these also will need to be reversible to supply optimum potency. High-performance chips purgative massive amounts of affability impose sensible limitation on nevertheless so much will we have an inclination to improve the performance of the system. Reversible circuits that preserve info, by world organization computing bits rather than propelling them away, can shortly supply the sole physically feasible thanks to keep rising performance. Reversible computing will cause improvement in energy potency. Energy potency can have an effect on the speed of circuits like nano-circuits and so the speed of most computing applications. To extend the operations of devices once more reversible computing is needed to apply in design circuits. Let circuit component sizes to restore to atomic size limits and therefore devices will become additional, though the hardware style prices sustain in close to future is also high. However, performance and the facility value being additional ascendant than logic hardware value in today s computing era. This helps to see the outputs from the inputs and conjointly the input is unambiguously recovered from the outputs. Conjointly within the synthesis of reversible circuits, direct fan-out is not allowed as one to-many thought is not reversible, but fan-out in reversible circuits is achieved mistreatment further gates. A reversible circuit ought to be designed mistreatment minimum variety of reversible logic gates. From the purpose of reversible circuit style, there square measure several parameters for crucial the quality and performance of circuits.

7 101 The quantity of Reversible gates (N): the quantity of reversible gates employed in circuit. The quantity of constant inputs (CI): This refers to the quantity of inputs that square measure to be maintained constant at either zero or one to synthesize the given logical operate. The number of garbage outputs (GO): This refers to the quantity of unused outputs gift in an exceedingly reversible logic circuit. One cannot avoid the rubbish outputs as this square measure terribly essential to realize changeableness. The reversible circuits type the essential structures of coming up with quantum computers. The primitive reversible gates that are gathered from the references and the coming up with of complicated circuit s mistreatment reversible gates. The paper will any be extended towards the digital style development mistreatment reversible logic circuits with pass junction transistor logic helps to form an occasional power circuits. Reversible computing could have applications in pc security and dealings process, however the most long profit are going to be felt alright in those areas that need high energy potency, speed and performance, it embody the world like Low power CMOS, Quantum PC, Nano-technology, Optical computing, Style of low power arithmetic and knowledge path for digital signal process (DSP) and Field Programmable Gate Arrays (FPGAs) in CMOS technology for very low power, high testability and self-repair. Low Power digital CMOS becomes more interesting and general advances in process technology and new applications implement in low power. As technology advances the power consumption and noise, smaller devices and faster operations become severe problems when designing high speed ICs. In this era of technology and advancement power consumption has become an important factor of consideration. Here we reduced the power consumption of 2 to 8 decoder by using reversible logic. Reversible logic finds its application in quantum computing, nanotechnology, low power VLSI. In the irreversible logic for the loss of each bit of information proposed that KTlog2 joules of energy is dissipated, where K is Boltzmann s constant and T represents temperature. This amount of heat is

8 102 very small in simple circuits but it becomes large in complex circuits. Reversible logic involves the use of reversible gates which have same number of inputs and outputs and they can be made to run in backward direction also. Each input in the circuit is associated with some energy. If a bit is lost, that is number of bits at the output are less as compared to the inputs,then energy associated with the corresponding bit is dissipated in the form of heat. Since in reversible circuits no bit loss is there hence ideally in reversible circuits no power dissipation occurs. But practically some power dissipation does occur, which is much less than the conventional logic. The extra output used in order to make inputs and outputs equal are called garbage outputs. The circuit should be designed in such a manner to keep these outputs are minimum. However, in certain reversible circuits constant inputs are also used. These constant inputs are set either to logic 1 or to logic 0 depending upon the operation of the circuit. Reversible gates differ from the conventional logic gates in terms of above two factors. A system-level design trade-offs were required in order to provide the Spartan-3A/3AN Starter Kit board with the most functionality. 7.2 Spartan-3AN FPGA Typical FPGA app uses memory to store configuration images. To demonstrate new Spartan-3A and Spartan-3AN FPGA capabilities, the starter kit board has four different configuration memory sources that all function work together. The additional configuration makes the kit board trickier than typical FPGA applications. The starter kit board also has a built in USB-based JTAG programming interface. The on-chip circuitry simplifies the device programming experience. For other applications, the JTAG programming uses off-board or a separate programming module, Xilinx Platform USB cable. The Spartan-3A/3AN FPGA typically operates with two supply rails, 1.2V and 3.3V. The Spartan-3A/3AN Starter Kit board showcases a quadrupleoutput regulator developed by National Semiconductor specifically to power

9 103 Spartan-3 generation FPGAs. This regulator is sufficient for FPGA applications. Spartan-3AN FPGAs require VCCAUX to be 3.3V whereas Spartan-3A FPGAs accepts VCCAUX to be 2.5V or 3.3V. The Spartan-3A/3AN Starter Kit Board uses a default VCCAUX of 3.3V. Spartan-3A and Spartan-3AN FPGAs have different availability. FPGA configuration storage Micro Blaze code storage/shadowing 8 x8 or x17 data interface after configuration Two 17 M bit SPI serial Flash STMicroelectronics and Atmel Data Flash serial architectures FPGA configuration storage Supports single configuration bit stream or multiple Multi Boot configuration bit streams Nonvolatile data storage Micro Blaze code shadowing Two-line, 17-character LCD screen PS/2 port Supports PS/2-compatible mouse or keyboard Supports both mouse and keyboard using a Y-splitter cable (not included) VGA display port, 12-bit color 10/100 Ethernet PHY (requires Ethernet MAC in FPGA) Two nine-pin RS-232 ports (DTE- and DCE-style) On-board USB-based programming solution FPGA download/debug

10 104 SPI serial Flash in-system direct programming 50 MHz clock oscillator 8-pin DIP socket for second oscillator SMA connector for clock inputs or outputs 100-pin Hirose FX2 expansion connector with up to 43 FPGA user I/Os Compatible with Digilent FX2 add-on cards High-speed differential I/O connectors Receiver: Six data channels or five data channels plus clock Transmitter: Six data channels or five data channels plus clock Supports multiple differential I/O standards, including LVDS, RSDS, mini-lvds Also supports up to 24 single-ended I/O Uses widely available 34-conductor cables Two six-pin expansion connectors for Digilent Peripheral Modules Four-output, SPI-based Digital-to-Analog Converter (DAC) Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain pre-amplifier Stereo audio jack using digital I/O pins Chip Scope Soft Touch debugging port Rotary-encoder with push-button shaft Eight discrete LEDs Four slide switches Four push-button switches

11 105 We implement Reversible logic gates in FPGA, to verify area, time, delay, power consumption and functionality of inputs. The Spartan-3AN FPGA platform offers nonvolatile pin-compatible versions of the Spartan-3A FPGA platform. The Spartan-3AN FPGAs support the same external programming sources as Spartan-3A FPGAs, but add an additional internal SPI Flash programming mode. The internal SPI Flash can also be used for user data. TheSpartan-3A/3AN Starter Kit Board supports both external and Spartan-3AN internal configuration options. 7.3 Basic Reversible Logic Gates Everyday a new technology which is being faster, smaller and complex than the previous version is being developed. The increase of clock frequency to attain great speed and increasing in the number of transistors on to a single chip resulting in complexity of conventional systems ought to conceive a large power. Almost all the gates involved to perform logical functions in conventional computers are really irreversible. Due to less heat dissipating capacity reversible logic is gaining a lot interest in past and recent times. That is when every new information is passed the old data are erased by dissipation of heat. It is seen that reversible logic has a wide range of applications in upcoming emerging technologies such as quantum dot cellular automata, optical computing, quantum computing, DNA computing to produce zero power dissipation under ideal conditions. As well as ultra low power VLSI circuits. Reversible logic is seen that have very essential in fields like in the construction of arithmetic circuits used in quantum computation, nano technology and other low power digital circuits. Recently, several new researchers have focused their objective on the synthesis of efficient reversible logic circuits and design. Feynman Gate, New Gate and Fredkin gate are the important reversible gates which are used for reversible logic synthesis. The Reversible implementations are also seemed to be found in adiabatic CMOS and thermodynamics. Power dissipation in latest technologies

12 106 is found to be an important problem, and excess heating is a serious concern for both manufacturer (smaller scale technologies, impossibility of introducing new, limited temperature range for operating the product) and customer (power supply, which is especially important for mobile systems). The combinational circuits have been done with VHDL CODE of these circuits and are the basic reversible logic gates. The simulations can be done using VHDL and Verilog HDL for all the combinational circuit of every basic reversible logic gates can be verified by it. It can be found that computational sates can never be lost, so that we can recover any earlier stage by computing it backwards or by also un-computing the results it can be done by use of reversibility in computing. This is termed as logical reversibility. The advantage of logical reversibility provides its output only after implementing physical reversibility. No energy to heat dissipation is the process of Physical reversibility. It is seen that achieving perfect physical reversibility is practically impossible. When voltage levels change from positive to negative computing systems generates heat: bits from zero to one. Rather than converting voltages to new levels, moving the charge from one node to the next can be done gradually by use of reversible circuit elements. By this way, a minute amount of energy on each transition is dissipated. Digital logic designs are strongly affected by Reversible computing. To get the actual state of inputs from the outputs reversible logic elements are needed. It will also impact high-level programming languages and instruction sets as well. Eventually, these will also have to be reversible to provide optimal efficiency. 7.4 Synthesis of Reversible Logic Circuits A practical limitation are imposed releasing large amounts of heat on high-performance chips on how far can we improve the performance of the system. Reversible circuits which are suppose to conserve information; instead of throwing them away it is done by un-computing bits, which will soon offer

13 107 the one and only physically possible way to improve the performance. Energy efficiency improvement will be done by reversible computing. The speed of circuits will be fundamentally affected by energy efficiency such as nanocircuits and therefore the speed of most computing applications. To improve the easy handling of devices again reversible computing is required. The size of circuit element will be reduced to size of atomic limits and hence the devices will become more portable. Although the hardware design costs calculated in near future may be comparatively high but the performance and power cost being more advanced than the cost logic hardware in today s computing era, it is seen that the need of reversible computing cannot be ignored. A reversible logic gate is an input and output logic device with mapping one input to other to form maximum number outputs which helps to implemented huge circuit with few number of gates and also achieve important parameter of power dissipation. This helps to determine the outputs from the inputs and also the inputs can be uniquely recovered from the outputs. To overcome an-out issues in reversible circuits, need to add an additional number of gates. A reversible logic circuit designed using less number of reversible logic gates. From the point of view of reversible circuit design, there are many parameters for determining the complexity and performance of circuits. i. Reversible gates (N): The reversible gates used in circuit to reduce quantum cost. ii. iii. The constant inputs (CI): This refers to the inputs number that is to be maintained constant at either 1 or 0 to synthesize the given logical function. The garbage outputs (GO) number: This refers to the unused outputs number present in a reversible logic circuit. In reversible logic circuit design cannot avoid the garbage outputs, it depends upon condition applied into reversible gate and very essential to achieve reversibility.

14 108 iv. Quantum cost (QC): This refers to the circuit cost in terms of a primitive gate cost and calculated the primitive reversible logic gates number 1*1 or 2*2 required to realize the circuit. 7.5 Quantum Gates Feynman Gate Feynman gate is a reversible gate is shown in figure 7.1, with its gate structure and Quantum implementation. Feynman gate having inputs based on design implementation like 2*2 input and output vectors. The input vectors is (A,B) and output vectors is (P,Q). The outputs of reversible gates are depends on three input vectors and its output vectors is P=A, Q=A B output is defined with Quantum cost is 1. Feynman gate of fan-out is not allowed and it acts as a copying gate useful for duplication of the required outputs. Figure 7.1 Feynman Gate and Quantum Logic Table 7.1 Truth Table of Feynman Gate A B P Q

15 Double Feynman Gate (F2G) Double Feynman gate is a reversible gate is shown in figure 7.2, with its gate structure and Quantum implementation. Double Feynman gate having inputs based on design implementation like 3*3 input and output vectors. The input vectors are (A, B, C) and output vectors are (P, Q, R). The outputs of reversible gates are depends on three input vectors and its output vectors is P=A, Q=A B and R=A C output is defined with Quantum cost is 2. Double Feynman gate of fan-out is not allowed and it acts as a copying gate useful for duplication of the required outputs. Figure 7.2 Double Feynman Gate and Quantum Logic Table 7.2 Truth Table of Double Feynman Gate A B C P Q R

16 Toffoli Gate Toffoli gate is a reversible gate is shown in figure 7.3, with its gate structure and Quantum implementation. Toffoli gate having inputs based on design implementation like 3*3 input and output vectors. The input vectors is (A, B, C) and output vectors is (P,Q, R). The outputs of reversible gates are depends on three input vectors and its output vectors is P=A, Q=B and R=AB C output is defined with Quantum cost is 5. Figure 7.3 Toffoli Gate and Quantum Logic Table 7.3 Truth Table of Toffoli Gate A B C P Q R

17 Fredkin Gate Fredkin gate is a reversible gate is shown in figure 7.4, with its gate structure and Quantum implementation. Fredkin gate having inputs based on design implementation like 3*3 input and output vectors. The input vectors is (A, B, C) and output vectors is (P,Q, R). The outputs of reversible gates are depends on three input vectors and its output vectors is P=A, Q=A B AC and R=A C AB output is defined with Quantum cost is 5. Figure 7.4 Fredkin Gate and Quantum Logic Table 7.4 Truth Table of Fredkin Gate A B C P Q R

18 Peres Gate Peres gate is a reversible gate is shown in figure 7.5, with its gate structure and Quantum implementation. Peres gate having inputs based on design implementation like 3*3 input and output vectors. The input vectors is (A,B,C) and output vectors is (P,Q,R). The outputs of reversible gates are depends on three input vectors and its output vectors is P = A, Q = A B and R=AB C output is defined with Quantum cost is 4. Figure 7.5 Peres Gate and Quantum Logic Table 7.5 Truth Table of Peres Gate A B C P Q R

19 Implementation and Simulation Reversible Half Subtractor The TR gate as a reversible half subtractor. As shown in Fig.7.6, the TR gate implements the reversible half subtractor with quantum cost of 4, delay of 4 and 0 garbage outputs (the inputs regenerated at the outputs are not considered as garbage outputs). Thus design achieves 43% reduction in terms of quantum cost (QC) and delay compared to design, while the improvement is 33% in terms of the quantum cost (QC) and the delay compared to design. Figure 7.6 Reversible Half Subtractor Figure 7.7 Implementation of Reversible Half subtractor

20 114 Table 7.6 Truth Table of Reversible Half Subtractor A B Borr Diff We have functionally verified the working of the proposed quantum implementation of the TR gate. The output P of the TR gate is equal to A and the output Q is equal to A XOR B thus the functionality of the outputs P and Q is easy to verify. The path of the outputs Q consists of V + and V gates thus cannot be directly verified. In order to verify the output R, we use the truth table of the TR gate and compare the expected output with the output produced. For the path from input C to output R, the controlled signals of V + and V gates are labeled as C1,C2 and C3 as shown in Figure 7.7. A small illustration of the verification of the output R for two input combinations in which the inversion and identity properties of V and V + gates will be utilized (the properties of V and V + gates working as an NOT gate and identity gate. Figure 7.8 RTL Schematic View 1 of Reversible Half Subtractor

21 115 Figure 7.9 RTL Schematic View 2 of Reversible Half Subtractor Figure 7.10 RTL Schematic View 3 of Reversible Half Subtractor Figure 7.11 RTL Schematic View 4 of Reversible Half Subtractor Let a1 and b1 are two binary numbers. The half subtractor performs A-B operation. Table 7.6 shows the truth table of the half subtractor. The output of the XOR gate produces the difference between A and B. The output of the AND gate A B produces a Borrow. Thus, the output function will be Borrow= A B ; Difference= A xor B. The quantum half subtractor as shown in Fig 7.11 is designed from 2 CNOT gates (2 Feynman gates) and 1 Toffoli gate. The design is the most widely used design of quantum half subtractor. The reversible half subtractor, while the quantum cost of 7 and delay of 7. In we propose the reversible half subtractor design based on a new quantum

22 116 implementation of the reversible TR gate. The reversible TR gate is a 3 inputs 3 outputs gate having inputs to outputs mapping as (p1=a, q1=a xorb, r1 = A B as shown in Fig The implementation of the TR gate with 2x2 reversible gates is shows that the proposed TR gate has quantum cost of 4 and delay of 4. It is to be noted that the upper bound on the quantum cost of the TR gate was estimated. Figure 7.12 Output Waveform of Reversible Half Subtractor Figure 7.13 Design Summary of Reversible Half Subtractor

23 117 Figure 7.14 Coding for half subtractor using reversible logic gates Figure 7.15 Implementation output of reversible half subtractor

24 118 Power delay for conventional model and its reversible logic gates using FPGA is tabled below in table 7.7. Table 7.7 Power delay comparison of half subtractor Parameter CMOS based subtractor Reversible logic gates based subtractor No. of Slices 1 1 No. of 4 input LUT 2 2 No. of bonded IOB 5 4 Delay (watt-sec) 8.515E E-12 Time (nano-sec) Figure 7.16 shows power delay output of reversible half subtractor Reversible Full Subtractor To subtract three binary numbers, one can use a full subtractor which realizes the operation Y=A-B-C. The truth table of the full subtractor is shown in Table 7.8. This gives the equation of the borrowand difference as follows:

25 119 Difference= (A XORB)XORC; Borrow = AAND(B XOR A)XOR(B ANDC). In the reversible full subtractor is designed with 2 Toffoli gates, 3 Feynman gates and 2 NOT gates. Thus, reversible full subtractor has the Quantum cost of 15, delay of 15. In this work, we propose the design of the reversible full subtractor in Fig It requires two TR gates to design a reversible full subtractor with zero garbage outputs. The quantum realization of the TR gate based reversible full subtractor is shown in Fig We can see that the TR gate based reversible full subtractor has the quantum cost of 8 with delay of 8. As the fourth gate (V gate) and the fifth gate (V + gate) are in series thus forming an identity and c1an be removed. This results in a new optimized design of TR gate based reversible full subtractor with quantum cost of 7 and delay of 7. Thus, the proposed reversible full subtractor design based on TR gate has an improvement ratio of 70% both in terms of number of quantum cost (QC) and delay, the improvement is 50% in terms of the quantum cost and the delay. Figure 7.17 Reversible Full Subtractor Figure 7.18 Optimized Quantum Implementation of TR Gate Based Reversible Full Subtractor

26 120 Table 7.8 Truth table of Reversible Full Subtractor A B C Borr Diff Figure 7.19 RTL Schematic View 1of Reversible Full Subtractor Figure 7.20 RTL Schematic View 2 of Reversible Full Subtractor

27 121 Figure 7.21 RTL Schematic View 3of Reversible Full Subtractor Figure 7.22 RTL Schematic View 4of Reversible Full Subtractor Figure 7.23 RTL Schematic View 5of Reversible Full Subtractor 1) Consider the case when inputs ABC to have value 101. Now we have A=1, B=0 and C=1 thus control signals C1, C2 and C3 will have values as C1=0, C2=1 and C3=1, thus first V + gate will not play the controlling role and will just work as a wire transferring the input C. The second and third V gates will be active playing the controlling role resulting in a NOT gate (two V gates in series work as a NOT gate). Thus at output R. we will have the inverted value of C resulting in the value at output R as 0. From the logic equation the output R is R = A B C which also produce the value as 0. This verifies the working of the quantum implementation of the TR gate for inputs ABC to have value 101.

28 122 2) Consider the case when inputs ABC to have value 111, we have A=1, B=1 and C=1 thus control signals C1, C2 and C3 will have values as C1=1, C2=1 and C3=0. The second V gate will not play control role since control signal C3 is 0, the first V + and third V + gate will form an identity resulting in value of input c passed to output R producing R=C. Thus the output R will be 1. From the logic equation R is R = A B xor C which also produce the value as 1. This verifies the working of the quantum implementation of the TR gate for inputs ABC to have value 111. Similarly, the proposed design is tested for all 8 inputs combinations and it matches the expected output. Figure 7.24 Output Waveform of Reversible Full Subtractor Figure 7.25 Design Summary of Reversible Full Subtractor

29 123 Figure 7.26 Implementation output of Reversible Full Subtractor using FPGA Figure 7.27 Coding for full subtractor using reversible logic gates

30 124 Table 7.9 Power delay comparison of full subtractor Parameter CMOS based full subtractor Reversible logic gates based full subtractor No. of Slices 1 1 No. of 4 input LUT 2 2 No. of bonded IOB 7 5 Delay (watt-sec) 8.47E E-12 Time (nano-sec) Figure 7.28 Power delay output of full subtractor using reversible logic Two-Bit Binary Comparator Using Reversible Logic Modern digital circuit designing is now focusing on the reversible circuits and designing of low power loss circuits in the area of nanotechnology, quantum computing, optical computing, signal processing etc. A two-bit binary comparator designed using reversible logic gates such as Feynman, TR, URG, Toffoli and BJN gates. Comparator circuit is achieved through optimization of total number of garbage outputs generated and total number of gates used in the

31 125 circuit. Proposed circuits have been simulated and implemented using Xilinx Spartan 3AN FPGA platform. Conventionally digital circuits were generally made up of logic gates which were irreversible in nature and irreversible gates loss the information bits during the operation it causes produce energy. A total number of output signals generated less than is total number of input signals applied that time information loss occurs. In reversible circuits conventional logic gates were used for designing which were irreversible in nature, whereas in reversible logic these design entities are replaced by basic reversible logic gates. Reversible circuit designing is added advantage widely in the area of advanced computing, Quantum computing, low power CMOS design, nanotechnology, etc due to its ability to design low loss or approximately lossless circuits. Reversible logic gates are (n, n) logic gates where (n,n) refers to the (number of input signals, number of output signals). In reversible gates input signal can be formulated by knowing the output signals. Reversible logic approach can optimize the design entity with less number of gates. The reversible circuits having few key issues from gates are the garbage output signals generation is minimized. Above comparator compares two 2-bit numbers A and B and generate the comparison result in the form of three signals F =A.B +A.B.B +A.A.B (7.1) F =.A A.B.B +A.A.B.B +A.A.B.B (7.2) = (7.3)

32 126 Figure 7.29 Logic Diagram For Reversible 2-Bit Comparator Table 7.10 Truth Table For Reversible 2-Bit Comparator A0 A1 B0 B1 A>Y A=B A<B

33 127 The base of optimization is total reversible gates used and garbage outputs generated. Optimized Comparator circuit (shown in figure 4) has 9 total reversible gates used and 10 unused outputs generated. This design can be employed in low power logical design applications. The most optimized reversible 2-bit comparator circuit is shown in figure This design uses a combination of Feynman gate, a (2, 2) reversible gate and TR, URG and BJN gates which are (3, 3) reversible gates. In this optimized design TR gates are used in input stage and outputs are derived from TR, Feynman gates. It has been further simplified and all three outputs have been derived from BJN gate. Here total gates used are garbage output generated is 9 and 10. Figure 7.30 RTL schematic view 1 of Two-Bit Comparator Figure 7.31 RTL Schematic 2 View of Reversible 2-bit magnitude comparator

34 128 Figure 7.32 RTL Schematic 3 View of Reversible 2-bit magnitude comparator Figure 7.33 RTL Schematic 4 View of Reversible 2-bit magnitude comparator Figure 7.34 RTL Schematic 5 View of Reversible 2-bit magnitude comparator

35 129 Figure 7.35 Output Waveform of Reversible 2-bit magnitude comparator Figure 7.36 Design Summary of Reversible 2-bit magnitude comparator

36 130 Figure 7.37 Implementation of 2 bit comparator using reversible logic gates, SPARTAN-3AN Figure 7.38 Coding for 2 bit comparator using reversible logic gates

37 131 Figure 7.39 FPGA output of 2 bit comparator Power delay for conventional CMOS model and its reversible logic model using FPGA is tabled below in table in Table 7.11 Power delay comparison of 2 bit comparator Parameter CMOS based subtractor Reversible logic gates based subtractor No. of Slices 4 2 No. of 4 input LUT 8 3 No. of bonded IOB 14 7 Delay (watt-sec) 11.03E E-12 Time (nano-sec)

38 132 Figure 7.40 Power delay output of 2 bit comparator Reversible 3 to 8 Decoder The reversible logic synthesis for the n-to-2 n decoder; where n is the fault tolerant Feynman double gate and Fredkin gate. Thus, the entire scheme inherently becomes fault tolerant. Shor s Algorithm for designing the generalized decoder has been presented. Figure 7.41 Logic diagram of 3 to 8 reversible fault tolerant decoder

39 133 Table 7.12 Truth Table of 3-to-8 Reversible Fault Tolerant Decoder A B C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q The Reversible Decoder is specially designed for reduce the power dissipation in the decoder circuit; where as conventional decoder is `acts as normal decoder without any logical expression to reduce the power consumption. A decoder is a combinational circuit used in many devices for signal processing. To overcome the drawbacks of conventional decoder, a reversible decoder is proposed. Reversible Fault Tolerant Decoders are plays important role on reversible logic gates. These Decoders are worked on to find out the fault occurs either at output or input side. Figure 7.42 RTL schematic view 1 of 3-to-8 reversible fault tolerant decoder

40 134 Figure 7.43 RTL schematic view2 of 3-to-8 reversible fault tolerant decoder Figure 7.44 RTL schematic view3 of 3-to-8 reversible fault tolerant decoder Figure 7.45 RTL schematic view4 of 3-to-8 reversible fault tolerant decoder Figure 7.46 RTL schematic view5 of 3-to-8 reversible fault tolerant decoder

41 135 Figure 7.47 RTL schematic view6 of 3-to-8 reversible fault tolerant decoder 3-to-8 RFD also designed by using the Fault tolerant gates. In 3-to-8 RFD, we can use the both reversible fault tolerant gates. It can be designed by using the output of 2-to-4 RFD. Normally, in all reversible decoders, it requires only single Feynman double gates as shown in Fig In Feynman Double gate it requires a more no of transistors and low quantum cost, delay will be high. To overcome, these drawbacks we can use the Fredkin gates. By using Fredkin gates in reversible decoder, it produces high quantum cost and less delay. For the design procedure of 3-to-8 RFD, it realizes four Fredkin gates respectively. In 3-to-8 RFD, it requires only Fredkin gates and output of 2-to-4 RFD. It follows the same principle of Normal decoder i.e., it takes "3" data inputs and produces the 2^n i.e.,(2^3) is equal to "8" outputs. Figure 7.48 Output Waveform of 3-to-8 Reversible Fault Tolerant Decoder

42 136 Figure 7.49 Design Summary of 3-to-8 Reversible Fault Tolerant Decoder Figure 7.50 Coding for 3 to 8 Reversible Fault tolerant Decoder

43 137 Figure 7.51 Implementation output of 3 to 8 RFT Decoder Power delay for conventional CMOS model and its reversible logic model using FPGA is tabled below in table in Table 7.13 Power delay comparison of 3 to 8 RFT decoder Parameter CMOS based decoder Reversible logic gates based decoder No. of Slices 6 4 No. of 4 input LUT 10 8 No. of bonded IOB Delay (watt-sec) 9.351E E-12 Time (nano-sec)

44 138 Figure 7.52 Power delay output of 3 to 8 RFT decoder 7.7 Chapter Summary We demonstrate real time implementation of single electron transistor (SET) in Quantum logic to reduce power consumption and dissipation in flow electrons, when we design logic in transistor level. In this summary, we conclude that implementation of quantum logic with single electron transistor in Field programmable gate array, its shows area occupied in gate-level design and bring out parameter of power, delay; area depends upon the logic implemented in FPGA. With help of Xilinx Software, we achieve all process effectively. We analyzed the input and output characteristics of logic to correct functionality and variation of logic. We form RTL schematic for every logic which is implemented such as Reversible half and full subtractor, Reversible 2- bit magnitude comparator and Reversible 3-to-8 fault tolerant decoder.