E/E issues will result in increase in walk home events. Other Costs of Failure Examples

Transcription

1 Autmated Design Analysis: Cmprehensive Mdeling Circuit Card Assemblies Dr. Randy Schueller and Cheryl Tulk Senir Members the Technical Sta, DR Slutins Abstract It is widely knwn and understd that the verall cst and quality a prduct is mst inluenced by decisins made early in the design stage. Finding and crrecting design laws later in the prduct develpment cycle is extremely cstly. The wrst case situatin is discvering design prblems ater ailures ccur in the ield. Designing r reliability has been easier said than dne due in large part t the many cmpeting interests invlved in a design. Fr example, the designer is challenged with increasing the prduct perrmance while cntinually reducing the rm actr. The reliability engineer may raise cncerns abut design risks, but withut the ability t quantiy the ptential impact, they are ten unable t meaningully inluence the design decisins. Implementing a newly develped reliability predictin analysis tl, Sherlck, will rever change this equatin. Bere a single prduct is built, this valuable new tl enables the engineer t imprt the design iles and quantitatively predict the lie the prduct accrding t the assumptins made r the user envirnment. The ailure rate is predicted r thermal cycle atigue slder jints and plated thrugh hle vias as well as r shrting rm cnductive andic ilament (CAF) rmatin. The stware als prduces a inite element analysis the circuit bards shwing regins susceptible t excessive bard strain during vibratin r shck events. The greatest value cmes rm the ability the engineers t perrm varius what i scenaris t determine the impact any number design chices. What i I change the munt pint lcatins? What i I change the via diameters, the spacing, r the cpper thickness? What i I change the laminate thickness r material selected? What cmpnent is at highest risk ailure and what i I change its rmat? What is the reliability impact changing rm SnPb t SAC305 slder? Finally, nce the design has been ptimized t satisy the many cmpeting requirements, the stware can be used t predict the rate ailure ver the lietime the prduct. This inrmatin can then be used t mre accurately plan r the warranty csts. With margins shrinking in the electrnics industry, OEMs depend mre n prits rm extended warranties. Inaccurate lie predictin can cut heavily int this incme stream. Under-predictin the ailure rate will lead t cst verruns while verestimating ailure will mean lst business t cmpeting extended warranty plans and the setting aside unds that culd instead be used r urther prduct develpment. This paper will illustrate the capabilities and value that this new tl prvides t the varius unctinal units within an electrnics manuacturing cmpany. Reliability Assurance Reliability is the measure a prduct s ability t perrm the speciied unctin at the custmer (independent envirnment) ver the desired lietime. Assurance is reedm rm dubt and cnidence in the prduct s capabilities. Typical appraches t reliability assurance include gut eel, empirical predictins such as MIL-HDBK-217 and TR-332, industry speciicatins and test-in reliability schemes. Sherlck is reliability assurance stware based upn physics ailure algrithms. The mtivatin r using the stware lies in ensuring suicient prduct reliability. This is critical because markets are lst and gained ver reliability. Reputatins can persist r years r decades and hundreds millins dllars are at stake. Using an autmtive example, sme cmmn csts ailure: Ttal warranty csts range rm $75 t $700 per car Failure rates r E/E systems in vehicles range rm 1 t 5% in irst year peratin (Hansen Reprt, April 2005). Diicult t intrduce drive-by-wire, ther systemcritical cmpnents E/E issues will result in increase in walk hme events Other Csts Failure Examples Type Business LstRevenue/Hr Retail Brkerages $6,450,000 Credit Card Sales Authrizatin $2,600,000 Hme Shpping Channels $113,750 Catalg Sales Centers $90,000 Airline Reservatin Centers $89,500 Cellular Service Activatins $41,000 Package Shipping Services $28,250 Online Netwrk Cnnect Fees $22,250 ATM Service Fees $14,500 Supermarkets $10,000 Reliability and Design The undatin a reliable prduct is a rbust design. A rbust design prvides margin, mitigates risk rm deects, and satisies the custmer. Assessing and ensuring reliability during the design phase maximizes the return n investment (ROI). Fr cmparisn, deects and cst: Caught during design: 1x; Caught during engineering: 10x; Caught during prductin: 100x Caught at the custmer: 1000x Electrnic OEMs that use design analysis tls hit develpment csts 82% mre requently, average 66% ewer re-spins and save up t $26,000 in re-spins.

2 MTTF / MTBF Many cmpanies use mean time t ailure (MTTF) r mean time between ailures (MTBF) calculatins as their nly means assessing the reliability their prduct while in the design stage. MTTF applies t nnrepairable items while MTBF applies t repairable items. They are based n the expnential distributin: Distributin: F(t) = 1 e -λt Density (pd): (t) = λ e -λt Survival (s): S(t) = e -λt Failure rate: λ(t) = (t) / S(t) = λ e -λt / e -λt = λ MTTF: = 1 / λ (Mean Time T Failure) MTBF is typically calculated thrugh a parts cunt methd. Every part in the design is assigned a ailure rate. This ailure rate may change with temperature r electrical stress, but nt with time. Failure rates are summed and then inverted t prvide MTBF. Mst calculatins assume single pint ailure while sme calculatins take int cnsideratin parallel paths A variety handbks prvide ailure rate numbers. These include MIL-HDBK-217, Telcrdia, PRISM, 217Plus, RDF 2000, IEC TR 62380, NSWC Mechanical, Chinese 299B, HRD5. Sme cmpanies use internally generated numbers. sample size and des nt assume a ailure rate behavir (decreasing, increasing, steady-state). Deining Envirnments Meaningul reliability predictin must take int accunt the envirnment in which the prduct is used. There are several cmmnly used appraches t identiying the envirnment. Apprach 1 invlves the use industry/military speciicatins such as MIL-STD-810, MIL-HDBK-310, SAE J1211, IPC-SM-785, Telcrdia GR3108, and IEC The advantages this apprach include the lw cst the standards, their cmprehensive nature, and agreement thrughut the industry. I inrmatin is missing rm a given industry, simply cnsider standards rm ther industries. The disadvantages include the age the standards, sme are mre than 20 years ld, and the lack validatin against current usage. The standards bth verestimate and underestimate reliability by an unknwn margin. Figure 1 shws an example such a standard. MTBF/MTTF calculatins tend t assume that ailures are randm in nature and prvide n mtivatin r ailure avidance. And, it is very easy t manipulate numbers with tweaks made t reach desired MTBF such as mdiying quality actrs r each cmpnent. These calculatins are als requently misinterpreted. Example: A 50K hur MTBF des nt mean n ailures in 50K hurs. Basically these calculatins are a better it twards lgistics and prcurement, nt ailure avidance. Furthermre these calculatins d nt take int accunt wear ut mechanisms such as slder jint ailures, plated thrugh-hle atigue, r damage due t vibratin r shck events. Prcess Overview There are several high levels steps invlved in running the Sherlck stware. They are: Deine Reliability Gals Deine Envirnments Add Circuit Cards Imprt Files Generate Inputs Perrm Analysis Interpret Results Reliability Gals Desired lietime and prduct perrmance metrics must be identiied and dcumented. The desired lietime might be deined as the warranty perid r by the expectatins the custmer. Sme cmpanies set reliability gals based n survivability which is ten bunded by cnidence levels such as 95% reliability with 90% cnidence ver 15 years. The advantages using survivability are that it helps set bunds n test time and Figure 1 Industry standard envirnmental cnditins (IEC Anther apprach t identiying the ield envirnment is based n actual measurements similar prducts in similar envirnments. This gives the ability t determine bth average and realistic wrst-case scenaris. All ailure-inducing lads can be identiied and all envirnments, manuacturing, transprtatin, strage, and ield, can be included. In additin t thermal cycle envirnments, the Sherlck stware accepts vibratin and shck input as well. Figure 2 shws representatin this input. Identiy the number natural requencies t lk r within the desired requency range. Single pint r requency sweep lading is available and techniques are als available t equivalence randm vibratin t harmnic vibratin.

3 Vibratin lads can be very cmplex and may cnsist sinusidal (g as unctin requency), randm (g2/hz as a unctin requency) and sine ver/n randm. Vibratin lads can be multi-axis and damped r ampliied depending upn chassis/husing. shws an example a PCB stack-up and relevant data r reliability mdeling. Figure 2 Envirnmental priles inserted int stware r mdeling. Transmissibility The respnse the electrnics will be dependent upn attachments and stieners. Peak lads can ccur ver a range requencies including the standard range 20 t 2000 Hz and an ultrasnic cleaning range 15 t 400 khz. Vibratin ailures primarily ccur when peak lads ccur at similar requencies as the natural requency the prduct / design. Sme cmmn natural requencies: Larger bards, simply supprted: Hz Smaller bards, wedge lcked: Hz Gld wire bnds: 2k 4kHz Aluminum wire bnds: >10kHz Imprt Files The stware is designed t accept ODB iles which cntain all the data r the PCB, the cmpnents, and their lcatins. The data can als be imprted with Gerber iles and an individual bill materials. Figure 3 Figure 3. PCB Layer Viewer and relevant data.

4 Parts List Individual cmpnent data is part the ODB ile; hwever, mdiicatins t the data can be made manually t ensure the physical characteristics all the cmpnents are accurate. Figure 4 shws the cmpnent editr while Figure 5 shws the cmpnents laid ut n the bard. Stackup Laminate Database barrel vias (as shwn in Figure 6). The migratin ccurs thrugh the PCB laminate and nt n the surace (which is cnsidered a dierent deect mechanism). One actr that drives CAF is damage t the laminate surrunding the drilled via. This can ccur rm a dull drill bit, excessive desmear etching, r rm prly laminated layers. Envirnmental actrs that can increase the likelihd CAF rmatin are the vltage acrss neighbring vias, the spacing the vias, and high temperature/humidity cnditins. The stware evaluates the edge-t-edge spacing all the vias n the bard and estimates the risk CAF rmatin based n the damage arund each via as well as hw well the prduct was qualiied with CAF testing. Such vias can then be assessed t determine i there is a high vltage ptential between them r i they culd be expsed t high humidity cnditins. Figure 5 Laminate Manuacturers Figure 6 Laminate Types Figure 4. Parts List Package Database Editr Figure 6. Cnductive Andic Filament rmatin between vias within the PCB. Figure 5. Layer cmpnent editr. Analyses Six analyses are currently cnducted: CAF Cnductive Andic Filament Frmatin Plated Thrugh Hle Fatigue Slder Jint Fatigue Finite Element Simulatins: Natural Frequencies Vibratin Fatigue Mechanical Shck Cnductive Andic Filament (CAF) Frmatin Cnductive andic ilament rmatin is when electrchemical migratin cpper ccurs between tw PTH Fatigue Plated Thrugh Hle (PTH) Fatigue ccurs when a PCB experiences thermal cycling. The expansin/cntractin in the z-directin is much higher than that the cpper which makes up the barrel the via. The glass ibers cnstrain the bard in the x-y plane but nt thrugh the thickness s z-axis expansin can range rm ppm/c. As a result, a great deal stress can be built up in the cpper via barrels resulting in eventual cracking near the center the barrel as shwn in the crss sectin phts in Figure 7. Figure 7. PTH Fatigue Images

5 A validated industry ailure mdel r PTH atigue is available in IPC-TR-579, which is based n rund-rbin testing 200,000 PTHs perrmed between 1986 t This mdel used hle diameters 250 µm t 500 µm, bard thicknesses 0.75 mm t 2.25 mm and wall thicknesses 20 µm and 32 µm. Advantages include the analytical nature in using a straightrward calculatin that has been validated thrugh testing. Disadvantages include the lack wnership and validatin data that is apprximately 20 years ld. The mdel is unable t assess cmplex gemetries including PTH spacing and PTH pads that tend t extend lietime. It is als diicult t assess the eect multiple temperature cycles. Hwever, this assessment can be perrmed using Miner s Rule. The PTH equatins take int accunt the expansin ceicient, the thickness the PCB, the cpper thickness, the via diameter, and the glass transitin temperature. In additin t the series algrithms used t calculate the atigue lie PTHs, the quality the cpper plating is als taken int accunt. The PTH Quality Factr is a means estimating the quality the PTH abricatin prcess. This is a smewhat subjective determinatin. Rugh edges the cpper wall will prvide crack initiatin sites and wuld reduce the quality. On the ther hand, smth cpper walls alng with a surace inish such as ENIG wuld imprve the quality the PTH. An example a ailure curve r PTH thermal cycle atigue is shwn in Figure 8 alng with a list vias in rder their expected lie. Figure 9. Tabular PTH Fatigue Lie Data Slder Jint Fatigue Slder jint atigue ailures are becming mre prevalent due t the cntinued shrinkage slder jint size and pitch that cmes with mre advanced packages (Figure 10). The Sherlck stware takes int accunt the physical characteristics the package and the PCB t calculate the thermal cycle atigue lie the slder jints. The user can select eutectic tin-lead (SnPb), Lead-ree SAC 305 (Sn-3.0%Ag-0.5%Cu) r SN100C (SnCuNiGe). Additinal slders may be added in the uture and the slder may be speciied at the bard r at the cmpnent level. Figure 8. PTH Fatigue Lie Predictin Figure 10. Cycles t Failure r Varius Devices Slder Fatigue Mdel: Mdiied Engelmaier The mdiied Engelmaier mdel is used within the stware which is a semi-empirical analytical apprach using energy based atigue.

6 First, determine the strain range,, using: L C h D T s where C is a crrectin actr, L D is diagnal distance, a is CTE, T is temperature cycle, h is slder jint height. C is a unctin activatin energy, temperature and dwell time. L D is described urther. Da is a 2 a 1 and h s deaults t mm. Next, determine the shear rce applied t the slder jint using: 2 1 L T L D F D L D h s h c 2 E 1 A 1 E 2 A 2 A s G s A c G c 9 G b a where F is shear rce, L D is length, E is elastic mdulus, A is the area, h is thickness, G is shear mdulus, and a is edge length bnd pad. Fr the subscripts: 1 is the cmpnent, 2 is the bard, s is the slder jint, c is the bnd pad, and b is the bard. This mdel takes int cnsideratin undatin stiness and bth shear and axial lads. Leaded mdels include lead stiness. and using the energy-based mdel r SnP N W 1 The stware als has user verrides r slder atigue. These are lcated in the slder.csv ile. Validatin Mdeling Results A natural questin that is asked is hw accurate are the Sherlck mdeling results cmpared with actual data? T answer this, ver ne hundred mdels were run with individual cmpnents and the results cmpared with reliability data rm the literature. The results r QFN, QFP, and BGAs are shwn in Figure 11. The predicted results are n the x-axis and the mdeled results n the y- axis. A perect mdel wuld result in a diagnal line. Naturally, there is variatin in the results; hwever, r the mst part, the predicted results are within a 10% band the actual data. A larger scatter in data is seen r BGAs, as is typical experimental results r these cmpnents. Area A1 is thickness cmpnent (h1) x slder jint width and A2 is thickness bard (h2) x slder jint width. As is length slder jint (Ls) x slder jint width which deaults t 45% L D. Ac is the length the bnd pad (Lc) x slder jint width. Lc deaults t 60% L D. Remaining Parameters (h, G, v, a) Thickness: h s deaults t mm and h c deaults t mm Gs = Es / 2 x (1+v s ) where Es = Temperature dependent mdulus slder and v s = Gc = Ec / 2 x (1 + v c ) where Ec = 120 GPa and v c = 0.3. Gb = Ec / 2 x (1 + v b ) where Eb = 17 GPa and v b = a = A s. Then, determine the strain energy dissipated by the slder jint using: W 0.5 F A s Calculate cycles-t-ailure (N 50 ), using energy based atigue mdels r SAC develped by Syed Amkr: N W 1 Figure 11. Predicted thermal cycle results cmpared with mdeling results.

7 Unreliability Thermal cycle results are prvided as an unreliability plt that represents the cumulative reliability all the cmpnents n the circuit card assembly (CCA). An example is shwn in Figure 12. The stware will g a step urther and shw the rank rder the individual cmpnents and their respective reliability s that the weakest links are determined. Figure 13 shws an example the results table that is generated. When a prduct cnsists several CCAs, an unreliability ailure plt is prvided that takes int accunt all the assemblies. requency generated r the assembly based the munt pints used r the card. Figure 14. Mesh and Munt Pints Figure 12 Slder Jint Fatigue Lie Predictin (representing a very harsh underhd envirnment). Figure 15. Natural Frequency Displacement Figure 13. Sherlck Results Table Natural Frequency Analysis The Sherlck stware cntains an embedded inite element mdeling tl that allws the user t select the mesh size and angle. The FEA is used t calculate the natural requencies the CCA as well as the vibratin and shck behavir. An example the mesh created r a CCA is shwn in Figure 14, llwed by the 1 st natural Vibratin Fatigue Lietime under mechanical cycling is divided int lw cycle atigue (LCF) and high cycle atigue (HCF). LCF is driven by plastic strain and mdeled by Cin-Mansn. p -0.5 < c < -0.7; 1.4 < - 1 /c > 2 HCF is driven by elastic strain and mdeled by Basquin. b e N E < b < -0.12; 8 > - 1 /b > 20 2N c

8 Mechanical Lads (Vibratin) Expsure t vibratin lads can result in highly variable results since: Vibratin lads can vary by rders magnitude (e.g., g 2 /Hz t 1 g 2 /Hz) Time t ailure is very sensitive t vibratin lads (t W 4 ) Very brad range vibratin envirnments MIL-STD-810 lists 3 manuacturing categries, 8 transprtatin categries, 12 peratinal categries, and 2 supplemental categries Excessive Vibratin (JGPP) Randm Vibratin was deined as 9.8 t 28 Grms, 0.07 t 0.5 G 2 /Hz with a natural Frequency 72 Hz. With BGA s, SnPb slder always utperrmed lead-ree. The results were less cnclusive r leadless and leaded parts. Vibratin levels that are t high are mre representative lw-cycle atigue than high-cycle atigue. This amunt bard strain wuld crack ceramic capacitrs and the inrmatin caused quite a stir in the high reliability industries cncerning SAC slder. Realistic High Cycle Fatigue Testing High cycle atigue testing can take weeks n an electrdynamic shaker. Sme results such testing are shwn in Figure 16. Figure 76. Realistic High Cycle Fatigue Testing r SAC 305 Vibratin Interpretatin SAC slder is stier than SnPb slder. Fr a given rce per lad, SAC will respnd with a lwer displacement / strain, bth elastic and plastic. Lw-cycle atigue is plasticity driven. Under displacement-driven mechanical cycling, SnPb will tend t ut-perrm SAC (e.g., chip scale packages, CSP). Under lad-driven mechanical cycling, SAC will tend t ut-perrm SnPb (e.g., leads thin scale utline packages, TSOP). High-cycle atigue is elasticity driven. Stier SAC slder exhibits a lwer strain range. Typical Methd Vibratin: Steinberg Step 1 is the calculatin maximum delectin (Z 0 ). Z PSD 2 2 n where PSD is the pwer spectral density (g 2 /Hz), n is the natural requency the CCA, and Q is the transmissibility which is assumed t be square rt natural requency. Step 2 is t calculate the critical displacement. Where B is length PCB parallel t cmpnent, c is a cmpnent packaging cnstant typically 1 t 2.25, h is PCB thickness, r is a relative psitin actr and is 1.0 when a cmpnent is at the center the PCB and L is cmpnent length. Step 3 is the lie calculatin. N where N c is 10 r 20 millin cycles. Several assumptins made r this calculatin are: The CCA is simply supprted n all ur edges. Mre realistic supprt cnditins, such as stands r wedge lcks, can result in a lwer r higher displacements. The chassis natural requency diers rm the CCA natural requency by at least actr tw (ctave) which prevents cupling. Vibratin ccurs at rm temperature. Depending upn the cniguratin and lading, vibratin at lwer r higher temperatures can increase/decrease lietime The calculatin des nt cnsider the inluence in-plane displacement (i.e., tall cmpnents). Vibratin Stware Implementatin The stware uses the inite element results r bard level strain in a mdiied Steinberg-like rmula that substitutes the bard level strain r delectin and cmputes cycles t ailure. Critical strain r the cmpnent is deined by: c Z c chr N c 0 c Z 0 c Z L 6. 4 B L n Q

9 where ζ is analgus t B but mdiied r strain, c is a cmpnent packaging cnstant, 1 t 2.25 and L is cmpnent length. The Miles Equatin relates Harmnic vibratin t randm vibratin and must be utilized until the randm vibratin FEA cde is ully tested and released. where n = Natural requency, Q = transmissibility and ASD input = Input spectral density in g 2 /Hz. Sherlck vibratin mdeling results shw the displacement the PCB at all lcatins (see Figure 17). The results are pltted r each axis vibratin and the mst impacted cmpnents are revealed in the cmpnent list (Figure 18). Fatigue results are als shwn in an unreliability plt ver the lie the prduct, in the case where vibratin is an nging event. Mechanical Shck Envirnments Mechanical shck requirements were initially driven by experiences during shipping and transprtatin. Shck became increasing imprtance with the use prtable electrnic devices and is a surprising cncern r prtable medical devices. Figure 98 Graphical Vibratin Results JEDEC Shck Failure Failures related t mechanical shck typically cause pad cratering (A,G in the image) and intermetallic racture (B, F in the Figure 19). This is an verstress ailure nt a atigue ailure and llws a randm ailure distributin. The basic envirnmental cntributing actrs include: Height r G levels Surace (e.g., cncrete) Orientatin (crner r ace; all rientatins r wrstcase) Number drps Figure 109. JESD22 B110A, Subassembly Mechanical Shck Figure 87 Graphical Vibratin Results The stware analyzes shck based upn a critical bard level strain and will nt predict hw many drps t ailure. Either the design is rbust with regards t the expected shck envirnment r it is nt. Additinal wrk being initiated t investigate crner staking patterns and material inluences. An example the mdeling shwing displacement acrss a CCA ater a shck event is shwn in Figure 20. The rank rder cmpnents experiencing the largest strain are shwn in Figure 21.

10 Figure 20. Shck displacement results r a test bard. Figure 22. Failure Rate Inrmatin Entry Figure 113. Lie Predictin that cmbines cmpnent ailure with PTH and slder atigue. Figure 21. Cmpnents are listed in rder thse experiencing the highest strain. Cnstant Failure Rate Mdule A recent additin t the stware has been the inclusin a cnstant ailure rate mdel using MIL-HNBK-217F calculatins. Inputs necessary t cmpute ailure rates are lcated in the parts list (Figure 22). The cmpnent ailure rate is based the 217F mdel and takes int accunt the temperatures at which the prduct perates. An example the unreliability ailure plt is shwn in Figure 23, alng with ailure rates rm slder jint atigue and vibratin. Discussin The use the Sherlck circuit card assembly reliability mdeling tl is limited nly by the imaginatin and needs the user. There are a wide range prblems it can either slve r prvide insight t with regards t designing a reliable prduct. Sme these uses are identiied belw: Use Sherlck t determine thermal cycle test requirements needed t replicate the user envirnment. Use t mdiy munt pint lcatins Use t determine envirnmental stress screen (ESS) cnditins. Determine impact cmpnent package mdiicatins/changes. Determine impact changing t Pb-ree slder. Determine expected warranty csts. The apprpriate test cnditins can be determined by irst generating a slder jint atigue mdel based n the expected ield cnditins the prduct. The percent ailure at the required lie is then knwn r the design. The mdel is then rerun using the desired thermal cycle

11 test cnditins (say 0 t 100 C). The number cycles required t generate the same percent ailure shwn in the previus mdel is hw many cycles are required (with n great percent ailure). Naturally, the number cycles may be increased i the sample size is reduced. Early in the design phase a prduct is the best time t run varius what-i scenaris r the design. These might include experimenting t determine where the munt pint lcatins shuld be in rder t reduce strain n sensitive cmpnents. One may als run thermal cycling mdeling using the varius package ptins available r critical integrated circuits. The impact changing a prduct rm SnPb t Pb-ree slder may als be evaluated. Sme high reliability prducts required 100% ESS t ensure n prly built prducts escaped prductin. A cmmn ESS test is thermal cycling; hwever, ne des nt wish t remve mre than 5% the useul lie the prduct during the ESS. By mdeling the ttal lie, ne can make sure that the number cycles selected r ESS is apprpriate. Finally, many cnsumer electrnic cmpanies prvide a warranty perid r their prducts. Funds must be set aside r each prduct shipped t cver the expected ield returns within the warranty perid. It is imprtant that these csts be rughly accurate and based n data, since mney is lst i the retained amunt is t large r t small. The results prvide by Sherlck can prvide a prtin the ttal expected ield returns due t hardware wear-ut mechanisms. Summary The simple truth is that designing in reliability up rnt pays immensely ver the lie the prduct. T date, there has nt been a simple t use methd estimating the wear-ut lie an electrnic prduct. Sherlck stware is designed t ill this need and des s by allwing a rapid assessment electrnic systems reliability utilizing Physics Failure (PF). Sherlck is a pwerul reliability tl that can be used by the entire engineering design and management team. It allws the reliability grup t get invlved in the design prcess as well, as they nw can better quantiy trades bere the prduct is ready r testing. Sherlck is the uture Autmated Design Analysis (ADA): the integratin design rules, best practices and a return t a physics based understanding prduct reliability.