Generation of Spin Polarization in Side-Gated InAs Quantum Point Contact

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2 Generation of Spin Polarization in Side-Gated InAs Quantum Point Contact A dissertation submitted to the Graduate School of the University of Cincinnati in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering in the School of Electronic & Computing Systems of the College of Engineering & Applied Science June 2012 by Partha Pratim Das M.Sc. University of Delhi, India Committee Chair: Dr. Marc Cahay Committee Members: Dr. R. Newrock, Dr. P. Boolchand, Dr. P. Kosel & Dr. J. Heikenfeld ii

3 Abstract This dissertation explores the use of side-gated semiconductor quantum point contacts (QPCs) to generate strongly spin polarized current by purely electrical means. An anomalous conductance plateau (at conductance value, G = 0.5 (2e 2 /h)) was observed [P. Debray et al., Nature Nanotechnology 4, 759 (2009)] in an asymmetrically-biased, InAs quantum point contact with in-plane side gates, at 4.2 Kelvin in the ballistic transport regime. This was a clear experimental signature of spontaneous spin polarization in the narrow channel of the QPC. A non-equilibrium Green s function (NEGF) simulation revealed that three ingredients are necessary to create the spin polarization: an asymmetric lateral confinement, a lateral spin-orbit coupling (LSOC) induced by the lateral confining potential of the QPC, and a strong electronelectron interaction. In order to use such QPC devices to make all-electric spin valves, it is necessary to probe the sensitivity of these three ingredients to the bias difference between the two side gates that confine the electrons in the narrow channel. Towards that goal, this thesis shows experimentally that the anomalous conductance plateaus are quite robust and remain over a wide range of asymmetric bias voltages. In addition, a very systematic study is conducted to understand the appearance of conductance anomalies which range from 0.4 to 0.7 (2e 2 /h) depending on the biasing conditions. These results are interpreted as evidence for the sensitivity of the QPC spin polarization to the defects (surface roughness and impurity (dangling bonds) scattering) generated during the etching process that defines the QPC side walls or gates. This assertion is supported by NEGF simulations of the conductance of a QPC in presence of dangling bonds on iii

4 its walls. We also show that a spin polarization over 90% can be achieved despite the presence of these defects. NEGF simulations show that the maximum spin polarization is not necessarily reached where the conductance of the channel is equal to 0.5 (2e 2 /h). We propose developing QPC devices in series at elevated temperature as a mean to build an all-electric spin valve. iv

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6 Acknowledgements At the outset, I express my sincere gratitude and profound thanks to my thesis advisor and committee chair Dr. Marc Cahay for his constant help, support and encouragement throughout my graduate study. He has been very kind and understanding with me all these years. I thank my thesis committee members Dr. Richard Newrock, Dr. Punit Boolchand, Dr. Peter Kosel and Dr. Jason Heikenfeld for their valuable comments on my thesis. Special thanks go to Dr. Richard Newrock for allowing me to access his laboratory to conduct the low temperature transport measurements needed for my thesis. I also thank John Marcus for his technical support during experiments. Thankful gratitude to Dr. Philippe Debray for teaching me the low temperature measurements techniques at the initial stage and also for his guidance in some of the experiments. I am gratified to have a colleague and friend Nikhil, who has been very supportive during my difficult times of graduate study. I am more than thankful to him. Dr. Junjun Wan, whose simulations have been very useful in analyzing my experimental results, is highly appreciated. I am grateful to Dr. Steve Herbert for allowing me to use his deposition system. I thank all of my good friends for their help and support at various stages of my academic life. I remain indebted to all those who contributed directly or indirectly to my thesis research. I thank my mother and all other family members for their love and support, without which I could not complete my PhD. And finally, I specially appreciate Sumee for everything. This work was supported by NSF Awards ECCS and vi

7 List of Contents 1. Overview Introduction Background MOSFET and SPINFET Datta-Das Spin-FET Efficiency: MOSFET vs. SPINFET Spin Hall Effect All-Electric Spintronics Theoretical Background Electron: Charge and Spin Spin-Orbit Coupling Structural Inversion Asymmetry: Rashba SOC Bulk Inversion Asymmetry: Dresselhaus SOC Lateral Spin-Orbit Coupling (LSOC) Quantized Conductance in Quantum Point Contacts Spin Polarization Due to LSOC Advantages of a 1D Channel Origin of 0.5 Plateau Spin Texture in QPCs in Presence of LSOC Influence of Impurity Scattering on Spin Polarization in side-gated QPC Sample Description and Device Fabrication Introduction Molecular Beam Epitaxy InAs/InGaAs/InAlAs quantum well structure Structure and Layer Sequence of InAs 2DEG Sample Device Fabrication and Processing Steps Wafer Cleaning Resist Spinning. 48 vii

8 a. E-Beam Resist (PMMA). 48 b. Photoresist Lithographic Techniques 50 a. Electron Beam Lithography 50 b. UV-Photolithography Development Etching and Device Isolation Metal Deposition and Lift-off. 61 a. Deposition.. 61 b. Lift-off Atomic Force Microscope Annealing Scribing and Bonding Experimental Techniques Introduction Measurement Set-up Device Quality Check Conductance Measurement in QPC Device Results and Discussion Introduction Characterization of InAs 2DEG Classical and Quantum Hall Effect Shubnikov de Hass (SdH) Oscillations Experimental Results and Discussion Conductance Measurement: Part I.. 85 a. Results 85 b. Discussion Conductance Measurement: Part II. 90 a. Results 90 b. Discussion.. 94 c. NEGF Simulations. 99 viii

9 5.4 Conclusion Future Work High Temperature Operation Realization of All-Electric Spin-Valve References 110 ix

10 List of Figures Fig 1.1: Schematic illustration of Datta-Das spin-fet showing spin precession in the 1D channel due to top gate electric field. FMs are the spin polarized ferromagnetic electrodes. The current flows in x direction. The electric field point along y direction. The Rasbha field B R points along z.. 5 Fig. 1.2: Schematic of spin Hall effect showing the transverse spin current in a system with strong SOC, when a charge current flows through it [9] 8 Fig. 2.1: Pictorial representation of Zeeman spin splitting in presence of an external magnetic field (B). 15 Fig. 2.2: Energy dispersion for Rashba SOC in the 1D case. Opposite spins travel with different Fermi velocities Fig. 2.3: Energy dispersion relationship: (a) Degenerate case, (b) Energy split due to Zeeman splitting, (c) Energy split due to Rashba SOC.. 19 Fig 2.4: (a) A schematic demonstration of a 1D quantum wire with current flowing in the x- direction (blue arrow). (b) The potential profile which confines the motion of electrons along the y-direction. The electrons flow perpendicular to the page (along x-direction) leading to opposite spin accumulations (shown by red and blue arrows) along the two edges (I and II) of the wire [21] x

11 Fig. 2.5: (a) A schematic diagram showing how a QPC constriction is formed between two electron reservoirs using top gates (or split gates) deposited on a GaAs/AlGaAs heterostructure. (Courtesy: C. H. van der Wal) (b) Quantized conductance (in units of 2e 2 /h) vs. the gate voltage [22]. (c) Subband structure of a 1D electron system. E F is the Fermi level Fig. 2.6: Zeeman spin splitting of the first quantized plateau in presence of an external magnetic field B. The so-called 0.5 plateau appearing around G = 0.5(2e 2 /h) indicates that the spin degeneracy is lifted [21]. 25 Fig. 2.7: (a) Scanning electron micrograph of a side-gated InAs QPC. Dark areas represent isolation trenches. Arrows schematically show spin orientations of incoming (left, unpolarized) and outgoing (right, polarized) electrons. Electrons travel along x-axis. UG and LG are the inplane side gates. (b) Schematic representation of the transverse confining potential profile of a side-gated QPC. I and II represent the two edges of the QPC channel. B SO is the effective magnetic field induced by LSOC. Blue (dashed) and yellow curves are for symmetric and asymmetric biases, respectively [25]. (c) Linear conductance (G, in units of 2e 2 /h) of QPC measured at both gate symmetric (S) and asymmetric (AS) bias condition. The plot for AS shows the 0.5 plateau. V G is common sweep voltage applied simultaneously to both side gates [21] Fig. 2.8: NEGF results showing the evolution of 0.5 plateau with decreasing values of the e-e interaction parameter γ [21]. 33 Fig. 2.9: (a) Schematic diagram of a QPC with its different length scales. 1, 2 and 3 are the impurity locations. (b) Conductance plots for impurity (attractive and repulsive) location 3. The xi

12 0 mev is for no impurity case. (c) Conductance plots for impurity (attractive and repulsive) location 1, 2, and 3 [49].. 35 Fig. 3.1: A schematic diagram of a MBE system showing its different components [50]. 39 Fig. 3.2: (a) InAs QW formation using an InAs/InGaAs hetrostructure. For materials far apart (i.e. before MBE growth), the Fermi energy level (E F ) is at a different location for the different semiconductos. (b) When grown by MBE, E F is the same throughout the entire heterostructure at equilibrium. 41 Fig. 3.3: (a) The quantized energy level of 1D potential well. (b) Wave functions corresponding to different quantum numbers, n (=1, 2, 3,.) [50] Fig. 3.4: The DOS for the quantum well and its relation to the 1D energy sub-band diagram [50].. 43 Fig. 3.5: (a) A schematic cross-section of the InAs/InGaAs heterostructure used to make the QPC. The grey area indicates the etched portion which defines the QPC trench. (b) A threedimensional AFM image of a QPC with two in-plane side gates (G1 and G2) fabricated with chemical wet-etching technique Fig.3.6: PMMA resist thickness variation with spinning speeds/rpm for a spinning time of 45 sec. For example, 2% anisole PMMA with 4000 rpm, or above gives a thickness ~ 50 nm [52] Fig.3.7: Thickness variation of S1800 series positive photoresist with spin speed [53].. 50 xii

13 Fig. 3.8: (a) Raith 150 e-beam lithography system available in UC Cleanroom. (b) The stage where the sample is loaded. 51 Fig. 3.9: Block diagram of a typically used EBL [54]. 52 Fig.3.10: A Karl Suss MJB3 Mask Aligner available in UC cleanroom (gold room).. 55 Fig.3.11: (a) A chrome mask used for pattering. (b) Basic working principle of photolithography. (1) A photoresist (positive) layer is coated uniformly onto a substrate to be patterned. (2) The chome mask with the desired pattern on it. (3) Exposed with UV light. (4) After development in a chemical solution. The UV exposed parts are dissolved leaving the exact pattern of the mask on the substrate for further processing, e.g. etching, metallization, etc. 56 Fig. 3.12: Schematic diagram of a mask aligner with different parts. The three degrees of freedom (x, y, θ) are also shown [50].. 57 Fig. 3.13: (a) Photomask 1 for patterning isolation trenches. (b) Photomask 2 for patterning ohmics. In both cases only the grey areas are transparent to UV light. 58 Fig. 3.14: (a) The device isolation trenches which separate the device under consideration from the rest of the wafer. The tiny QPC sits inside the green circle. (b) Atomic force micrograph (AFM) of a QPC showing the trenches, patterned by e-beam lithography first, and then wetetching technique. The trenches eventually define the quasi one-dimensional channel region in between. 61 Fig 3.15: Ohmics (in golden color) after metal lift-off. 62 Fig 3.16: Schematic diagram of an AFM showing the different components [50]. 63 xiii

14 Fig. 3.17: (a) A Veeco Dimension 3100 Model of AFM used in this work (top). (b) A typical AFM scan showing trench width, channel width and trench depth of a QPC (bottom) Fig. 3.18: A wire bonded device Fig.4.1: (a) The measurement set-up used for low temperature transport measurement. (b) The tail of the DR probe with its main components marked. (c) An image of a bonded sample mounted in the sample holder of the DR probe. 69 Fig. 4.2: (a) Typical layout of a QPC device. The 8 golden pads are the ohmics deposited on the top of the wafer. Pads S and D are the source and drain, respectively. Pads 2 & 5 are the in-plane side-gates. Pads 1 & 3 or 4 & 6 are the pairs of voltage probes to measure the voltage across the QPC channel (inside the red circle). (b) An AFM image (3D front view) of a QPC device showing the channel (between pads S and D ) and the in-plane side-gates (pad # 2, 5). Dark red areas are the isolation trenches cut by e-beam lithography and wet etching technique to define the side-gates. 70 Fig. 4.3: (a) The circuit for gate leakage check. The function generator (FG) provides the variable AC voltages. The voltage across the standard 1 kohm resistance was applied to the ground via 2DEG and current was recorded. (b) Leakage current as a function of gate voltage applied from the FG. Current (noise) of the order of few nanoamperes means that the side-gates are completely leakage-free. 72 Fig. 4.4: (a) Circuit diagram for conductance measurements in a QPC channel. The drive voltage (V DS ), from voltage source V osc, between the source (S) and drain (D) creates a current through the narrow channel. The current flows in x-direction. The dc voltage applied to the side-gates (G1 and G2) provides electrostatic confinement (along y) to the electrons in the channel. The xiv

15 voltage drop across the channel (i.e. between the two voltage probes (denoted by pad V)) is measured by a digital voltmeter (shown in blue circle). (b) A typical conductance plot of a InAs QPC channel as a function of common sweep voltage (V G ) applied to both gates. The conductance was measured in units of 2e 2 /h. 74 Fig. 5.1: Schematic representation of the classical Hall effect. The current flows along x-axis. The magnetic field (B) points along z-axis. The transverse accumulation of charge gives rise to the Hall field along y-axis Fig. 5.2: Quantum Hall (blue) and SdH (red) measurements on an InAs Hall bar at 4.2 K 79 Fig. 5.3: (a) Density of states in the first subband in magnetic field [51]. (b) Periodic SdH oscillations observed in InAs 2DEG. 81 Fig. 5.4: A three-dimensional AFM image of a QPC with two in-plane gates (G1 and G2), fabricated using a chemical wet etching technique. The current flows in the x-direction. An asymmetric LSOC is generated using an asymmetric bias between the two gates generating an electric field in the y-direction 84 Fig. 5.5: The conductance of the QPC (in units of 2e 2 /h) measured as a function of the common sweep voltage V G applied to the in-plane gates, at T=4.2 K. The sweep voltage, V G is superimposed on initial potentials V G1 and V G2 applied to the gates to create an asymmetry. The left-most curve shows the conductance for the symmetric case; i.e., with only the common sweep voltage V G applied to the gates. For the other curves, from left to right, the initial potential V G2 applied to gate G2 is fixed at -2.0V and the initial potential V G1 on gate G1 is equal to 0.0, -0.1, - 0.3, -0.6, -0.9, -1.2, -1.5, -1.8, -2.0, -2.3, -2.6, -2.9, -3.1, -3.4, -3.7, -4.0, -4.5, -5.0, -5.5 and -6.5 V, respectively.. 85 xv

16 Fig. 5.6: The conductance (in units of 2e 2 /h) in a magnetic field, versus the common sweep voltage V G applied to the two in-plane gates, at T=4.2 K. Prior to the application of the common gate bias, the initial biases V G1 and V G2 were set equal to -1V and 0V, respectively. The different curves correspond to different values of the constant magnetic field applied perpendicular to the 2DEG. The plots corresponding to B = 0T and 7.5T are shown by arrows. From bottom to top, the other curves correspond to magnetic field values of 3.0 T, 5.5 T, 6.0 T, 6.5 T and 7.0 T, respectively Fig. 5.7 (a) Forward Asymmetry: The conductance of the QPC (in units of 2e 2 /h) as a function of the sweep voltage V G applied to the gates. The sweep voltage is superimposed on the potentials V G1 and V G2 applied to the gates to create an asymmetry. The potential applied to gate G2 is fixed at +2.0V. The leftmost curve corresponds to the conductance for the symmetric case, i.e., with only the common sweep voltage V G applied to the two gates. For the other curves, the potential on gate G1 is, from left to right, -2.0, -2.4, -2.6, - 2.8, -3.0, -3.2, -3.4, -3.6, -3.8, -4.2, -5,5 and -6.5 V. (b) Reverse Asymmetry: V G dependence of conductance measurement with the bias polarity on the gates G1 and G2 switched, i.e. gate G1 is fixed at +2V, and the potential at gate G2 is varied the same way as on gate G1 in Fig. 5.7(a). 90 Fig. 5.8: (a) Forward Asymmetry: plot of conductance of the QPC (in units of 2e2/h) as a function of the sweep voltage V G applied to the gates. The sweep voltage is superimposed on the potentials V G1 and V G2 applied to the gates to create the asymmetry. The potential applied to gate G2 is fixed at -1.0V. The leftmost curve corresponds to the conductance for the symmetric case, i.e., with only the common sweep voltage V G applied to the two gates. From left to right, the potentials on gate G1 are equal to 0, 0.4, 0.8, 1.2, 1.6, 2.0, 2.4, 2.8, 3.2, 3.6, 4.0, 4.4, 4.8 and 5.2V, respectively. (b) Reverse Asymmetry: The V G dependence of the conductance with the bias xvi

17 polarity on gates G1 and G2 switched, i.e. gate G1 is fixed at -1.0V, and the potential on gate G2 is varied the same way as on gate G1 in Fig. 5.8(a).. 92 Fig. 5.9: (a) Data set 1: Comparison of the conductance with V G1 = -3.2V and V G2 = 2V and the reverse case, i.e., V G1 = 2V and V G2 = -3.2V. (b) Data set 2: Comparison of the conductance when V G1 = -1V and V G2 = 2.8V and the reverse case, i.e., V G1 = 2.8V and V G2 = -1V. In both figures, the same common sweep voltage axis is used for the two polarities. 93 Fig. 5.10: Illustration of the conduction band energy profile between the two side gates, along a line through the middle of the QPC and perpendicular to the direction of current flow. The energy levels 1,2,3 represent dangling bonds on either side of the channel. E f is the Fermi level of the source contact. Figures (a) and (b) show the conduction profile for opposite polarities of the potential between the two side gates Fig. 5.11: Schematic of the QPC configuration used in the numerical simulations. The QPC parameters are w 2, l 2, w 1, l 1 = 16, 32, 48, and 64 nm, respectively. The two dark circles represent two dangling bonds located on the side walls of the narrow portion of the QPC Fig. 5.12: Total conductance G tot = G + G as a function of V sweep for a InAs QPC containing two dangling bonds at locations 1 and 2 in Fig The full curve corresponds to the case where an asymmetry in the QPC potential confinement is introduced by taking V sg1 = -0.2 V + V sweep and V sg2 = 0.2 V + V sweep. For this case, we also show the contributions from the up (G ) and down (G ) spins. The dashed curve for G tot corresponds to the case where an asymmetry in the QPC potential confinement is introduced by taking V sg1 = 0.2 V + V sweep and V sg2 = -0.2 V + V sweep. 102 xvii

18 Fig. 5.13: Spin conductance polarization α = [G - G ]/[G + G ] as a function of V sweep for a InAs QPC containing two dangling bonds at locations 1 and 2 in Fig α is positive and reaches a maximum of 0.97 for V sweep = 0.1V when an asymmetry in the QPC potential confinement was introduced using V sg1 = -0.2 V + V sweep and V sg2 = 0.2 V + V sweep. ; α is negative and reaches a maximum of for V sweep = 0.2 V when an asymmetry in the QPC potential confinement was introduced using V sg1 = 0.2 V + V sweep and V sg2 = -0.2 V + V sweep. 103 Fig. 6.1: Scanning electron micrograph (SEM) of a dual-qpc device made from InAs/InAlAs QW. SGs are in-plane side gates. QPC1 and QPC2 will act as spin injector and spin-detector, respectively xviii

19 List of Tables Table 4.1: Resistance values of different pairs of ohmics at T=300K and T= 4.2 K. 71 xix

20 Chapter 1 Overview 1

21 1.1 Introduction Spintronics is a newly emerging avenue of research which promises to deliver smaller, nonvolatile, and faster electronic devices with less energy consumption [1, 2]. Until recently, the electron spin was ignored in the mainstream charged-based electronics. Spin-based electronics or spintronics aims at the simultaneous manipulation of the electron spin and charge degrees of freedom and offers the possibility of developing electronic devices based on control of the electron spin. Spintronics research was stimulated by the discovery of giant magneto-resistance (GMR) effect in the mid-1980s. This is a quantum mechanical magneto-transport phenomena observed in thin-film structures made of alternate ferromagnetic and non-magnetic layers. For this remarkable discovery, which revolutionized the information technology industry over the past two decades, Albert Fert and Peter Grünberg won the 2007 Physics Nobel prize. Nowadays, major efforts in spintronics are aimed at realizing all-semiconductor magnetoresistive random access memory (MRAM) devices, fast and low power spin-fets, and spin-based quantum computation [3]. Before the realization of spin-based practical devices with novel characteristics is possible, finding effective ways to inject, manipulate, and detect the spin of the electron is of paramount importance. Since a magnetic moment is associated with the electron spin, attempts have been made to incorporate ferromagnetic metal electrodes into device architecture to allow for the injection, manipulation and detection of spin-polarized current. The use of ferromagnetic electrodes with semiconductors in the proposed Datta-Das spin-fet [4] makes the device bulky and leads to additional design and fabrication complexities. Moreover, magnetic electrodes may have magnetoresistance and proximity field effects that may result in spurious local Hall voltages that can complicate device characteristics and operation. Therefore, a far better way and 2

22 completely different avenue is to avoid the use of ferromagnetic contacts or external magnetic fields entirely and to control the creation, manipulation, and detection of electron spin by purely electrical means. This remains a central challenge in spintronics [5, 6]. Though it is still in its infancy, semiconductor spintronics research continues to grow vigorously. It raises hope to solve many issues, such as effective spin injection into the channel and the conductivity mismatch at the metal/semiconductor interface linked to the conventional metal spintronics. Semiconductor spintronics also holds the promise of integrating the best qualities of two separate avenues: unparallel storage capacity of magnetic memory and the attractive computing power of semiconductor logic [7]. This requires a robust understanding of spin-transport mechanism in semiconductors. The main motivation for our semiconductor spintronics research was to explore the possibility of producing a spin polarized current in an all-electric way and without using any ferromagnetic metal electrodes and external magnetic field. 1.2 Background MOSFET and SPINFET The conventional metal-oxide-semiconductor-field-effect transistor (MOSFET) operates on the basis of charge flow. There are two switching states ON and OFF : ON is when charge conduction through the channel (between source and drain) is high enough, and OFF when the conduction is low. So, a MOSFET acts like an electronic switch or logic gate, which requires charge motion. Switching requires changing the charge amount Q, in a time interval t, resulting in a current flow of magnitude I Q t. Dissipation energy, 2 2 I R t Q R t is always associated with a such charge flow in a resistive channel. For the 3

23 dissipation energy to be minimum, either t should be large (switching slowly) or Q be small. But, neither of them is desirable, because the former makes the switch slow and latter reduces noise immunity since it decreases the logic-level separation by bringing the two states closer together. This shortcoming made physicists and engineers think about spin-fet where electron charge will be replaced by its spin degree of freedom. In an external magnetic field electrons spin eigenstates can either be up or down. The electron spin can easily be flipped with a very small amount of energy. Moreover, compared to charge, electron spin is less sensitive to the environment. In a spin-fet the current flows between two terminals (source and drain) and it is modulated by applying an electric potential at a third terminal, called the gate, as in the conventional MOSFET. The only difference is that the gate potential does not control the number of electrons flowing in the channel, but instead it modulates their spin orientation. With the help of the gate, transistor ON and OFF action can be realized in a spin-fet should the source and drain terminals be efficient spin injector and spin detector Datta-Das SPINFET The Datta-Das spin-fet was proposed more than two decades ago [4]. It is the basic prototype of a spin-fet and is shown schematically in Fig The source and drain contacts in the spin-fet are ferromagnetic metals and magnetized along the direction of the current flow (xdirection) in the channel region. If the spin injection efficiency of the FM source contact is assumed to be 100% and there is no gate potential from the top, the electrons in the channel will travel without losing their original spin orientation (assuming, for simplicity, there is no spin 4

24 relaxation mechanism due to electron scattering from the magnetic impurities while travelling through the channel, and the magnetization of the contact points does not affect the particular spin alignment) and arrive at the FM drain contact with their spins still Fig 1.1: Schematic illustration of Datta-Das spin-fet showing spin precession in the 1D channel due to top gate electric field. FMs are the spin polarized ferromagnetic electrodes. The current flows in x direction. The electric field point along y direction. The Rasbha field B R points along z. aligned with the original direction (along x). This is the transistor ON state. But, if an electric field is applied from the gate pointing downward (along y) electrons moving in the channel will see it as a magnetic field due to relativistic effects, and the direction of that effective magnetic field will be perpendicular to the plane of electron propagation vector (k) and the applied electric field (E). The effective magnetic field will interact with the spin, resulting in spin-orbit coupling (SOC). This is known as the Rasbha interaction and so the effective field is the Rashba field 5

25 (B R ), where B R = αk/μ B and α is the Rashba SOC parameter. The spins of the electrons moving with the wave vector k precess around the direction B R as they travel. This is the Rasha spin precession. The precession angle is given by, θ = 2m*αL/ħ 2 (1.1) where L is the length of the 1D channel, m* the electron effective mass and ħ the reduced Plank constant. The Rashba SOC parameter, α = α* e E, where α* is the material specific intrinsic SOC parameter. Since the transport in the channel is purely 1D (along x), and the electric field points along the y-axis, the precession axis is very well-defined, along z. The precession angle (θ) can be controlled by the gate potential. If the gate electric field is adjusted so that the spin precesses by 180 when it arrives at the drain, the spin orientation will be anti-parallel with respect to that of the drain, and so the electron will not get through and will bounce off the drain. This is the transistor OFF state. Thus, the Datta-Das spin-fet is considered as a spin analogue of a conventional MOSFET with the striking difference that in the former the electron spin is modulated not the charge Efficiency: MOSFET vs. SPINFET A concerted effort has been made to realize the spin-fet in order to overcome the fundamental limits of CMOS devices (such as high power dissipation and low speed) when the device density on a chip becomes very high. Presently, in a Pentium IV chip, the device density is ~ 10 8 cm -2 with clock speed of ~ 2.8 GHz [8]. If all of the transistors switch at the same time, the power dissipation is between W/cm 2. Moore s law predicts that by 2025 the device density per chip will be cm -2 with clock speed of 10 GHz [8]. Then the power dissipation of a chip will increase to 2 MW/cm 2. The three-decades-old established technology can remove 6

26 only 1000 W/cm 2 heat energy from a chip and there is little hope for any dramatic improvement. This is the fundamental challenge facing the existing CMOS technology. Further downscaling of devices and increasing their density on a chip seems to be impossible in the present scenario unless the energy dissipation per switching event can be reduced. Therefore, a consensus is gradually evolving to explore novel means to manipulate electron spin rather than the charge, to ultimately realize the spin-based transistors. The energy required to flip the electron spin orientation is much less than that to drive charge motion. The splitting energy of the two spin polarized states is gμ B B. This is known as Zeeman splitting energy. Only this much energy is used when a spin-up state is flipped to a spin-down, or vice-versa. It can be further reduced by decreasing the magnetic field strength (using the gate potential). Therefore the spin-fet is a potential candidate for overcoming the difficulties faced by CMOS technology s fundamental scaling limits. This thesis is a step towards the realization of a Datta-Das spin-fet in an all-electrical way. We will avoid (for reasons mentioned above) any use of ferromagnetic metals as the source and drain contacts and any external magnetic field to inject, manipulate and detect spin-polarized currents. We emphasize to achieve these goals via purely electrical means. 1.3 Spin Hall Effect The SOC is a purely relativistic phenomenon. It couples an electron spin to its orbital motion. Lately, there has been considerable research on the spin Hall effect (SHE). This effect occurs when an unpolarized charge current traverses a material with spin-orbit interaction, resulting in a perpendicular spin current where up spin ( +1/2>) electrons accumulate on one edge of the sample and down spin ( -1/2> ) electrons accumulate on the other. A simple 7

27 schematic representation of SHE is shown in Fig SHE is a direct consequence of SOC in the system, which tends to align the spin angular momentum (S) and orbital angular momentum (L) in opposite direction [9]. A +1/2> electron, having scattered from an atom with strong SOC and L, tends to have its direction of motion twisted around the atom and moves towards the right (Fig. 1.2 ). Similarly, a -1/2> electron, when scatters off a similar atom with L, moves towards the left. This scattering, called skew scattering, causes a spatial separation of opposite spins in a direction perpendicular to the externally driven charge current. This results in a transverse spin current. Fig. 1.2: Schematic of spin Hall effect showing the transverse spin current in a system with strong SOC, when a charge current flows through it [9]. Though SHE was predicted theoretically four decades ago [10], its experimental observation has occured very recently in semiconductor materials [11, 12]. The work presented in refs. [11] and 8

28 [12] provide ways for only optical detection of spin. To date there has not been a successful and unambiguous electrical detection of the accumulated spins due to SHE. 1.4 All-Electric Spintronics One of the main reasons why the Datta-Das spin-fet has eluded experimental demonstration is the use of ferromagnetic source and drain contacts. Two tiny magnetized contacts, facing each other, will invariably induce magnetic field in the channel region which will adversely affect the spin transport. Moreover, the metal-semiconductor interface in such a transistor will make the spin injection inefficient. Lately, a new avenue of research has emerged called spintronics without magnetism [7, 11, 13, 14]. This alternate research track relies on the ability to manipulate electron (or, hole) spin through SOC. The proposed Datta-Das spin-fet works by controlling the Rashba SOC in a 1D semiconductor channel. To date, there have been numerous experimental efforts to control electron spin through Rashba SOC [15, 16], but all turned fruitless. A new kind of SOC, called the lateral SOC (LSOC), was proposed in 2006 [17, 18, 19]. The name lateral is used because this SOC originates from a lateral (or in-plane) electric field. The electric field is a result of lateral potential confinement in a 1D quantum wire. References [17], [18] and [19] predicted an accumulation of opposite spins along the edges of the 1D channel. Note that this spin accumulation is distinctly different from that of the spin Hall effect, because the origin of spin Hall effect is not in any way related to the lateral potential confinement. However, none of the work [17, 18, 19] predicted a net spin polarization. Our group at UC [20], led by Marc Cahay, Philippe Debray and Richard Newrock, used the concept of LSOC in a novel and clever way and showed experimentally, for the first time, that it was 9

29 possible to have complete spin polarization in a quantum point contact (QPC) device a short quantum wire between two large electron reservoirs, when its lateral confinement potential was made highly asymmetric. This was achieved through purely electrical means [21]. This was the first experimental demonstration of LSOC. LSOC is clearly different from Rashba SOC where the electric field results from an asymmetry in the confining potential of the quantum well. Unlike the case of LSOC, where the electric field is in-plane, the field which causes Rashba SOC points along the direction perpendicular to the two-dimensional electron gas in a quantum well. The QPC device was made from an InAs/InAlAs quantum well structure, using electron-beam lithography and wet etching techniques. In addition to the LSOC (which originates from the two hard wall boundaries of the etched 1D channel of the QPC), an asymmetric bias voltage was applied between lithographically defined in-plane side-gates. In the ballistic transport regime, an anomalous plateau at conductance value of 0.5 (2e 2 /h) was observed [21] apart from the usual normal conductance plateau at (2e 2 /h) [22, 23]. We call this feature the 0.5 plateau. The occurrence of the 0.5 plateau is a clear evidence of spin polarization in the narrowest 1D constriction of the QPC [24]. Non-equilibrium Green s function (NEGF) simulations carried out by another group member (Junjun Wan under the supervision of Marc Cahay) [21, 25] revealed that three important ingredients are very essential for generating spin polarization in an InAs QPC: an asymmetric lateral confinement, an LSOC induced by the lateral confining potential of the QPC, and a strong electron-electron (e-e) interaction. The LSOC initially triggers the spin imbalance in the channel region and the strong e-e interaction enhances it and finally yields maximum spin polarization. Such a QPC can be utilized as a spin-polarizer or spin-analyzer in a spin-fet should an appropriate biasing range be found. From a practical viewpoint, it is of paramount importance to 10

30 have a fairly robust 0.5 plateau which exists for a range of asymmetric bias voltages. This issue was not addressed in the earlier work [21]. We successfully reproduced our earlier results, but with a slight difference: this time the anomalous plateau appeared, not exactly at 0.5 (2e 2 /h), but around 0.4 (2e 2 /h). In the first part of this thesis work, we made a systemic study of how the 0.4 plateau evolves with gradual increase of bias asymmetry in the QPC channel, through the in-plane side-gates. We also give a convincing argument why the plateau did not appear exactly at conduction value of 0.5 (2e 2 /h). Secondly, we made an extensive study of the occurrence of anomalous plateaus at different locations [( ) (2e 2 /h)] below the normal conductance plateau (2e 2 /h) for different biasing conditions. The anomalous plateaus appear only over an intermediate range of asymmetric bias of several volts. The plateaus are quite robust and flat. These results are interpreted as evidence for the sensitivity of the QPC spin polarization to defects (surface roughness and impurity (dangling bond) scattering) generated during the etching process that forms the QPC side walls. As an outcome of this research, two single QPCs in series, separated by a distance smaller than the material spin-coherence length, can be used to build an all-electrical spin-valve. QPC1 injects polarized spins into the device channel and is the injector. QPC2 detects the spin state and is the detector. QPC1 and QPC2 replace the conventional magnetic electrodes or contacts. The ON condition of the device is defined when the spin orientations of the injector and detector QPCs are set parallel by fine tuning the confining potential of each QPC by varying their respective side gate voltages. Similarly, the OFF condition is achieved when the spin orientations of the injector and detector QPCs are set antiparallel. 11

31 The rest of this thesis is divided into the following chapters: Chapter 2 Theoretical Background: This chapter explains the underlying physical concepts needed to understand the experimental work, including the basic concept of spin, the quantized conductance in QPC, the different types of SOC in semiconductors and their applications, and the observation of anomalous conductance plateau in a side-gated QPC and its significance with respect to spin-polarization, etc. Chapter 3 Sample Description and Device Fabrication: The first part of this chapter deals with a detailed description of the InAs quantum well structures used in our experiments. The second part explains the different nano-fabrication steps followed in the cleanroom for making the QPC devices. Chapter 4 Experimental Techniques: This chapter explains how the low temperature transport measurements were made at liquid helium temperature (4.2 K). It elaborates the measurement set-up comprising of a liquid helium dewar and a superconducting magnet system (capable of generating field up to 9 Tesla), several lock-in amplifiers, function generators, dc battery source, digital volt meters and an interfaced computer LabVIEW program to measure the conductance of QPC devices. Chapter 5 Results and Discussion: This chapter presents the experimental results and their interpretation. We describe the appearance of anomalous conductance plateaus at various locations below the normal conductance plateau in a side-gated InAs QPC. Some NEGF results are added to qualitatively describe some of the experimental results. Chapter 6 Future work: This chapter outlines the steps needed to extend this research effort towards the realization of an all-electric spin valve. 12

32 Chapter 2 Theoretical Background 13

33 2.1 Electron: Charge and Spin It is well known that electrons have two degrees of freedom charge and spin. In 1909, Robert Millikan, a professor at the University of Chicago performed the famous oil drop experiment and found the unit charge of an electron to be ~ C. The concept of spin came much later. The common mental picture of the spin of a classical sphere gives us an idea about the angular momentum (with continuous values) associated with a sphere spinning around its own axis. However, this simple concept cannot be extended to elementary particles such as electrons. In the famous textbook on quantum mechanics, Landau and Lifshitz wrote [27], that the spin property of elementary particles has no classical interpretation. The concept of spin angular momentum first came from an American physicist, Ralph de Laer Kronig, in 1925 [28]. He postulated that in addition to the already known principal (n) and angular quantum numbers (l and m), a new kind of degree of freedom associated with the self-rotation ( or spin motion) of the electron is needed. He called it spin angular momentum. Later Uhlenbeck and Goudsmit added their views on it and finally the electron spin took a theoretical shape [8]. It was Stern and Gerlach who experimentally established that electron spin is a purely quantum mechanical property and it cannot be explained classically [8]. They showed that the spin angular momentum can bear only two values either spin-up (+ħ/2) or spin-down (-ħ/2), and therefore is quantized. A magnetic moment is associated with the electron spin. An electron with spin S = ħ/2 possess a magnetic moment M = gµ B S, where g is a constant called the electron gyromagnetic factor and B is the Bohr magneton [28]. When the electron is placed in an external magnetic field (B) its magnetic moment will couple to the field splitting the energy bands into ones for spin up and spin-down electrons. On solving the Schrodinger equation, one gets the energy 14

34 splitting to be E= gµ B B. This is known as Zeeman spin splitting. The splitting energy is proportional to the strength of the magnetic field (Fig. 2.1). Fig. 2.1: Pictorial representation of Zeeman spin splitting in presence of an external magnetic field (B). In general, the Zeeman splitting energy is much smaller than the Fermi energy in semiconductors and metals, and spin-dependent phenomena are not usually observed under normal conditions. However, this situation changes if there is a spin-polarized current injected into a semiconductor. This will open up several branches of spin-based electronics, such as creation, manipulation and detection of the spin degree of freedom. Note that for spin-dependent phenomena to be observed, the Zeeman energy has to be large compared to k B T. Thus, the temperature plays a vital role in observing spin transport phenomena in such systems. 2.2 Spin-Orbit Coupling Spin-orbit coupling (SOC) is a possible mechanism for achieving the main objectives of spintronics the creation, manipulation and detection of spin polarized current. SOC is a purely quantum mechanical which can be fully understood starting with the Dirac equation. There are different types of SOC in semiconducting materials with different physical origins. 15

35 Ralph de Laer Kronig, who first laid out the concept of electron spin, also thought about Q SOC [28]. In an atom, the electric field at a location r from the nucleus is E r, 3 4 0r where Q is the effective charge seen by the electron. This electric field is felt by the moving electrons as a magnetic field, B given by: 1 B 0 0v E 2 c v E, (2.1) where v is the orbital velocity of electron and c the speed of light in vacuum [28]. We can say that the electric field is Lorentz transformed to an effective magnetic field. The SOC Hamiltonian obtained from the Dirac equation [29], ( ) ( ) where λ is SOC parameter and, m 0 is the rest mass of electron, k = p/ħ, c is the speed of light, σ = (σ x, σ y, σ z ) are the Pauli spin matrices and U is the electrostatic potential. The electric field is related to the potential U via E = - U. We know that in the Dirac formalism, the energy gap between positive and negative energy is given by 2m 0 c 2 ~ 1MeV. This is called the Dirac gap. This gap has to be small for the SOC in a system to become high. This reasoning can be extended to semiconductors using a two band model where the Dirac gap is replaced by the energy gap between the conduction and valence bands, which is of the order of 1 ev or less in III-V semiconductors [29]. This results in a high SOC in semiconductor materials. InAs, a low band gap (~ 0.36 ev) semiconductor with low electron effective mass (m* = 0.023m 0 ) has large spin-orbit coupling. This is the prime reason InAs-based quantum well structures are thought to have interesting spin dependent properties and why they have been selected for this work. 16

36 2.2.1 Structural Inversion Asymmetry: Rashba SOC It is seen from Eq. (2.2) that the SOC Hamiltonian depends on the electrostatic potential U. In solids the electrons do not experience a strong attraction due to the nuclei. However, an SOC causing potential (or electric field) can have many different physical origins, e.g., an internal potential gradient or an externally applied electric field [28]. This was first studied by E. I. Rashba [30] in 1960 in an asymmetrically grown QW structure where the barrier height of the two sides of the well was different, causing a gradient in the potential and the electric field (in the growth direction) which resulted in SOC. The moving electrons see this electric field as an effective magnetic field that lies in the plane of the 2DEG, perpendicular to the electric field. This effective magnetic field is responsible for spin splitting and lifting the spin degeneracy. This is known as the Rasbha interaction [30]. The Rashba Hamiltonian and the corresponding spin-splitting energy dispersion relation are given by [30], ( ) and ( ) (2.3) The Rashba electric field (E) points along the direction (the direction of growth of the asymmetric heterostructure). α is a constant defined by α = α* e E where α* is the Rashba SOC parameter, which is proportional to the intensity of the electric field. The value of α can be tailored externally by applying a gate voltage from the top. Figure 2.2 shows the energy dispersion curve for spin-up and spin-down electrons in the 1D case. Electrons with opposite spins travel with different Fermi velocities. Thus they have two different wave vectors which 17

37 correspond to two electron gases with slightly different carrier concentrations which can be seen in the beating pattern of the Shubnikov-de Hass (SdH) oscillations [31,32]. Fig. 2.2: Energy dispersion for Rashba SOC in the 1D case. Opposite spins travel with different Fermi velocities. Rashba SOC arises due to a structural inversion asymmetry (SIA) which can be tailored by introducing either internal (through asymmetric confinement of the 2DEG or QW) or external electric fields (applying voltages through top gates). Note that unlike Zeeman splitting, Rashba spin splitting does not result in a net magnetization of the 2D system as its Hamiltonian (H Rashba ) carries a time-reversal invariance. No common spin quantization axis is available for its spin eigenstates. Also, as shown in the parabolic dispersion curves (Figs. 2.3(b) and (c)), opposite spins for the case of Rashba are shifted along k, rather than the E axis, as in case of Zeeman splitting. 18

38 (a) (b) (c) Fig. 2.3: Energy dispersion relationship: (a) Degenerate case, (b) Energy split due to Zeeman splitting, (c) Energy split due to Rashba SOC. There have been intense efforts to manipulate the electron spin in 2D systems by controlling the electric field which produces Rashba SOC [15, 16]. A successful experimental demonstration would pave the way for realization of the Datta-Das spin-fet [4]. But, as of now, there has been no report of success Bulk Inversion Asymmetry: Dresselhaus SOC Unlike structural inversion asymmetry which can be engineered into a QW system, bulk inversion asymmetry (BIA) arises due to the lack of an inversion center in the zinc-blende structure of some semiconductors (e.g. InAs, GaAs etc.). 19

39 Time and space inversion symmetry in solids lead to the following relations: Time inversion symmetry: E (k) = E ] (-k), E (k) = E (k) Space inversion symmetry: E (k) = E (-k) Here, k is the wave-vector and and denote the spin-up and spin-down states of electrons. The symmetry operation (space and time) changes k to k. Combining both time and space inversion symmetry we have E (k) = E (k), a relation valid in semiconductors such as Si and Ge. But, in III-V semiconductors (e.g. InAs, GaAs, etc.) there is no inversion center and therefore E (k) E (k). Thus, the spin degeneracy is lifted for a non-zero k. This was first noted by G. Dresselhaus [33] and is referred to as Dresselhaus spin-orbit coupling Lateral Spin-Orbit Coupling (LSOC) The concept of lateral spin-orbit coupling is more recent than Rasbha and Dresselhaus SOC. It was proposed in 2006 by three theory groups K. Hattori et al. [17], Y. Xing et al. [18] and Y. Jiang et al. [19]. Consider a 1D quantum wire where the current flows in the x-direction and the motion of the electrons is restricted along the lateral y-direction. A 1D quantum wire can be formed from a 2DEG system lying in the xy-plane by creating a confining potential (U) along the y-direction as shown in Fig

40 (a) (b) Fig 2.4: (a) A schematic demonstration of a 1D quantum wire with current flowing in the x-direction (blue arrow). (b) The potential profile which confines the motion of electrons along the y-direction. The electrons flow perpendicular to the page (along x-direction) leading to opposite spin accumulations (shown by red and blue arrows) along the two edges (I and II) of the wire [21]. The potential remains constant along y in the central part of the wire, but rises steeply around the edges (Fig. 2.4(b)). This implies an electric field E = - U points towards the edges. The moving electrons will see the electric field as an effective magnetic field (along the z- direction). This effective magnetic field (B SO ) will couple to the electron spin, resulting in spinorbit coupling. Since the origin of this SOC is the lateral electric field, we call it lateral spinorbit coupling (LSOC). This is clearly different from the Rasbha SOC, which originates from an 21

41 electric field due to the asymmetric confinement of a quantum well structure. Unlike LSOC, the Rasbha electric field is perpendicular to the 2DEG. The LSOC energy caused by the lateral in-plane electric field is given by [18], V 2 2m c SO *2 2 z k x d U( y) dy (2.4) For electrons moving in the +k x direction in the 1D channel, Eq. (2.4) tells us that the effective potential at y = 0 is lower for the spin-down electrons (σ z = -1) than for the spin-up electrons (σ z = +1). At the opposite side of the wire (i.e. at y = L), the effective potential for the spin-up electrons is lower than the one for spin-down electrons. This causes a spin imbalance and results in accumulations of opposite spins along the edges of the wire [16]. For electrons travelling in -k x direction the sign of spin accumulation is reversed. Thus, a lateral confining potential can cause opposite spin accumulation along the two sides of the 1D quantum wire. However, none of the theoretical studies [17, 18, and 19] predict a net spin polarization and a spin-polarized current in the 1D system. 2.3 Quantized Conductance in Quantum Point Contacts The history of quantum point contact (QPC) begins in 1988 when two separate groups B. J. van Wees et al. at Delft [22] and D. A. Wharam et al. at Cambridge [23], discovered a stepwise behavior in the conductance (Fig. 2.5(b)) through a narrow 1D channel, called quantum point contact, created by depleting the two dimensional electron gas at the hetero-interface of a GaAs/AlGaAs heterostructure (Fig. 2.5(a)). To observe this they applied fairly large negative voltages to the split gates sitting on the surface. The conductance steps were found to be 22

42 quantized at a value of G 0 = (2e 2 /h), and the effect was called quantized conductance. Here, e is the electron charge and h is Planck s constant. E E 3 E 2 EF E 1 k (a) (b) (c) Fig. 2.5: (a) A schematic diagram showing how a QPC constriction is formed between two electron reservoirs using top gates (or split gates) deposited on a GaAs/AlGaAs heterostructure. (Courtesy: C. H. van der Wal) (b) Quantized conductance (in units of 2e 2 /h) vs. the gate voltage [22]. (c) Subband structure of a 1D electron system. E F is the Fermi level. The width of the channel can be controlled by appropriate voltage biasing of the gates. QPCs can also be made using in-plane side gates instead of surface top gates. Because of the small aspect ratio, width/length, a QPC is a nearly 1D system. 23

43 Figure 2.5(c) illustrates schematically the band structure of a 1D system. It consists of a number of 1D subbands, the bottoms of which are at E 1, E 2, etc. E F is the Fermi level and k the 1D propagation vector. The energy of the subband bottom, E n, and the conductance G, are given by 2 E n m n 1,2,3 2 n w e G h 2 N 2 t mn n, m 1 (2.5) where N is the number of occupied subbands below the Fermi level and w is the width of the channel. When the wire dimensions are smaller than both the elastic and inelastic scattering lengths, transport is ballistic and the transmission probability, t mn 2 = 1. The summation is equal to N and the conductance is quantized at integral values of (2e 2 /h). Each time the Fermi level sweeps up through a subband bottom, N increases by unity. The factor of 2 on the right hand side of G is for the spin degeneracy of the electrons. When the spin degeneracy is removed, e.g., by a strong external magnetic field (Fig. 2.6), the conductance is quantized at integral values of 0.5(2e 2 /h). Though it is not direct evidence, the occurrence of the plateau at conductance value G = 0.5G 0 is a clear experimental signature of complete spin polarization. 24

44 G (2e 2 /h) AlGaAs/GaAs QPC T = 70 mk B=0 1.0 B=1.5T V G (V) Fig. 2.6: Zeeman spin splitting of the first quantized plateau in presence of an external magnetic field B. The so-called 0.5 plateau appearing around G = 0.5(2e 2 /h) indicates that the spin degeneracy is lifted [21]. Figure 2.5(c) shows that the available k-space or momentum space in a 1D system is severely limited compared to that in 2D or 3D system. The QPC is a very versatile device. The channel width of the device can be controlled by the gate voltages. One can thus control the electron density and the position of the Fermi level. When the Fermi level is in the lowest subband, transport is strictly 1D in the fundamental mode. The Fermi surface consists of only two points, k F. When a large number of subbands are occupied, transport becomes quasi-1d. Note that when the Fermi level is close to the bottom of the lowest subband, the electron density can be very low and there will be strong electron-electron interaction. 25

45 2.4 Spin Polarization Due to LSOC Figure 2.7(a) shows a scanning electron micrograph of a QPC device with in-plane side gates. As discussed earlier, the gradients of the lateral confining potential, U(y), of a quantum wire or QPC result in a transverse in-plane electric field E (Fig. 2.7(b)). An electron moving with wave vector k sees this as an effective magnetic field. The resulting spin-orbit interaction is H SO k U x y, where is the intrinsic SOC parameter of the channel material. The effective magnetic field (Fig. 2.4(a)) is B SO k U x y. Because this coupling results from the lateral electric field, we call it lateral spin-orbit coupling. It is clearly different from Rashba SOC, which arises from the electric field due to the asymmetry in the confining potential of a quantum well (QW) structure. Note that unlike the RSOC-causing electric field, which is perpendicular to the 2DEG plane (or device plane), the electric field which gives rise to the LSOC lies in the 2DEG plane. Recent theoretical work reported that the LSOC can induce an accumulation of opposite spins on the edges of a quantum wire [17, 18, and 19]. But, none predicted a net spin polarization that might generate a spin-polarized current. P. Debray et al. [21] showed that when the confining potential U(y) of the QPC is made highly asymmetric, a net spin polarization results. Spin-up and spin-down electrons experience opposite LSOC forces and are displaced in opposite directions along the y-axis. This results in an accumulation of opposite spins at the two transverse edges (Fig. 2.7(b)). For symmetric confinement, the spin polarizations at the opposite edges cancel one other, giving zero net polarization. 26

46 (b) (a) (b) (c) Fig. 2.7: (a) Scanning electron micrograph of a side-gated InAs QPC. Dark areas represent isolation trenches. Arrows schematically show spin orientations of incoming (left, unpolarized) and outgoing (right, polarized) electrons. Electrons travel along x-axis. UG and LG are the in-plane side gates. (b) Schematic representation of the transverse confining potential profile of a side-gated QPC. I and II represent the two edges of the QPC channel. B SO is the effective magnetic field induced by LSOC. Blue (dashed) and yellow curves are for symmetric and asymmetric biases, respectively [25]. (c) Linear conductance (G, in units of 2e 2 /h) of QPC measured at both gate symmetric (S) and asymmetric (AS) bias condition. The plot for AS shows the 0.5 plateau. V G is common sweep voltage applied simultaneously to both side gates [21]. When the confinement is made asymmetric (V I V II 0V) by tuning the side gate voltages V I and V II (Fig. 2.7(b)), either + Z on the left edge dominates Z on the right edge or viceversa (depending on the polarity of the asymmetric voltage applied to the gates), resulting in a spin imbalance and a net + Z or - Z polarization. The spin polarization creates a feature around G = 0.5G 0 below the normal conductance plateau at G 0 (Fig. 2.7(c)). We refer this to the 0.5 plateau. 27

47 2.5 Advantages of a 1D Channel One of the important criteria to create successful spin-based devices is that their channel length must be smaller than the spin coherence length (L s ) the maximum distance an electron travels without losing its original spin state. It is of paramount importance to use a material and a device architecture that yields the largest L s. In semiconductors where there is an intrinsic SOC or a lack of inversion symmetry, the spin degeneracy for +1/2> and -1/2> electrons is lifted. This splitting plays a pivotal role in spin manipulation and spin transport phenomena. The spin splitting due to SOC is a result of the interaction between the electron spin and the effective magnetic field. The amplitude and direction of the forces involved depend on the propagation vector (k) of the electrons. The electron spin will precess around the magnetic field. Since the direction of an electron s momentum (p = ħk) varies due to scattering from phonons, impurities, etc., the effective magnetic field changes with time. As a result, the average spin precession around the field, in the intervals between collisions, gives rise to the spin relaxation phenomena. When a spin polarized beam of electrons is injected into a semiconductor channel, the initial spin orientation loses coherence as the electrons travel through the channel. In III-V semiconductors, such as GaAs, InAs etc., there are mainly two types of spin relaxation mechanisms: the Elliot-Yafet (EY) [34, 35] and the Dyakonov-Perel (DP) [36]. In the EY process, the spin relaxes by momentum scattering off impurities or phonons. This happens because the SOC produces electron eigenstates that mix spin-up and spin-down states. At each scattering there is a probability of a spin flip. In the DP process, spin relaxation is related to the spin precession around the effective magnetic field induced by SOC. At each momentum scattering, the electron changes its k vector and experiences a different (in magnitude and/or 28

48 direction) SOC induced magnetic field. The precession axis and frequency changes randomly, producing spin dephasing. Phonon modulation of SOC can also lead to spin relaxation. The DP relaxation is more prominent in semiconductors without a center of symmetry, such as GaAs and InAs. In our work, a nearly 1D system in form of an InAs QPC channel is used to create the spin polarization in its narrowest part. Application of a negative bias voltage on the in-plane side gates further reduces the channel width, making the system perfectly 1D. Such a 1D constriction offers several advantages for observing spin dynamics. First, EY relaxation is strongly suppressed because of severe restrictions on the available k-space, which results in a significant reduction in momentum scattering. Second, the 1D channel offers a unidirectional propagation wave vector k (Fermi surface consists of only two points ±k F ), and therefore the spin quantization axis defined by the SOC magnetic field B SO is well defined. This considerably suppresses spin relaxation due to the DP mechanism. Reduction in available k-space reduces it further. An enhanced spin coherence length is therefore expected in a 1D channel. This is supported by experimental observation [37, 38]. There have been a few theoretical reports based on Monte Carlo (MC) simulations [39], spin diffusion (SD) equation [40], and recursive Green s function (RGF) techniques [41] which show that L s increases when the width (W) of the 1D channel is lowered. MC simulations predict L S W 1, SD equation gives L S L 1/2 e W 3/2, whereas RGF results show that there is a general tendency for L S to increase with decreasing W. The increase of L S with decreasing W has been supported by recent experimental work [42]. This raises the possibility of electrical control of spin relaxation in a side-gated QPC since its channel width can be controlled electrically by gate bias voltages. Finally, due to the increased electron- 29

49 electron (e-e) interaction in a 1D system, the effective electron g-factor is considerably larger in a 1D than in a 2D system [43, 44] enhancing Zeeman spin splitting. 2.6 Origin of 0.5 Plateau A former group member, S. M. S. Rahman 1 observed experimentally a 0.5 plateau, in addition to the normal plateau at conductance value G G 0 = 2e 2 /h, in absence of an external magnetic field, when the lateral confining potential of a side-gated InAs QPC was made sufficiently asymmetric [21, 25]. As shown in Fig. 2.5, the spin-splitting of the first 1D subband can produce such an anomalous plateau around G= 0.5G 0 in presence of a magnetic field perpendicular to the device plane. The appearance of 0.5 plateau is a clear experimental signature for spin polarization [21]. Therefore, such a QPC can be used to polarize and detect electron spin. To understand theoretically the origin of the 0.5 plateau, we consider the free electron Hamiltonian of the QPC as given by [21], H = H 0 + H SO (2.6) H 2m 2 p p U( ) y * x y H ( k U( y)) SO B SO where β is the lateral SOC parameter of the QPC material and B so the effective magnetic field induced by the LSOC. U(y) describes the potential profile of the QPC channel along its y- 1 S. M. S. Rahman was a graduate student in the UC Physics Department. For his thesis, see ref. [29]. 30

50 direction; the current flows in the x-direction. We used a nominally symmetric InAs quantum well to make the QPC device, therefore the RSOC is minimal and the Rashba term is absent from the Hamiltonian. We do not consider the Dresselhaus SOC term, because the current in our InAs QPCs flows along [100] direction, for which this interaction is found to be minimal [45]. Therefore, LSOC is the only term considered here. Since the 0.5 plateau appears below the first quantization at G 0 (close to pinch-off of the channel) we are only interested in the transport in the fundamental mode, or in the lowest 1D subband. It is noteworthy that the Fermi energy of the 1D electron gas is often considerably smaller than the Fermi energy of the 2DEG. This happen when the conductance channel is narrowed by the negative gate bias voltages which can raise the bottom of the 1D potential well relative to the 2D subband bottom [46, 47]. As a result, even though the 1D subband separation may be much smaller than the 2DEG Fermi energy, it is possible to have transport in the fundamental mode. The free-electron Hamiltonian H is invariant under time reversal, and therefore a numerical solution of the Schrodinger equation, obtained through a scattering matrix approach, does not result in a 0.5 plateau in the ballistic regime of QPC conductance [21]. The inevitable consequence of time-reversal invariance (TRI) for a system with spin ½ particles is that each single-particle energy level must have at least a two-fold Kramers degeneracy. TRI must be broken for spin polarization to occur. Time-reversal operates on a closed quantum system. A real system is seldom closed and is often interfaced to its environment. In our specific case, the source and drain current contacts, without any SOC, are the interfaces. To measure the conductance an external bias voltage is applied to send a current through the QPC. The flow of 31

51 current breaks the TRI. Though breaking the TRI this way allows spin polarization, it is not enough to lead to complete spin polarization. Another former group member, J. Wan 2, solved the Schrodinger equation with the Hamiltonian in Eq. (2.6) using a non-integral Green s function (NEGF) formalism. He took the electron-electron (e-e) interactions into account, and found that three ingredients are of paramount importance in producing spin polarization in a side-gated InAs QPC: (1) an asymmetric lateral confinement, (2) a LSOC induced by the lateral confining potential of the QPC, and (3) a strong e-e interaction. LSOC inevitably exists in the QPC channel because of the two hard boundaries on either side of the channel where we have an air/2deg interface. The asymmetry in the confining potential of the QPC is needed to trigger an initial imbalance between the densities of spin-up and spin-down electrons in the channel. Once that imbalance is created the strong e-e interaction enhances it and gives rise to the 0.5 plateau [21, 25]. In J. Wan s work, the e-e interaction was considered in the form of a Coulomb repulsive potential, V ( r r ' ' int r, r ), where γ is a measure of the interaction strength. In Fig. 2.8, we see that the 0.5 plateau smoothly rises to the normal conductance plateau (G 0 ) as the e-e interaction strength decreases (γ varying from 5.4 to 3.4). 2 J. Wan was a graduate student in the UC Electrical Engineering Department. For his thesis, see ref. [26]. 32

52 G(2e 2 /h) V T (V) Fig. 2.8: NEGF results showing the evolution of 0.5 plateau with decreasing values of the e-e interaction parameter γ [21]. In summary, a highly spin-polarized current can be produced in a side-gated QPC made from a nominally symmetric InAs quantum well structure (with a high intrinsic SOC) when its lateral confining potential is made sufficiently asymmetric. This happens when the e-e interaction (γ) is fairly strong. Therefore, the conduction through the channel has to take place in the lowest subband because γ is highest there because of the low electron concentration in the channel. The 0.5 plateau appears when the pinched-off channel is gradually opened by adjusting the gate voltages, and when the Fermi level crosses the first subband from below and is just above its bottom. 33

53 2.7 Spin Texture in QPCs in Presence of LSOC J. Wan et al. [48] used the NEGF formalism to study the conductance anomalies for a wide range of QPC dimensions and gate bias voltages. They predicted a number of conductance anomalies below the first quantized conductance plateau (G 0 =2e 2 /h) due to spontaneous spin polarization in the QPCs. The larger the aspect ratio, the more conductance anomalies should be observed. They related these conductance anomalies to fingerprints of different spin textures in the narrow part of the QPCs. 2.8 Influence of Impurity Scattering on Spin Polarization in side-gated QPC J. Wan et al. [49] performed a second theoretical study on how the anomalous conductance plateau was influenced by the presence of impurities in a side-gated QPC channel. The NEGF formalism was used to calculate the total conductance for cases with impurities at different locations in the conduction channel. The number, location and shape of the conduction anomalies below the normal conduction plateau (G 0 = 2e 2 /h) were found to depend on the nature (attractive or repulsive) and location of the impurities in the QPC channel. An essential ingredient for generating spin polarization is the asymmetric potential profile in the QPC channel. The impurities present in the vicinity of the channel can induce such an asymmetry even for the case when the side gates are symmetrically biased. Figure 2.9(a) shows the schematic diagram of a side-gated QPC device used for these NEGF simulations. Figure 2.9(b) is a conductance plot as a function of sweep voltage for a QPC channel with an impurity at location 3 in Fig. 2.9(a). The conductance anomalies showed a 34

54 (a) (b) (c) Fig. 2.9: (a) Schematic diagram of a QPC with its different length scales. 1, 2 and 3 are the impurity locations. (b) Conductance plots for impurity (attractive and repulsive) location 3. The 0 mev is for no impurity case. (c) Conductance plots for impurity (attractive and repulsive) location 1, 2, and 3 [49]. 35

55 dependence on the strength and the nature (attractive and repulsive) of impurity. In all the plots there were conductance anomalies close to 0.5 G 0 accompanied by a negative differential region (NDR) and a second anomaly somewhere between G 0. For the case of an attractive impurity potential, the peak-to-valley ratio of the NDR after the 0.5 G 0 increased with the strength of the impurity potential. An opposite trend was seen for a repulsive impurity. Figure 2.9(c) shows the sensitivity of the conductance anomalies to the impurity location (points 1, 2 and 3 in Fig.2.9(a)) in the central portion of the channel. As will be described in the chapter 5 (Results and Discussion), we observed experimentally various conductance anomalies for InAs based QPCs in the range of G 0 for different biasing conditions. The experimental results will be analyzed based on the NEGF results described above. 36

56 Chapter 3 Sample Description and Device Fabrication 37

57 3.1 Introduction The two-dimensional electron gas (2DEG) has been quite an interesting system of research for physicists and electrical engineers, and there have been various important device applications (electronic and optical). It is made from quantum heterostructures grown by sophisticated techniques such as molecular beam epitaxy (MBE). In general, a 2DEG is formed using a III-V semiconductor hetrostructure starting with an interfaces between a narrow and a wide band-gap material. A quantum well forms between the interface of the two heterojunctions, where electrons are trapped and their motion constrained along the growth direction, yielding the 2DEG. One- dimensional wires can be formed, starting with a 2DEG, using lithographic and wet/dry etching techniques. In our work, a high mobility InAs/InGaAs-based symmetric heterostructure is used. InAs is a low band-gap (~ 0.36 ev) material with high spin-orbit coupling. Therefore, it is thought to have interesting device possibilities in a quantum point contact (QPC) structure with in-plane side gates, (as will be discussed in detail later). This chapter explains the formation of an InAs quantum well (QW) in MBE grown quantum heterosturcture and details the QPC processing steps. 3.2 Molecular Beam Epitaxy The word epitaxy means an ordered arrangement of atoms on a substrate. Molecular beam epitaxy (MBE) was developed in the 1970s for growing very high quality crystalline thin films for use in the fabrication of advanced semiconductor devices. It is a very sophisticated technique for epitaxial growth of several crystalline semiconductor layers on top of one another, with a high degree of accuracy. It is done inside a ultrahigh vacuum chamber. A typical 38

58 Fig. 3.1: A schematic diagram of a MBE system showing its different components [50]. schematic diagram of the important components of an MBE system is shown in Fig.3.1. The solid source materials are placed in evaporation cells, called Kundsen cells, which provide an angular distribution of atoms or molecules in a beam. The substrate is heated to the necessary temperature and, when needed, can be continuously rotated to improve the growth homogeneity. There are two steps for MBE operation. In the first step the solid source materials, the constituent elements of the material to be grown, are placed in the evaporation cells. Each material is evaporated, collimated into a beam, and directed toward the hot substrate. Particles within a beam do not react or collide with one another. To have such a molecular flow, the mean free path of the particles has to be greater than the geometrical size of the chamber. An ultrahigh vacuum environment ensures the ballistic nature of the beam. The heated substrate is rotated to ensure a uniform deposition rate across it. 39

59 In the second step, the evaporated atoms from the different Kundsen cells are deposited on the hot substrate. The substrate is cleaned, loaded through the load lock, and adjusted so that it faces all the cells from which hot beams of materials emanate. The as-deposited film profile depends on the deposition rate, surface temperature, surface material, and crystallographic orientation. During deposition ultrahigh vacuum (10-11 Torr) is maintained in the chamber via a cryopump. The film profile can be accurately analyzed using in situ reflection high energy electron diffraction (RHEED) technique. In the beginning, it shows a particular intensity when there is no growth. The intensity of the RHEED pattern starts oscillating with the growth of a layer. When a monolayer growth is completed the pattern returns to the initial intensity. 3.3 InAs/InGaAs/InAlAs quantum well structure For our work, a 2DEG system formed using an InAs/InGaAs quantum well (QW) is used to fabricate a 1D channel. The InAs 2DEG samples were obtained from Intelligent Epitaxy Technology, Inc (IntelliEPI). It was grown using the MBE technique so as to be of high purity and defect-free (at the interface of different semiconductors) for low temperature (4.2 K) operation. In this heterostructure, a thin layer of InAs (low bandgap ~ 0.36 ev) is sandwiched between two layers of InGaAs (large bandgap ~ 0.76 ev), thus forming the QW structure as shown in Fig Mobile electrons are trapped in the QW. Their motion is restricted to move along the growth direction (z), but they are free to move along the other two spatial directions (i.e., x and y). Since the electrons in the quantum well are free only to move in a plane, such a system is called a two-dimensional electron gas, or 2DEG for short. 40

60 (a) (b) Fig. 3.2: (a) InAs QW formation using an InAs/InGaAs hetrostructure. For materials far apart (i.e. before MBE growth), the Fermi energy level (E F ) is at a different location for the different semiconductos. (b) When grown by MBE, E F is the same throughout the entire heterostructure at equilibrium. If we assume the conduction band discontinuity at the InAs/InGaAs interface in Fig. 2 to be infinite, the quantized energy levels and the corresponding wavefunctions of the 1D infinite potential well are given by: ( ) ( ) ( ) 41

61 where n (=1, 2, 3,.) is the quantum number associated with different energy levels, a is the width of the 1D potential well, m* the effective mass of electron in the well. and ħ the reduced Planck s constant. In equation (3.2), A n is a normalization constant. Figure 3 shows the discrete energy levels and their corresponding wavefunctions. (a) (b) Fig. 3.3: (a) The quantized energy level of 1D potential well. (b) Wave functions corresponding to different quantum numbers, n (=1, 2, 3,.) [50]. In a QW, the electrons are free to move in a plane (say, xy) and are constrained along the third spatial direction (i.e., z). The total energy of an electron in each subband is given by: ( ) ( ) ( ) where, E n is given by the Eq. (3.1) and k =(k x 2 +k y 2 ) 1/2 is the wave-vector in the (x,y) plane. For a fixed value of n, Eq. (3.3) is the energy dispersion relation for each subband. 42

62 The number of quantum (electronic) states per unit energy is referred to as the density of states (DOS), denoted by ge, ( ) and it indicates how densely the quantum states in a particular system are packed in an energy interval. The number of quantum states between energy E and E+dE is therefore given by g( E) de. Fig. 3.4: The DOS for the quantum well and its relation to the 1D energy sub-band diagram [50]. For a 2D system where electrons are bound in one direction and free to move along the other two directions, the DOS is given by [51]: g(e) = ( ) It is seen that the DOS is independent of energy and only depends on effective mass of the electrons (m*), which is constant for each subband. The DOS of a 2DEG has a staircase behavior as a function of energy as shown by the blue curve of Fig

63 3.4 Structure and Layer Sequence of InAs 2DEG Sample Figure 3.5(a) shows the InAs/InGaAs 2DEG sample used in this research work, with its different constituent layers. This is a specially grown quantum well structure with high purity and low defects (to have less scattering during conduction) in the 2DEG region. Figure 3.5(b) shows an AFM image of a QPC device. The InAs/In 0.53 Ga 0.47 As quantum well is obtained from a modulation doped quantum heterostructure. The growth of the heterostructure starts with a thick semi-insulating InP substrate. A 300 nm In 0.52 Al 0.48 As buffer layer is grown on the substrate. A 7 nm n-doped In 0.52 Al 0.48 As layer supplies electrons to the symmetric InAs quantum well (of thickness 3.5 nm) formed between two 10 nm In 0.53 Ga 0.47 As layers. The modulation doping has two precise advantages: (a) it separates the electrons from their donors to reduce scattering by ionized impurities, and (b) restricts the electrons in 2-dimensions [51]. A 10 nm In 0.52 Al 0.48 As spacer layer between the n-in 0.52 Al 0.48 As and In 0.53 Ga 0.47 As increases the separation between electrons and the donors. It can further reduce the scattering, but at the expense of lowering carrier density in the 2DEG. In our particular context of low temperature experiments, we are mostly interested in achieving a high mobility 2DEG, and less interested in the electron density. Both GaAs and AlAs have nearly same lattice constant. So, they are not distorted when stacked one on other in a heterostructure. Moreover, layer of In 0.52 Ga 0.48 As is lattice-matched to the InP substrate [51]. On the top, a 2 nm InAs cap layer is deposited to prevent oxidation of the active layers. Also, for InAs the Fermi level is pinned far above the conduction band minimum making it easier to deposit ohmic contacts on it. 44

64 The InAs well is under compressive strain since the lattice constant of InAs (a InAs = Å) is larger than the lattice constant of the surrounding material which is lattice-matched to InP (a InP = Å). As a result, dislocations can appear at the InAs/InAlAs interfaces as well as dangling bonds at the InAs/vacuum interfaces after trenches are etched through the 2DEG. These imperfections will lead to scattering in the narrow portion of the QPC devices formed using this heterostructures, as will be discussed in Chapter 5. The InAs 2DEG samples were characterized by standard quantum Hall and Shubnikov de Hass (SdH) measurements on a Hall bar. From those, the mobility and carrier (electron) concentration were calculated. The details of 2DEG characterization are described in chapter 5. 45

65 (a) (b) Fig. 3.5: (a) A schematic cross-section of the InAs/InGaAs heterostructure used to make the QPC. The grey area indicates the etched portion which defines the QPC trench. (b) A three-dimensional AFM image of a QPC with two in-plane side gates (G1 and G2) fabricated with chemical wet-etching technique. 46

66 3.5 Device Fabrication and Processing Steps The devices were fabricated in cleanroom environment (class 100) using electron-beam lithography (EBL) and UV-photolithography. First, EBL is used to write the fine quantum point contact (QPC) structures, and then UV lithography is used to write the isolation trench and ohmic contacts. The isolation trenches completely isolate the QPC device from the rest of the wafer. The principal processing steps involved in the fabrication process are: EBL for writing the small features (up to a few hundreds of nanometers) to define the QPCs. UV-photolithography to write the isolation trenches and ohmics (micron size). Chemical development and etching after each type of lithography. Metallization for ohmics, followed by metal lift-off. Atomic force microscopy to check different features of the as-prepared QPCs, e.g. trench wall roughness, trench depth, 1D channel width, etc. Annealing of ohmic contacts. Scribing and bonding Wafer Cleaning A 5 mm 5 mm wafer chip is diced from a two-inch circular wafer. The chip/sample is soaked in hot (~ 60 C) acetone, methanol and isopropanol, 10 minutes each, followed by oxygen plasma treatment (using reactive ion etching) for 40 sec. An oxygen plasma treatment is used to burn out the organics. Then it is pre-etched in 4% HCl for 5 minutes (to remove possible oxide 47

67 layers grown on the cap layer of InAs heterostructure), flushed in DI water, blown with dry nitrogen and prebaked on hotplate at 185 C for 5 min. Prebaking helps drive off the moisture and residual water vapor from the wafer surface. Then e-beam resist (PPMA) is spun on the wafer at 5000 rpm for 60 sec. Before spinning the resist, the sample surface is examined under a high resolution optical microscope to make sure it is completely clean and no residual dust particles are on it. The entire cleaning steps are done in the cleanroom Resist Spinning a. E-Beam Resist (PMMA) For defining the small QPC structures by EBL, the wafer chip is coated with polymethylcrylate (PPMA) resist. PMMA is a positive electron beam resist dissolved either in anisole or in chlorobenzene, so those regions exposed to the electron beam are removed after developing in a suitable solvent (discussed later). A too-thin resist layer will cause the wafer surface to be exposed to an excessive electron dose which may damage it. A too-thick layer of resist will not receive enough of an electron dose for it to dissolve under the chemical action of the developer. Therefore the spin time and speed need to be optimized to get the proper thickness of resist so as to have effective e-beam writing and developing. In our work we used PMMA resist with 2% anisole with molecular weight of 495. This was bought from Microchem [52]. 48

68 Fig.3.6: PMMA resist thickness variation with spinning speeds/rpm for a spinning time of 45 sec. For example, 2% anisole PMMA with 4000 rpm, or above gives a thickness ~ 50 nm [52]. A nearly 50 nm PMMA resist layer is coated on the wafer surface using a spinning speed of 5000 revolution per minute (rpm) for 60 sec. PPMA with different concentrations and spinning speeds yields resist layers of different thicknesses (see Fig. 3.6). The chip is then baked on a hot plate at 180 C for 90 sec to harden the resist. b. Photoresist For defining the micron-size isolation trenches and ohmics (using UV-photolithography) positive photoresist (PR) is used. The region exposed to UV light dissolves and is washed away by a chemical developer (discussed later). We use S1818 positive PR supplied by Shipley. A nearly two micron layer of resist is obtained using a spinning speed of 4000 rpm for 60 sec. Figure 3.7 shows the thickness variation of S1800 series PR with speed. 49

69 Fig.3.7: Thickness variation of S1800 series positive photoresist with spin speed [53] Lithographic Techniques a. Electron Beam Lithography One of the widely used tools for fabricating nanoscale devices is EBL which offers a resolution limit down to few tens of nanometers. Nanoscale devices are now being fabricated in many laboratories around the world to study various effects, such as those created by downscaling of existing devices, quantum effects in mesoscopic devices, tunneling effects in 50

70 (a) (b) Fig. 3.8: (a) Raith 150 e-beam lithography system available in UC Cleanroom. (b) The stage where the sample is loaded. superconductors, etc. Recently, efforts are on to make viable switching devices with dimensions down to the molecular level. Figure 8 shows a photograph of the Raith 150 e-beam writer available at UC. In this work, small QPC devices are written using this tool. The machine is kept in a gold room in our UC Cleanroom (to prevent UV light coming in). It can also be used to take scanning electron micrograph (SEM) to analyze the two-dimensional surface texture of a sample. In the Raith 150 e-beam writer, an electron beam, with a Gaussian distribution (energy profile) scans over the PMMA coated sample and write the desired design. The electron beam is generated from a tungsten tip, and accelerated with a high voltage. A block diagram of EBL is shown in Fig There are several sets of electromagnetic lenses to collimate the accelerated beam of electrons. For reasonably good writing, the beam needs to be focused properly and the aperture and stigmation alignment needs to be corrected. 51

71 The electrons in the beam scatter into the sample. Two kinds of scattering phenomena are observed for electrons penetrating the resist layer first, forward scattering a small scattering angle and inelastic in nature which creates secondary electrons with a few ev of energy. Second, large angle scattering and elastic in nature. These when coming back into the resist layer, produce more secondary electrons. In both processes the secondary electrons are responsible for breaking/weakening the polymer crosslink of PMMA. Fig. 3.9: Block diagram of a typically used EBL [54]. Several parameters need to be fixed before we write the pattern. There are two work stations, called Raith and Leo, interfaced to the Raith machine [55]. The design of the desired pattern is made using built-in CAD tools at the Raith site. They are converted to machine readable data through a GDSII file. The Leo site is for viewing the TV and SEM image of the sample under the electron gun. A joystick helps the user move the sample stage in the horizontal plane (xy-plane). The working distance (the z-direction, for focusing adjustment) can be controlled from the Leo site. The Raith 150 EBL provides an electron beam with accelerating voltages from 0-30 kv. A 10 kv beam is used throughout our work. After loading the sample 52

72 and measuring the current (useful for dose calculation), a sharp spot is burned on the sample by adjusting the working distance. A 20 nm size sharp round spot indicates a reasonably well focused beam. Also, a set of UV-global coordinates are defined to locate a point on the sample surface. With proper stigmation and aperture alignment one can move ahead to write the desired pattern. Once good focusing is attained, one needs to fix a proper dose of electrons. Dose is a measure of amount of electrons hitting the resist surface per unit area per unit time. A dose matrix is first written to fix the proper dose. In our work, a dose of 55 μc/cm 2 with beam current ~100 pa is used. Another important factor for good e-beam writing is area step size (distance between exposure spots). Ideally it should be 1/10 th of the minimum feature size. Throughout our work, we use a 7.5 micron aperture size of the e-gun to write the QPC devices. b. UV-Photolithography The UV-photolithography mask-aligner is a popular tool for patterning micron and submicron size devices. It is an optical means of transferring geometric patterns, written on a photomask, onto a substrate. For our purpose we use a dark-field chome mask on quartz glass. Before the photoresist (PR) is coated uniformly onto a substrate using a vacuum chuck spin-coater, the surface is chemically cleaned using acetone, methanol and iso-propyl alcohol, as described in detail above. Two types of photoresist are available: positive and negative. For positive resists, the resist is exposed with UV light wherever the underlying material is to be removed. Exposure to the UV light results in chemical degradation of the resist: it becomes more soluble in the developer. The exposed resist is then washed away by the developer solution, leaving windows to the bare 53

73 underlying material. The mask, therefore, contains an exact copy of the pattern which is to remain on the wafer. Negative resists behave the opposite way. Exposure to the UV light causes the negative resist to become polymerized, and more difficult to dissolve. Therefore, the negative resist remains on the surface wherever it is exposed, and the developer solution removes only the unexposed portions. Masks used for negative photoresists, therefore, contain the inverse (or photographic "negative") of the pattern to be transferred. We use a positive photoresist (S1818 from Shipley) throughout this work, so regions exposed to UV light get dissolved by the developer. After spinning the positive PR, the wafer chip is prebaked at 115 C for 60 sec. Prebaking essentially drives off the solvent in which the PR is dissolved. In this work a Karl Suss MJB3 Mask Aligner (Fig. 3.10) is used for the UV exposure for pattering the micron size isolation trenches around the device and ohmic contacts. It is mostly a manually driven machine. The basic working principles of photolithography are shown in Fig

74 Fig.3.10: A Karl Suss MJB3 Mask Aligner available in UC cleanroom (gold room). 55

75 (a) (b) Fig.3.11: (a) A chrome mask used for pattering. (b) Basic working principle of photolithography. (1) A photoresist (positive) layer is coated uniformly onto a substrate to be patterned. (2) The chome mask with the desired pattern on it. (3) Exposed with UV light. (4) After development in a chemical solution. The UV exposed parts are dissolved leaving the exact pattern of the mask on the substrate for further processing, e.g. etching, metallization, etc. 56

76 Figure 3.12 shows the schematic diagram of a typical mask aligner. The resist-coated sample is mounted on the sample holder and held by a vacuum chuck. The sample is gradually brought in soft-contact with the mask. The mask remains stationary, the sample holder can be moved through three degrees of freedom, x, y, and θ: x, y being the spatial coordinate and θ the angular coordinate for rotation of the sample in xy plane (Fig.3.12). The sample is aligned with the mask pattern by adjusting these three coordinates. Once it is complete, the sample is further lifted in upward z-direction to bring it into hard contact with the mask so that the former gets locked and cannot move. Extreme caution must be taken at this step so that the sample does not break because of excessive pressure on the sample from the mask overhead due to the hard contact. Fig. 3.12: Schematic diagram of a mask aligner with different parts. The three degrees of freedom (x, y, θ) are also shown [50]. Two photomasks (for two-step exposures) are used one for pattering the isolation trenches, and the other for ohmics (shown in Fig (a) and (b)). Photomask 1 is used to 57

77 pattern the isolation trenches onto the tiny QPC devices. The sample is exposed with UV light for 11 sec. It is is then taken out and developed, followed by postbaking on hot plate at 115 C for 60 sec. and wet chemical etching (discussed later in detail). The postbaking is necessary to harden the photoresist and improve adhesion of the photoresist to the sample surface. After the first exposure (to pattern the isolation trenches), followed by developing and etching, is complete, the resist is stripped off by soaking the sample in acetone. It is again made ready for second exposure for patterning the ohmics using photomask 2. The exposure time is same as before. After exposure the sample is dipped in cholobenzene for 90 sec and then blown with dry nitrogen. It is baked in oven at 90 C for 3 minutes before developing. The next step is metallization or metal deposition. The chlorobenzene treatment makes metal lift-off easier. (a) (b) Fig. 3.13: (a) Photomask 1 for patterning isolation trenches. (b) Photomask 2 for patterning ohmics. In both cases only the grey areas are transparent to UV light. 58

78 3.5.4 Development Development is necessary to wash away the portion of resist (PMMA or S1818) exposed either to the electron beam (in case of EBL) or to UV light (in case of photolithography), so that the sample can be etched and processed further. There are two different developing solutions. For EBL, we use a chemical solution of MIBK (methyl isobutyl keton) and IPA (isopropyl alcohol) mixed at a ratio (1:1) for 65 sec for developing the QPC trenches (to define the in-plane gates). The UV-light exposed patterns (device isolation trenches and ohmics) are developed in a mixture solution of Microposit 351 developer and de-ionized (DI) water mixed at a ratio 1:5 for 60 sec Etching and Device Isolation Etching is done after the sample is developed. It is essential to isolate the piece of 2DEG constituting a complete device from rest of the wafer. Moreover, there may be more than one device in a single wafer, therefore isolation of one device from the other is necessary. Isolation is achieved by imprinting μm wide isolation trenches around the tiny QPC devices on a wafer. Chemical wet etching technique is used to remove a portion of the wafer material to isolate the 2DEG. Since the electrical conduction takes place through the 2DEG, the trenches must be etched down through the 2DEG. In general, GaAs based material is easy to etch because its etching and other processing techniques are fairly well-established in the semiconductor industry. InAs is much less explored for device applications. It is difficult to have its controlled etching because chemical etching is very crystallographic-orientation dependent. Nevertheless, both dry and wet etching recipes are available for InAs based samples [56-59]. 59

79 Although it is known from the reported work that dry-etching offers higher aspect ratio (depth over width) of the etched pattern, wet-etching is preferred for this work because it causes less surface damage [60] to the etched and exposed wall, resulting in relatively smoother surface walls (The merits of smoother trench walls on the QPC device are described in detail in the results and discussion part). For our work we use an acetic acid based etchant. It is prepared in a glass beaker by carefully mixing acetic acid (CH 3 COOH), hydrogen peroxide (H 2 O 2 ) and DI water (H 2 O) at a ratio 15:20:125. The etching recipe was obtained from Mark Johnson at NRL Lab, Washington DC. The wafer with isolation trenches/qpc devices is submerged into the etchant solution. Etching is stopped by rinsing the wafer in flowing tap water. The etching durations for (a) micron size device isolation trenches and (b) tiny QPC trenches are 60 sec and 25 sec, respectively. The etching rate is found to be ~ 4 nm/sec. Initially, the exact etching time is optimized by repeatedly checking the trench depth in a profiler and AFM. Note that the etchant must contain an oxidizing agent and be free from any metallic cations to avoid ionic contamination of the etched surface. This can result in unwanted surface leakage current in the device application [61]. The etchant works by first oxidizing the surface and then dissolving the oxide, thereby removing some of the underlying atoms of the semiconductor. Hydrogen peroxide is an oxidizing agent; acetic acid dissolves the resulting oxide. Figure 3.14 (a) and (b) show the device and QPC isolation trenches cut by wet etching technique. It is important to check if a particular device is properly isolated from the rest of the devices on the same wafer. This is done using a two-probe dc technique as discussed in chapter 4. 60

80 (a) (b) Fig. 3.14: (a) The device isolation trenches which separate the device under consideration from the rest of the wafer. The tiny QPC sits inside the green circle. (b) Atomic force micrograph (AFM) of a QPC showing the trenches, patterned by e-beam lithography first, and then wet-etching technique. The trenches eventually define the quasi one-dimensional channel region in between Metal Deposition and Lift-off a. Deposition Metallization or metal deposition is needed to deposit the ohmic contacts (or ohmics). It is carried out in the closed chamber of a deposition system (Cooke vacuum Products, CVE-600- EB-FR-S-DC) under high vacuum condition (~ Torr). The system uses both e-beam and resistive evaporation techniques. The ohmics consist of three layers: Ni (12 nm), Ge (20 nm) and Au (200 nm). Ni and Ge are deposited by e-beam evaporation and Au by resistive heating. The deposition rate is different for each element. Ni and Ge are deposited at a rate of 1Å/sec and Au 61

81 at 5 Å/sec. The whole deposition is done in a single shot without breaking the high vacuum. After the deposition is complete the chamber is vented with dry nitrogen for a few minutes and the sample is unloaded. The next step is metal lift-off. b. Lift-off The lift-off is a fairly easy process. After metallization the sample is kept submerged in hot (~50 C) acetone for a few hours. The acetone removes the resist, along with the unnecessary part of the metal sheath, leaving only the ohmics on the sample surface. Figure 3.15 shows the metallic ohmics after lift-off. Fig 3.15: Ohmics (in golden color) after metal lift-off. 62

82 3.5.7 Atomic Force Microscope Atomic force microscopy (AFM) is used to image the surface topography on a submicron scale. It is a form of scanning probe microscopy (SPM). A schematic diagram is shown in Fig The technique involves the use of a shaped tip with an approximate radius of nm. A feedback mechanism is used that measures the tip s interaction with the surface and holds the tip several nanometers above the surface. While scanning across the sample, the tip height variation is recorded to produce a topographic image of the surface. The tip is positioned at the end of a diving-board-shaped cantilever beam. The attractive and repulsive forces between the tip and the sample surface deflect the cantilever beam. A laser beam, reflected from the very end of the cantilever, captures the magnitude of deflection. The plot of laser deflection as a function of tip position constitutes the topography of the sample surface. Fig 3.16: Schematic diagram of an AFM showing the different components [50]. 63

83 The AFM has three different modes of operation: contact, non-contact and tapping. In the contact mode the tip always remains in contact with the sample surface. This mode is good only for solid samples. In the tapping mode, the cantilever is driven by a small piezoelectric element mounted in the AFM tip holder and made to oscillate up and down near its resonance frequency. The frequency of oscillation is about 500 to 50,000 cycles/min. Due to the forces acting on the cantilever, when the tip comes close to the surface, van der waal forces, or dipole-dipole interactions, electrostatic forces, etc. cause the amplitude of this oscillation to decrease as the tip gets closer to the sample. In the non-contact mode, the tip does not touch the sample surface. The cantilever oscillates at a frequency slightly above its resonance frequency, where the amplitude of oscillation is typically a few nanometers. For our purpose, we use a 10 nm diameter tip and the tapping mode of operation for scanning the QPC structures. A Veeco Dimension 3100 AFM (shown in Fig. 3.17(a)) is used to get a three dimensional image scan of the QPCs. An AFM scan provides the depth and width of the QPC trench (which defines the in-plane side gates) as well as the QPC channel width. Figure 3.17(b) shows a typical AFM scan of a QPC device presenting different dimensions of the channel, trenches, etc. 64

84 (a) (b) Fig. 3.17: (a) A Veeco Dimension 3100 Model of AFM used in this work (top). (b) A typical AFM scan showing trench width, channel width and trench depth of a QPC (bottom). 65

85 3.5.8 Annealing After the ohmics deposition and lift-off, the sample is annealed. It is done using a rapid thermal annealing set-up (Model: AG associates, Heatpulse 210T RTA) at 350 C for 120 sec. RTA helps in alloy formation (Au-Ge) and diffusion of germanium into the 2DEG to create good ohmics. The diffused germanium (into the wafer) acts as a dopant. The nickel acts as a wetting agent which prevents Au-Ge balling up during alloy formation Scribing and Bonding This is the last step of device fabrication. There are several QPC devices in a single chip. They are scribed (using a wafer scriber, model: C sn 1267-C) to separate them and one piece is glued to a chip carrier, using General Electric (GE) varnish. A wedge bonder (Kullicke and Soffa model 4123) is used to bond wires from the devices to the chip carrier using 25 mil diameter aluminum wires. The bonded chip carrier is then mounted on to the cryogenic insert for measurements. Figure 3.18 shows a complete bonded device. Fig. 3.18: A wire bonded device. 66

86 Chapter 4 Experimental Techniques 67

87 4.1 Introduction Our device properties were studied by measuring their linear conductance, G = I/V. This was done using a standard four-probe AC lock-in technique. In general there are two ways to measure the conductance of a device: apply a constant voltage between two points, such as the source and drain, and measure the current flowing between the points, or fix the current and measure the voltage. In this work, we followed the first procedure. All our measurements were carried out inside an RF screened room (to avoid noise and other electromagnetic disturbances) and at liquid helium temperature (4.2 K). 4.2 Measurement Set-up Figure 4.1(a) shows our experimental set-up. It consists of a liquid helium (LHe) dewar containing a dilution refrigerator (DR) probe (Fig.4.1(b)) and a superconducting magnet coil capable of producing fields up to 9 T. The electronics rack holds lock-in amplifiers, digital voltmeters, a function generator, a dc battery system (0-12 volts), and a liquid helium meter. All the components of the standard LHe cryostat used for transport measurement came from American Magnetics (AMI). We note that the DR probe was used as a simple 4.2 K probe throughout the work. The superconducting magnet is powered by a AMI Model 420 constant current source and a digital controller. In our experiments, the field was always perpendicular to the device plane. 68

88 (a) (c) Fig.4.1: (a) The measurement set-up used for low temperature transport measurement. (b) The tail of the DR probe with its main components marked. (c) An image of a bonded sample mounted in the sample holder of the DR probe. 69

89 4.2.1 Device Quality Check The probe with the QPC device mounted in it was inserted slowly into the LHe dewar to avoid sudden thermal shocks. After that the electrical connections to the probe were made using coaxial cables. The next task was to check the quality of the ohmic contacts and the device isolation. We wanted good quality ohmics in proper contact with the two-dimensional gas (2DEG) (see chapter 3 for details). Figures 4.2 (a) and (b) are top views of a device and the QPC constriction, respectively. The contact resistance of the ohmics was measured using a two-probe circuit (Fig.4.3 (a)). A small AC current was passed between two pads, and the voltage drop was measured using a lock-in amplifier. Fig. 4.2: (a) Typical layout of a QPC device. The 8 golden pads are the ohmics deposited on the top of the wafer. Pads S and D are the source and drain, respectively. Pads 2 & 5 are the in-plane side-gates. Pads 1 & 3 or 4 & 6 are the pairs of voltage probes to measure the voltage across the QPC channel (inside the red circle). (b) An AFM image (3D front view) of a QPC device showing the channel (between pads S and D ) and the in-plane side-gates (pad # 2, 5). Dark red areas are the isolation trenches cut by e- beam lithography and wet etching technique to define the side-gates. 70

90 Contact pad # Resistance (kω) at T= 300K Resistance (kω) at T= 4.2K S-D S-1 or S D-3 or D S-2 or S-5 Few MΩ No signal D-3 or D-5 Few MΩ No signal Table 4.1: Resistance values of different pairs of ohmics at T=300K and T= 4.2K. Table 4.1 shows some typical resistance values for different pairs of ohmics at T= 300 K and T= 4.2 K. If the ohmic quality is good, the resistance values are expected to decrease from room temperature to 4.2 K. They are found to decrease by a factor ~ 1.5. A simple circuit, as shown in Fig. 4.3 (a), was used to check the gate leakage. A voltage (0-15 V) was applied to the gate from the function generator and the current through the 2DEG was measured using a digital volt meter. This measurement was made at T=4.2 K. Figure 4.3(b) shows that no current flows between the gate and ground via the 2DEG; only noise is seen. This indicates the gates were leakage-free. No signal between any current pad (either source or drain) and any side-gate indicates that the gates were in complete electrical isolation from the QPC channel (at T= 4.2 K). This is a very important requirement for effective conductance measurements in a side-gated QPC device. 71

91 R = 1 k V D FG V I Gate 2DEG Ground Ground (a) (b) Fig. 4.3: (a) The circuit for gate leakage check. The function generator (FG) provides the variable AC voltages. The voltage across the standard 1 kohm resistance was applied to the ground via 2DEG and current was recorded. (b) Leakage current as a function of gate voltage applied from the FG. Current (noise) of the order of few nanoamperes means that the side-gates are completely leakage-free Conductance Measurement in QPC Device The low temperature conductance measurements were made using standard lock-in techniques with equipments obtained from commercial vendors. The major components are AMETEK Model 5210 dual-phase lock-in amplifiers, a Keithly 2000 multimeter, an Agilent 33220A function generator, and an Agilent E 3642A DC power supply. A homemade dc power supply was used to apply bias voltages to the side-gates. Initially, QPC devices with lithographic channel widths ranging from 250 nm to 400 nm, and lengths of the order of 500 nm, were tested. The effective width and the carrier density in the channel was controlled by the bias voltages on the two side-gates. Since we are interested in the fundamental transport mode, we want the 1D subband separation to be large which can be achieved in QPCs with small channel widths. In a 72

92 QPC with top or split gates, where the 1D channel is created just by depleting the 2DEG underneath by application of negative bias potential to its gates, an asymmetric bias cannot be applied effectively, because that will simply shift the channel. But, it can be easily done in a side-gated QPC, because the side gates which create the 1D channel are already defined by cutting trenches. This is the main reason why we chose to work with side-gated QPCs. Since there is very little surface depletion at the InAs 2DEG/vacuum interface, we can have a conducting channel (at 4.2 K) for a QPC with a very narrow channel width. This is an added advantage for InAs side-gated QPCs. During our experiments we observed this was not true for GaAs 2DEGs, because the latter has a large surface depletion. It is extremely difficult to get a side-gated GaAs QPC device with a conducting channel at 4.2 K. The conductance in the QPC channel was measured as a function of gate voltage. The core idea was to record the current (I) flowing through the narrow channel (as a result of the application of the small drive voltage between the source and drain), and the voltage drop (V) across it. The linear conductance was calculated by dividing the current by the voltage (G= I/V). [Note that a necessary condition to avoid electron heating in the channel is to keep ev DS << kt. This is to avoid thermal smearing.] The current and voltage were measured at 17 Hz using two synchronized lock-in amplifiers. In all measurements, V DS was set to 100μV. The data points were collected by a computer using LabVIEW, interfaced with the different components of the circuit. As mentioned, all measurements were carried out at T= 4.2 K and inside a screened room. The lithographic width of the QPC channel was changed by applying bias voltages to the metallic in-plane side gates, depleting the channel near the side walls of the QPC. Battery operated DC voltage sources were used to apply constant voltages, V G1 and V G2, to the two gates. 73

93 (a) (b) Fig. 4.4: (a) Circuit diagram for conductance measurements in a QPC channel. The drive voltage (V DS ), from voltage source V osc, between the source (S) and drain (D) creates a current through the narrow channel. The current flows in x-direction. The dc voltage applied to the side-gates (G1 and G2) provides electrostatic confinement (along y) to the electrons in the channel. The voltage drop across the channel (i.e. between the two voltage probes (denoted by pad V)) is measured by a digital voltmeter (shown in blue circle). (b) A typical conductance plot of a InAs QPC channel as a function of common sweep voltage (V G ) applied to both gates. The conductance was measured in units of 2e 2 /h. 74

94 An asymmetric potential ΔV G =V G1 V G2 was applied between the two side-gates to create spin polarization in the channel. The QPC conductance was then recorded as a function of a common sweep voltage, V G, applied to the two gates (in addition to the potentials V G1 and V G2 which create the asymmetry), with the current (Fig. 4.4(a)) flowing in the x-direction. The linear conductance G (=I/V) of the channel was measured for different ΔV G as a function of V G, with a drain-source drive voltage of 100 V. At the outset, each of the conductance curves was cycled a few times until the hysteresis was minimized. This was done to avoid contributions from the impurities (that are present at the vacuum/2deg interface) to the net conductance of the QPC. A single conductance plot is shown in Fig. 4.4(b). We also measured the magnetic field dependence of the conductance as a function of the sweep voltage V G. The magnetic field was perpendicular to the device plane or the 2DEG. 75

95 Chapter 5 Results and Discussion 76

96 5.1 Introduction In this chapter we report our experimental results for low temperature, low noise, conductance measurements on InAs QPC devices. The chapter is divided into two parts. First, we detail the characterization of an InAs two-dimensional electron gas (2DEG), and second, we discuss the results and interpretation of QPC conductance. The 2DEG was characterized using a standard Hall bar structure. The conductance measurements were carried out on a onedimensional QPC channel with in-plane side gates defined by cutting deep trenches using e- beam lithography and wet etching techniques. The details of QPC fabrication steps can be found in Chapter 3. The low temperature conductance measurement techniques are described in Chapter Characterization of an InAs 2DEG The formation of a 2DEG at the heterointerface of an InAs/InGaAs/InAlAs quantum well, and the layer sequence of the complete heterostructure were detailed in Sections 3.3 and 3.4 of Chapter 3. Standard Hall and Shubnikov de Hass (SdH) measurements were used to find the carrier concentration (n) and mobility (μ) of the 2DEG Classical and Quantum Hall Effect In 1879, E. H. Hall observed that opposite charges accumulate on the sides of a current carrying conductor when it is placed in a perpendicular magnetic field. In simple terms, the magnetic field (B) exerts a force ( ev B) on the charged carriers that is perpendicular to the transport current, as shown in Fig This is known as the Hall effect. Since the current is 77

97 allowed to flow in the x-direction, an electric field, called the Hall field, will develop due to this charge accumulation. The Hall field is given by, E y = E H = R H J x B (5.1) R H is known as the Hall coefficient for sample material and is given by, R H = (5.2) Fig. 5.1: Schematic representation of the classical Hall effect. The current flows along x-axis. The magnetic field (B) points along z-axis. The transverse accumulation of charge gives rise to the Hall field along y-axis. In the classical regime, the magnetic field vs. transverse resistance plot is linear (Fig. 5.2). dr R H is the slope ( ) of this linear region [51]. The electron density of the 2DEG can be db calculated from [29], n 1 er H e 1 dr db (5.3) 78

98 R Hall (Ohm) The electron mobility, μ is obtained from [29], dr RH db o (5.4) o where o is the sheet resistivity InAs 2DEG T= 4.2 K RSdH (Ohm) B (Tesla) Fig. 5.2: Quantum Hall (blue) and SdH (red) measurements on an InAs Hall bar at 4.2 K. In a real 2D system when the magnetic field is high, the Hall resistance shows step-like behavior, as shown in Fig Klaus von Klitzing [62] discovered that the resistance is quantized in steps of h/ne 2, where n is an integer. This is known as the quantum Hall effect. This phenomenon can be used to determine the electron concentration (n) and mobility (µ) of a 2DEG. 79

99 5.2.2 Shubnikov de Hass (SdH) Oscillations When a perpendicular magnetic field (Bẑ) is applied to a 2DEG lying in the xy-plane, the two-dimensional density of states consists of sharp delta-function located at the Landau levels with quantized energies given by: E n 1 ( n ) c 2 (5.5) eb where n takes integer values. c is the cyclotron frequency of the electrons in the 2DEG. m Each Landau level is composed of a number of degenerate electronic states; the allowed number of such states in each Landau level per unit area is eb/h, assuming the spins are not degenerate in a magnetic field. The density of states of the electrons in a 2DEG shows continuous step-like behavior. For non-zero magnetic field, it is replaced by a sequence of delta-functions [51]. This is true only when there is no electron scattering (i.e., the time interval between two scattering events is infinite). In practice, there is always scattering (e.g., impurity, phonon scattering) and these delta-functions are broadened (due to the uncertainty relation) with an energy separation of c between two subsequent levels (Fig. 5.3 (a)). As the magnetic field increases, more electrons can be accommodated in each of the Landau levels (because of increased number of states at each Landau level). In this process, the higher levels gradually become emptied, as the total number of electrons in the system has to remain unaltered. We know that the Fermi energy is the maximum energy of the occupied states. Thus changing the magnetic field makes the Fermi level move through the Landau levels. In other words, the Landau levels pass through the Fermi energy as the magnetic field is changed. When the Fermi energy falls in the energy gap between two Landau levels, the conductance goes to a minimum because there are no electronic states available for conduction to take place. Interestingly, the resistance is proportional to the 80

100 conductance in this case [51], and the drop in conductance is accompanied by a similar drop in resistance. As the Fermi energy moves inside a Landau level, the conductance increases again, and so does the resistance. Thus the resistance of a 2DEG oscillates as a function of magnetic field. These oscillations are known as Shubnikov-de Haas (SdH) oscillations [62, 63] R SdH (Ohm) (a) (b) 1/B (1/Tesla) Fig. 5.3: (a) Density of states in the first subband in magnetic field [51]. (b) Periodic SdH oscillations observed in InAs 2DEG. If the resistance is plotted against 1/B, periodic SdH oscillations are observed. Knowing the period, the 2DEG carrier density (n) can be calculated from [62, 63], 2e P1 / B (5.6) hn Note that since the SdH oscillations are a special characteristic of a 2DEG, Eq. (5.6) is more accurate than Eq. (5.3) for calculating the carrier density, n. 81

101 Our SdH and quantum Hall measurements performed on a simple Hall bar structure yielded the electron density and electron mobility of the InAs 2DEG, /m 2 and 3.67 m 2 /Vs respectively. 5.3 Experimental Results and Discussion For more than a decade, there have been many experimental reports of anomalies in the quantized conductance of quantum point contacts (QPCs). These anomalies appear at non-integer multiples of G 0 = (2e 2 /h), and include the observation of anomalous conductance plateaus around 0.5G 0 and 0.7G 0 [21, 63-71]. There is a growing consensus that these conductance anomalies are indirect evidence for the onset of spin polarization in the narrow portion of the QPC [21, 72-77]. There is also mounting evidence that the number and location of the conductance anomalies can be further tuned by deliberately introducing a broken symmetry in the electrostatic confinement in the narrow portion of the QPC [78, 79]. More recently, the change in the impurity potential in a GaAs QPC with an asymmetric lateral confinement due to an offset bias between two spit-gates has been shown to strongly affect the location of the conductance anomalies [80]. Recently, P. Debray et al. [21] obtained preliminary results showing that the lateral spin orbit coupling (LSOC), resulting from the lateral in-plane electric field of the confining potential of a QPC with in-plane side gates, can be used to create a strongly spinpolarized current by purely electrical means in the absence of any applied magnetic field. A nonequilibrium Green s function (NEGF) analysis that modeled a small QPC [21, 25] suggested that three ingredients are paramount for generating a strong spin polarization: an asymmetric lateral confinement, a LSOC induced by the lateral confining potential of the QPC, and a strong electron-electron (e-e) Coulomb interaction. 82

102 From a practical standpoint, it is important to assess the sensitivity of these three ingredients to the bias difference between the two gates. This issue was not addressed in our group s earlier work [21]. The first part of the experimental results and discussion section presented below addresses this issue explicitly. If an appropriate biasing range can be found, one which leads to a robust conductance anomaly, such a QPC could be used as a tunable spin polarizer or analyzer. Our conductance measurements show evidence of surface scattering, due to surface roughness and dangling bonds on the side walls of the narrow portion of the QPC. This assertion is further supported by applying a magnetic field perpendicular to the QPC plane. In the second part of this section, a more detailed and systematic study of the influence of surface scattering on the QPC conductance is made with the polarities of the gate potentials reversed. We present a simple theoretical model of surface and dangling bond scattering which qualitatively explains the difference in the number and location of conductance anomalies when the polarity of the offset bias between the gates are reversed. The NEGF simulations performed on a simple model of a QPC channel with dangling bonds (modeled as impurities) on its side walls produce conductance anomalies which are found to be in good agreement with experiments. We further show that the QPC spin conductance polarization can still be fairly large (98%) even in the presence of dangling bonds. 83

103 Fig. 5.4: A three-dimensional AFM image of a QPC with two in-plane gates (G1 and G2), fabricated using a chemical wet etching technique. The current flows in the x-direction. An asymmetric LSOC is generated using an asymmetric bias between the two gates generating an electric field in the y-direction. All the low temperature (4.2 K) conductance measurements for this thesis were made using the InAs QPC device shown in Fig The in-plane side gates, G1 and G2, are defined using e- beam lithography and wet etching techniques. The DC voltages V G1 and V G2, applied to gate G1 and G2, respectively, create an asymmetric potential profile in the narrowest part of the QPC. The asymmetry in the bias potential, ΔV G =V G1 V G2, is instrumental to the generation of a spin polarized current [21]. The linear conductance in the QPC channel, G=I/V, was recorded as a function of a common sweep voltage, V G, applied to the two gates, in addition to the potentials V G1 and V G2, with the current (Fig. 5.4) flowing in the x-direction. For all values of ΔV G, the gates were found to be non-leaking. The details of how the QPC conductance was measured can be found in chapter 4. 84

104 G(2e 2 /h) Conductance Measurement: Part I a. Results Figure 5.5 shows the conductance of the QPC as a function of the common sweep voltage V G for different asymmetric biases (ΔV G =V G1 V G2 ) between the gates. In Fig. 5.5, the left-most curve shows the conductance for the symmetric case, i.e., with only the common sweep voltage V G applied to the gates. For the other curves, from left to right, the potential V G2 applied to gate G2 is fixed at -2.0V and the potential V G1 on gate G1 is varied from -0.1 to -6.5 V, the latter corresponding to a large asymmetry between the two gates. As can be seen from Fig. 5.5, an anomalous plateau (around 0.4G 0 ) is only observed for an intermediate range of bias ΔV G. Quite remarkably, it appears over a maximum sweep voltage (V G ) range of nearly 1 V. 1.2 T=4.2K V G (V) Fig. 5.5: The conductance of the QPC (in units of 2e 2 /h) measured as a function of the common sweep voltage V G applied to the in-plane gates, at T=4.2 K. The sweep voltage, V G is superimposed on initial 85

105 potentials V G1 and V G2 applied to the gates to create an asymmetry. The left-most curve shows the conductance for the symmetric case; i.e., with only the common sweep voltage V G applied to the gates. For the other curves, from left to right, the initial potential V G2 applied to gate G2 is fixed at -2.0V and the initial potential V G1 on gate G1 is equal to 0.0, -0.1, -0.3, -0.6, -0.9, -1.2, -1.5, -1.8, -2.0, -2.3, -2.6, -2.9, - 3.1, -3.4, -3.7, -4.0, -4.5, -5.0, -5.5 and -6.5 V, respectively. The reason for applying negative potentials V G1 and V G2 on the gates was to push the electrons away from the side walls and reduce the effects of surface roughness scattering. Indeed, a three-dimensional atomic force micrograph of the QPC device, shown in Fig. 5.4, indicates that the side walls of the QPC are rather ragged (especially in the vicinity of the constriction), a result of the wet etching process used to define the trenches. Surface scattering from this roughness is expected to play a critical role in explaining the conductance data, for which we provide the following explanation. Also, we have studied the evolution of anomalous conductance plateau (at 0.4G 0 ) as a function of magnetic field (Fig. 5.6). The magnetic field is applied perpendicular to the device plane (xy-plane), or the 2DEG. The sweep voltage, V G is superimposed on gate biases of V G1 = -1.0 V and V G2 = 0 V. With increasing of magnetic field the anomalous plateau slowly rises and finally evolves to the normal conductance plateau at G 0. 86

106 G(2e 2 /h) 1.5 T=4.2K B= 7.5 T B= 0 T V G (V) Fig. 5.6: The conductance (in units of 2e 2 /h) in a magnetic field, versus the common sweep voltage V G applied to the two in-plane gates, at T=4.2 K. Prior to the application of the common gate bias, the initial biases V G1 and V G2 were set equal to -1V and 0V, respectively. The different curves correspond to different values of the constant magnetic field applied perpendicular to the 2DEG. The plots corresponding to B = 0T and 7.5T are shown by arrows. From bottom to top, the other curves correspond to magnetic field values of 3.0 T, 5.5 T, 6.0 T, 6.5 T and 7.0 T, respectively. b. Discussion The evolution of the anomalous plateau with ΔV G is interpreted as follows. The left-most curve in Fig. 5.5 corresponds to the symmetric case, i.e., there was only the common sweep voltage V G applied to the gates. The conductance curve is rather smooth, with no major features 87

107 at 0.4 or 1.0 G 0. We attribute this to significant elastic scattering in the narrow portion of the QPC, due either to surface roughness scattering or dangling bonds at both channel/vacuum interfaces, as supported by the surface ruggedness around the QPC observed using the AFM, Fig Since it has been known since the early 1990s that impurity scattering eventually leads to the disappearance of the integer conductance plateaus in symmetrically biased QPCs [81-86], the absence of clear features in the conductance for a symmetric bias is indirect evidence of surface scattering from the side walls. Hence we applied a negative bias to both in-plane side gates when studying the influence of the bias asymmetry. These negative biases push the electrons away from the side walls making transport through the channel more ballistic. The asymmetric bias eventually leads to spin polarization in the channel, triggered by the imbalance of the LSOC on the two sides of the channel, as discussed in detail in our group s earlier work [21]. Despite the different negative biases (V G1 and V G2 ) applied to the gates to create the asymmetry, when the sweep voltage increases, the total potential on either gate will eventually approach zero and the importance of surface scattering will reappear. This assertion is supported by the fact that there is still some evidence of elastic scattering in the channel: the normal conductance plateau is not exactly at G 0. The fact that the conductance anomaly is located at 0.4 G 0 and not 0.5 G 0 is in agreement with our recent NEGF simulations of the influence of impurity scattering on the location of the anomalous plateau. There we showed that conductance anomalies can appear at values different from 0.5 G 0 if the transport through the QPC is not truly ballistic [49]. With the increase of the asymmetric potential, the 0.4 plateau is prominent over an intermediate range ΔV G around 3 V. This suggests that a strong enough imbalance in LSOC between the two sides of the QPC is required to create the spin polarization. However, the 0.4 plateau eventually vanishes for larger value of ΔV G. We interpret this as follows. When the bias 88

108 asymmetry is large (with a more negative bias on gate G1), we expect electrons in the channel to be squeezed towards gate G2, increasing the electron concentration on that side of the channel. As a result there is increased screening of electron-electron interactions in the channel, which inhibits the onset of spin polarization in the QPC [21, 25]. In addition, there is some influence of surface scattering on that side of the QPC as electrons are being squeezed towards gate G2. These results suggest that to use a QPC with in-plane side gates as an active device for spin polarization, tuning the bias difference between the gates to an appropriate range is required. The existence of surface scattering in our device was further confirmed by looking at the evolution of the anomalous conductance plateau as a function of a perpendicular magnetic field. Figure 5.6 shows that under the influence of magnetic confinement, the 0.4 plateau evolves smoothly towards the normal G 0. Furthermore, the latter was sharp and well-pronounced. On top of the already existing lateral confinement (along y), the perpendicular magnetic field offers an additional confinement to the channel electrons (Their cyclotron radii decreases with increasing field). Magnetic confinement therefore helps to diminish scattering from the side walls. Transport through the channel is then near-ballistic and the normal conductance plateau reappears and is well-defined. Although not shown here, the magnetic field dependence of the anomalous plateau was similar for those values of the asymmetric gate biases for which the anomalous plateau could be seen. The gradual evolution of the conductance anomaly towards the normal conductance plateau, with increasing magnetic field, is also in agreement with the increase in the electron density in the QPC channel as the magnetic field increases [21]. As a result, the effects of electron-electron interactions are diminished, prohibiting the onset of spin polarization in the channel. 89

109 5.3.2 Conductance Measurement: Part II a. Results Figures 5.7 to 5.9 display the conductance measurements under different asymmetry conditions. In these plots the voltage-axis is correctly positioned for only the zero-asymmetry case (when the initial voltage on the two in-plane side-gates, V G1 and V G2 is zero, prior to applying the common sweep voltage V G ). Fig. 5.7 (a) Forward Asymmetry: The conductance of the QPC (in units of 2e 2 /h) as a function of the sweep voltage V G applied to the gates. The sweep voltage is superimposed on the potentials V G1 and V G2 applied to the gates to create an asymmetry. The potential applied to gate G2 is fixed at +2.0V. The leftmost curve corresponds to the conductance for the symmetric case, i.e., with only the common sweep voltage V G applied to the two gates. For the other curves, the potential on gate G1 is, from left to right, -2.0, -2.4, -2.6, - 2.8, -3.0, -3.2, -3.4, -3.6, -3.8, -4.2, -5.5 and -6.5 V. (b) Reverse Asymmetry: V G dependence of conductance measurement with the bias polarity on the gates G1 and G2 switched, i.e. gate G1 is fixed at +2V, and the potential at gate G2 is varied the same way as on gate G1 in Fig. 5.7(a). 90

110 For the other conductance plots, corresponding to non-zero bias asymmetry, we have displaced the curves to the right for clarity. We arbitrarily refer to the case where V G2 is fixed and V G1 is swept to vary the bias asymmetry as forward asymmetry. The opposite situation where the biasing conditions of the two gates are interchanged is referred to as reverse asymmetry. (i) Conductance measurement (Set 1) (a) Forward asymmetry: In this set of measurements, the conductance was recorded as a function of ΔV G with V G2 held at +2V, as we gradually changed the potential V G1 from 2.0V to 5.0V. In Fig. 5.7(a), the left-most curve is for zero-asymmetry case. With increasing asymmetry, a G = 0.4G 0 plateau appears, and then disappears. (b) Reverse asymmetry: For the case of reverse asymmetry, an anomalous conductance plateau around 0.7G 0 appears (Fig. 5.7(b)). The 0.7 structure is not strong but is present for all values of the bias asymmetry. (ii) Conductance measurement (Set 2) This set of measurements was performed immediately after Set 1, with the QPC held at 4.2K. For forward asymmetry, V G2 was held at 1V throughout and V G1 was varied from 0V to 5.2V. The conductance plots are shown in Fig. 5.8(a). The leftmost curve is for the zeroasymmetry case. We see clear plateaus around 0.4G 0 and 0.7G 0, over an intermediate asymmetry range with a sudden disappearance of both plateaus when V G1 = 5.2V. In the reverse asymmetry case, shown in Fig. 5.8(b), a narrow plateau is only seen around 0.6G 0 for all values of bias asymmetry. To better illustrate the difference between forward and reverse asymmetry in the conductance, Fig. 5.9(a) is a direct comparison of the conductance plots in Figs. 5.7(a) and (b) for V G2 = 2V and V G1 = -3.2V, and for V G1 = 2V and V G2 = 3.2, using the same x-axis values for 91

111 the sweep voltage V G for both. Similarly, using the results displayed in Fig. 5.8(a) and (b), Fig. 5.9(b) shows a comparison of the conductance plots for V G2 = 2.8V and V G1 = -1V, and for V G1 = 2.8V and V G2 = 1V, again using the same sweep voltage axis. Both Figs. 5.9 (a) and (b) show how different the conductance is when the polarity of ΔV G is flipped. These results disagree with the earlier non-equilibrium Green s function (NEGF) analysis [25] of the conductance through a QPC in the presence of LSOC under the assumption of ballistic transport. There J. Wan et al. reported that the conductances are identical when plotted as a function of the common sweep voltage V G. They showed that, for the case of ballistic transport in a geometrically perfect and symmetric channel, the role of the spin-up and spin-down electrons through the channel are interchanged when the bias asymmetry is flipped, but the overall conductance stays the same. As argued next, these conductance measurements indicate the presence of surface scattering from the side walls in the narrow portion of the QPC. Fig. 5.8: (a) Forward Asymmetry: plot of conductance of the QPC (in units of 2e2/h) as a function of the sweep voltage V G applied to the gates. The sweep voltage is superimposed on the potentials V G1 and V G2 92

112 applied to the gates to create the asymmetry. The potential applied to gate G2 is fixed at -1.0V. The leftmost curve corresponds to the conductance for the symmetric case, i.e., with only the common sweep voltage V G applied to the two gates. From left to right, the potentials on gate G1 are equal to 0, 0.4, 0.8, 1.2, 1.6, 2.0, 2.4, 2.8, 3.2, 3.6, 4.0, 4.4, 4.8 and 5.2V, respectively. (b) Reverse Asymmetry: The V G dependence of the conductance with the bias polarity on gates G1 and G2 switched, i.e. gate G1 is fixed at -1.0V, and the potential on gate G2 is varied the same way as on gate G1 in Fig. 5.8(a). Fig. 5.9: (a) Data set 1: Comparison of the conductance with V G1 = -3.2V and V G2 = 2V and the reverse case, i.e., V G1 = 2V and V G2 = -3.2V. (b) Data set 2: Comparison of the conductance when V G1 = -1V and V G2 = 2.8V and the reverse case, i.e., V G1 = 2.8V and V G2 = -1V. In both figures, the same common sweep voltage axis is used for the two polarities. 93

113 b. Discussion As can be seen in the AFM scan of the QPC shown in Fig. 5.4, the side walls of the QPC are rather ragged (especially in the vicinity of the constriction), a result of the wet-etching process used to define the trenches. One of the main challenges of the wet etching process is avoiding surface states and roughness in the channel side walls which can cause carrier depletion and degradation of carrier mobility [87, 88, 89]. Therefore, surface scattering is, in part, due to the roughness of the side walls which causes variations in the potential profile (Fig.5.4). The latter results from the variation in the width of the PMMA resist, patterned during e-beam lithography, a variation transferred to the width of the trenches during the wet-etching process. Additional surface scattering is expected from the (likely) presence of dangling bonds on the QPC walls. In QPC experiments, the charge state of dangling bonds (or other impurities) is often affected during sample handling, such as temperature cycling. This typically leads to markedly different conductance traces for identical biasing conditions. We observed this in the conductance of our InAs-based QPCs when the sample was brought to room temperature between low temperature measurements. Thermal cycling is expected to change the charge state of dangling bonds formed on the side walls of the QPC during etching. 94

114 Fig. 5.10: Illustration of the conduction band energy profile between the two side gates, along a line through the middle of the QPC and perpendicular to the direction of current flow. The energy levels 1,2,3 represent dangling bonds on either side of the channel. E f is the Fermi level of the source contact. Figures (a) and (b) show the conduction profile for opposite polarities of the potential between the two side gates. Since surface roughness and dangling bonds have a significant effect on the conductance of the channel, thermal cycling will result in a large change to the conductance, which we observed. Furthermore, the application of an asymmetric offset bias will affect the charge state of dangling bonds as their energy levels are pushed up or down compared to the Fermi levels in the QPC contacts, as illustrated in Fig Since the surface roughness and the number of dangling bonds is different on the two side walls, this will lead to some level of asymmetry in the electrostatic potential in the narrow portion of the QPC, which will be reflected in the conductance measurements. 95

115 (i) Analysis of conductance set 1: For the case of forward asymmetry depicted in Fig. 5.7(a), the conductance curve (the leftmost one in Fig. 5.7(a)) corresponding to the case of zero-bias asymmetry, i.e., with V G1 = V G2 = V G, has no noticeable features, except for a weak feature around 0.4 G 0. This feature is most likely related to the built-in asymmetry of the device following etching, i.e, the amount of surface scattering and dangling bonds are different on both sides of the narrow portion of the QPC. This can lead to a spin imbalance and the onset of spin polarization in the channel which is eventually accentuated with an increase in bias asymmetry between the two gates. The pinch-off voltage for V G is about 6V and the conductance reaches G 0 for V G on the order of 3V. This means that the channel is open with no voltage on the gates. The lack of a plateau in the conductance is evidence for significant elastic scattering of electrons in the narrow portion of the QPC, due either to surface roughness scattering or dangling bonds, at both channel/vacuum interfaces, as supported by the surface raggedness in the QPC channel observed using the AFM, Fig It has been known that impurity scattering leads to the disappearance of integer conductance plateaus in symmetrically-biased QPCs [81-86], and the absence of clear features in the conductance for a symmetric bias is indirect evidence for surface scattering from the side walls. Figure 5.7(a) shows a conductance anomaly around 0.4G 0 for small bias asymmetry, which gradually shifts to about 0.6G 0 as ΔV G increases. As V G1 becomes more negative, electrons in the channel are pushed towards G2, already at a positive bias voltage (+2V). Surface scattering on the G2 side therefore becomes more important. The conductance is also more sensitive to the presence of the charged surface states (dangling bonds) on the G2 side of the QPC. Our NEGF model [89] of how the spin polarization is affected by impurities in the central portion of a QPC, in the presence of LSOC and bias asymmetry between the gates showed that 96

116 the number, location, and shape of the conductance anomalies occurring below the first quantized conductance plateau G 0, are strongly dependent on the nature (attractive or repulsive) and location of the impurities. Our experimental data therefore appear to support the presence of scattering from some localized states on the surface. The gradual transition of the anomalous plateau from 0.4 G 0 to 0.6 G 0 could be the signature of two impurity states at different energies on the G2 side of the QPC. Additional indirect evidence for the increased influence of surface scattering due to the positive potential on gate G2 is the fact that the normal conductance plateau is above the ballistic limit G 0. Since the number of localized states and their energies should be different on the other side of the QPC, we expect the number and location of the anomalous conductance plateaus to be quite different for the reverse asymmetry case: this is illustrated in Fig. 5.7(b) for the case of reverse asymmetry. In this case, two conductance anomalies appear over a very narrow range of ΔV G around 0.3 G 0 and 0.6 G 0. In this reverse bias case, electrons are pushed towards G1 because of the constant +2V bias held on this gate and also as a result of the increasing negative bias on G2. The fact that all the conductance curves are smooth near G 0 indicates that there is a lot of surface roughness scattering on the G1 side of the QPC. We offer the following qualitative explanation for the difference in the number and location of the anomalous conductance plateaus for the forward and reverse asymmetry biasing conditions. The application of an asymmetric bias can affect the charge state of dangling bonds because their energy levels are pushed up or down compared to the Fermi level, as illustrated in Fig This figure is a schematic of the conduction band energy profile between the two side gates, along a line though the middle of the QPC and perpendicular to the direction of current flow. The energy levels 1, 2, 3 are representative of dangling bonds on either side of the 97

117 channel. E f is the Fermi level in the source contact. Figures 5.10 (a) and (b) represent the two opposite polarities of an offset bias applied between the two gates. Figure 5.10 illustrates that the number of dangling bonds below or above the Fermi level will depend on the polarity of the offset, as well as being a function of the common sweep voltage, which raises and lowers the entire energy band diagram with respect to the Fermi level E f. Since the surface roughness and the number of dangling bonds is different on the two side walls, this leads to some level of intrinsic asymmetry in the structure, which is reflected in the conductance measurements. (ii) Analysis of conductance set 2: For the case of forward asymmetry depicted in Fig.5.8 (a), the conductance curve (the leftmost one in Fig. 5.8 (a)) corresponding to the case of zero-bias asymmetry, i.e., with V G1 = V G2 = V G, has no noticeable features. The zero-asymmetry curve again has a pinch-off voltage of about 6V and a conductance reaching G 0 for V G near 3V. Figure 5.8 (a) shows two welldefined conductance anomalies around 0.4 G 0 and 0.7 G 0. These appear over a limited range of ΔV G and disappear simultaneously for a sufficiently large common sweep voltage V G. As in Set 1, we associate the anomalies with the influence of surface and dangling bond scattering on the amount of spin polarization in the QPC. The well-defined anomalies seem to indicate a strong interaction with the surface of the etched channel on that side of the channel as the positive potential on G1 increases the overlap of the electron wavefunction with that side wall. For large enough asymmetry, the increase in electron density on this side of the channel appears to screen the effects of the impurities and the conductance anomalies disappear. For the reverse asymmetry case depicted in Fig.5.8 (b), there is only one conductance anomaly, around 0.6 G 0, at a different location than those observed in the forward asymmetry case. This is believed to be 98

118 once again related to the asymmetry of the surface and impurity on the two side walls, as schematically shown in Fig c. NEGF Simulations To support our qualitative discussion above, we performed NEGF simulations 3 of an InAs QPC in the presence of LSOC and dangling bonds on the side walls. We neglected the influence of surface roughness scattering for simplicity. The details of the NEGF are outlined in the ref. [26]. A schematic of the QPC used in the simulations in shown in Fig The effective mass in the InAs channel was set equal to m * = 0.023m 0, where m 0 is the free electron mass. All calculations were performed at a temperature T = 4.2 K. Following Lassl et al. [89], the strength * of the parameter γ in the interaction self-energy was set equal to m. The strength of the parameter β in the LSOC was set equal 5 Ǻ 2. The parameters γ and β are defined in the appendix. The QPC dimensions were selected as follows: w 2, l 2, w 1, l 1 = 16, 32, 48, and 64 nm, respectively. These parameters are smaller than the experimental values of the QPC shown in Fig.5.4 and were chosen to reduce computational time. The potential at the source was set equal to 0V and the one at the drain, V d, to 0.1 mv in all simulations. An asymmetry in the potential of the gates was introduced by taking V sg1 = -0.2 V + V sweep and V sg2 = 0.2 V + V sweep or the reverse polarity and the conductance of the constriction was studied as a function of the sweeping (or common mode) potential, V sweep. The Fermi energy was equal to mev in the source contact and 106 mev in the drain contact, ensuring single-mode transport through the QPC. 3 The NEGF codes were initially written by Junjun Wan [26]. 99

119 Fig. 5.11: Schematic of the QPC configuration used in the numerical simulations. The QPC parameters are w 2, l 2, w 1, l 1 = 16, 32, 48, and 64 nm, respectively. The two dark circles represent two dangling bonds located on the side walls of the narrow portion of the QPC. At the interface between the rectangular region of size w 2 l 2 and vacuum, the conduction band discontinuities at the bottom and the top interface were modeled, respectively, as E E y) 2 w 1 cos 1 w y d 2 c 2 c(, (5.7) and E E y) 2 w1 w 1 cos d 2 c 2 c ( y, (5.8) to achieve a smooth conductance band change, where d was selected equal to 1.6nm to represent a gradual variation of the conduction band profile from the inside of the quantum wire to the 100

120 vacuum region. A similar grading was also used along the walls going from the wider part of the channel to the central constriction of the QPC (Fig.5.11). This gradual change in E c (y) is responsible for the LSOC that triggers the spin polarization of the QPC in the presence of an asymmetry in V sg1 and V sg2. Δ E c in Eqns. (5.7) and (5.8) was set equal to 4.5 ev. We model the potential energy of a dangling bond located at location (x 1, y 1 ), in the 2DEG as follows, U impurity ( x, y) 4 0 r ( x x ) 1 q 2 2 ( y y ) 1 2 2, (5.9) where q 4 U 0 r 0, and U 0 is the maximum strength of the impurity potential. We use ε r = 15.15, the relative dielectric constant of InAs, and set U 0 equal to 200 mev. In Fig.5.11, the black circles represent the two dangling bonds considered in our simulations. The first dangling bond has coordinates (x 1,y 1 ) = ( +, - ), i.e., it is located 1/4 th of the way from the left side in the narrow portion of the QPC and in the middle of top side wall interface modeled with Eq.(5.7). The second dangling bond has coordinates (x 2, y 2 ) = (, + ), i.e., it is located in the middle of the narrow portion of the QPC on the bottom side wall interface modeled with Eq.(5.8). 101

121 Fig. 5.12: Total conductance G tot = G + G as a function of V sweep for a InAs QPC containing two dangling bonds at locations 1 and 2 in Fig The full curve corresponds to the case where an asymmetry in the QPC potential confinement is introduced by taking V sg1 = -0.2 V + V sweep and V sg2 = 0.2 V + V sweep. For this case, we also show the contributions from the up (G ) and down (G ) spins. The dashed curve for G tot corresponds to the case where an asymmetry in the QPC potential confinement is introduced by taking V sg1 = 0.2 V + V sweep and V sg2 = -0.2 V + V sweep. We calculated the conductance of a QPC with the parameters listed above and the spin conductance polarization α = [G - G ]/[G + G ], where G and G are the conductance due to the majority and minority spin bands, respectively. We studied how the conductance and the maximum of alpha are affected in the presence of dangling bonds when the polarity of the offset bias applied between the two gates is flipped. 102

122 Fig. 5.13: Spin conductance polarization α = [G - G ]/[G + G ] as a function of V sweep for a InAs QPC containing two dangling bonds at locations 1 and 2 in Fig α is positive and reaches a maximum of 0.97 for V sweep = 0.1V when an asymmetry in the QPC potential confinement was introduced using V sg1 = -0.2 V + V sweep and V sg2 = 0.2 V + V sweep. ; α is negative and reaches a maximum of for V sweep = 0.2 V when an asymmetry in the QPC potential confinement was introduced using V sg1 = 0.2 V + V sweep and V sg2 = -0.2 V + V sweep. Figure 5.12 shows a plot of the total conductance G tot = G + G versus V sweep for the case of two dangling bonds located at locations 1 and 2 in the narrow portion of the QPC. The full curve for G tot corresponds to the case where V sg1 = -0.2 V + V sweep and V sg2 = 0.2 V + V sweep. Also shown in Fig.5.12 are the individual contributions G and G which differ substantially for V sweep in the range from 0.02V to 0.1V. Figure 5.12 shows conductance anomalies around 0.3 G 0 and G 0 and also a shoulder in the plot around 0.75 G 0. The dashed curve in Fig.5.12 is a plot of G tot for the case of reverse asymmetry, i.e., with V sg1 = 0.2 V + V sweep and V sg2 = -0.2 V + V sweep. 103

123 The difference between the two curves for G tot is due to the asymmetry in the potential energy profile in the narrow portion of the QPC prior to the application of the different biases on the side gates. This is in qualitative agreement with our experimental results shown in Fig.5.9. The spin conductance polarization α for the two biasing cases V sg1 = 0.2 V + V sweep and V sg2 = 0.2 V + V sweep is shown in Fig When V sg1 = -0.2 V + V sweep and V sg2 = 0.2 V + V sweep, α reaches a maximum of for V sweep = 0.02V. For this value of V sweep, G tot = 0.28 G 0. When V sg1 = 0.2 V + V sweep and V sg2 =- 0.2 V + V sweep, α is negative because the role of the majority and minority spin bands are flipped compared to the previous case and, α reaches a minimum of for V sweep = 0.2 V. For this value of V sweep, G tot = 0.47 G 0. Additional simulations showed that the number and location of the conductance anomalies are very sensitive to the number and locations of the dangling bonds. Furthermore, the conductance curve versus V sweep are different for the two polarities of the bias asymmetry between the gates. Despite the presence of dangling bonds, α is quite large indicating a substantial amount of spin polarization in the QPC channel. 5.4 Conclusion We performed a systematic study of the appearance and evolution of anomalous conductance plateaus (G < 2e 2 /h), at T= 4.2K, in an InAs/ InAlAs quantum point contact. This was done in the presence of lateral spin-orbit coupling; as a function of the polarity of the offset bias between the gates. We showed that the number and locations of the anomalous plateaus depend strongly on the initial biases (positive or negative) applied to create the asymmetric 104

124 potential. Some of the anomalous conductance plateaus appear over a range of nearly 1 V of the sweep voltage common to the two gates. We interpret our conductance measurements as evidence of surface scattering (surface roughness and impurity (dangling bond) scattering) from the two side walls of the QPC (Fig.5.10). Our interpretation of the experimental results is supported by NEGF simulations of the conductance of a QPC in the presence of dangling bonds on its side walls. In this case, conductance anomalies were found at values different from 0.5 G o, yet with an associated maximum spin polarization as high as 98%. This is of practical importance since the spin polarization of two QPCs in series could be tuned for either spin up or spin down injection, opening the path for the realization of an allelectric spin valve. The resulting ON/OFF conductance ratio of that spin valve could be further controlled by the addition of side gates acting on the channel between the two QPCs. This spin valve could work at elevated temperatures by an appropriate choice of materials and by reducing the width of the channel to avoid spin coupling between subbands due to the LSOC. Since the ON/OFF conditions must be reproducible over a large number of spin valves in order to build spintronics circuits based on side-gated QPCs, it is important to define the in-plane gates using etching processes that produce very well defined steep side walls and low damage, such as SiCl 4 and CF 4 reactive ion etching [91-93]. 105

125 Chapter 6 Future Work 106

126 6.1 High Temperature Operation In this thesis, we explored the use of asymmetrically-biased side-gated InAs QPC devices for generation of spontaneous spin polarization. InAs is a material with strong intrinsic spinorbit coupling (SOC). We observed, at 4.2 K, several anomalous conductance plateaus below G 0 = 2e 2 /h, which are clear signatures of spin polarization. It was achieved through purely electrical means. For practical application, the operating temperature of the device needs to be extended to at least 77 K, and preferably beyond. In Ref. [21], P. Debray et al. argued that a strong SOC is not necessary to produce spin polarization in a side-gated QPC device. Even a weak SOC can cause spin imbalance in the channel. It is a strong electron-electron (e-e) interaction which is the key ingredient to spontaneous spin polarization. The NEGF simulations showed that once the initial spin imbalance is created, a strong e-e interaction enhances it and yields maximum spin polarization in the QPC channel [21]. This is an interesting outcome and opens up a new avenue of research, because materials like GaAs, which have low intrinsic SOC could probably be used to make the QPC devices to generate strongly spin-polarized current. InAs has a short spin coherence length, about a micron at 4.2 K [94]. This reduces to only tens of nanometers at ambient temperature. This makes InAs or any other semiconductor with large SOC unsuitable for making practical devices operational at ambient temperature. Contrary to that, GaAs has a long spin coherence length, tens of microns [95] at ambient temperature. It is also possible to grow GaAs samples with very low electron concentration to ensure a strong e-e interaction. GaAs is a mainstream material with a mature and well-established processing technology. It also has the added advantage of a large Schottky barrier, making it relatively easy to deposit surface gates. 107

127 Therefore, GaAs is a potential candidate for developing all-electric spin devices that can be operational at elevated temperatures. 6.2 Realization of All-Electric Spin-Valve This thesis has experimentally demonstrated that it is possible to generate strong spin polarization in a side-gated InAs QPC device when its lateral confining potential is made sufficiently asymmetric. Such a QPC can act as a spin-injector or a spin-detector. Two QPCs connected in series and separated by a channel of length smaller than the material spin coherence length, might be usable as an all-electric spin valve. We refer to such a device as a dual-qpc spin valve. SG SG SG QPC QPC SG SG SG Fig. 6.1: Scanning electron micrograph (SEM) of a dual-qpc device made from InAs/InAlAs QW. SGs are in-plane side gates. QPC1 and QPC2 will act as spin injector and spin-detector, respectively. 108