Image Processing on the extreme Processing Platform

Transcription

1 PACT Muich, Germay August 2002 Image Processig o the extreme Processig Platform Robert Strzodka Numerical Aalysis ad Scietific Computig Uiversity of Duisburg strzodka@math.ui-duisburg.de

2 Overview Itroductio Data-Flow & Architectures Implemetatios o the XPP Performace & Cofiguratios Coclusios

3 Some Key-Tasks i Image Processig Deoisig Segmetatio Matchig Visualizatio

4 Deoisig by aisotropic diffusio

5 Segmetatio by the level-set method

6 Matchig by a gradiet-flow method origial image deformed image matchig error matchig result

7 Visualizatio of a vector field Iitial image Step 1 Step 2 Step 3 Step 4 Step 5 Step 7 Step 10

8 Data-Flow i Oe Iteratio Step Step +1 F ( ) ) X β β α C W α, β α β : β α C X β 1

9 Data Processig-Badwidth total - badwidth b = { b, b, b b } total mi iput read write, output biput bread bwrite boutput memory ( X ) β β α C IN Processor F ( ) ) X β β α C +1 X α OUT memory Task : Maximize total - badwidth b total

10 Curret SD ad RD RAM-Types for MPUs 25, ,00 15,00 10,00 5,00 0, ,06 2,13 1,60 3,20 1 PC133 DDR266 PC800 2xPC800 MPU 2GHz Badwidth i GB/s Latecy (RAS cycle time) i 10s

11 Data Processig-Badwidth total - badwidth b = { b, b, b b } total mi iput read write, output biput bread bwrite boutput memory ( X ) β β α C IN Processor pipelie +1 X α OUT memory Tasks : 1. Keep the whole pipelie busy Task : Maximize total - badwidth b 2. Maximize total - badwidth b total total

12 Compariso XPP-FPGA XPP FPGA + fast recofigurability + low level optimizatio + implicit sychroizatio + higher level programmig + easier debuggig + large local memory with variable access + may IO chaels

13 Overview Itroductio Data-Flow & Architectures Implemetatios o the XPP Performace & Cofiguratios Coclusios

14 Implemetatios o the XPP Aim : Maximal total - badwidth, i.e.:oe iput ad output i each clock cycle fifo caches for eighbor pixels local computatio F ( ) ) X β β α C dual ported access to exram exram address geerator exram

15 Boudry Coditios costat boudry coditio atural boudry coditio

16 Data Travers If local memory is too small to cache all eighbour pixels, traverse the data i smaller subvolumes. Costs: multiple trasfer of border elemets.

17 Implemeted Filters i 2D ad 3D i a 8+4x8 XPP array X + 1 α = F ( ) ) X = β : β α C W α, β α β : β α C X β 2D Stecil 3D Stecil 3x3 3x3x3 5x5 7x7 5x5x5 i array 10+4x15

18 Performace operatios per clock cycle output pixel per clock cycle stecil 7x7 XPP 12x8 stecil 3x3x3 XPP 12x8 stecil 5x5x5 XPP 14x15 49 MAC 27 MAC 125 MAC 1 for 2^9 fifos 0.73 for 2^9 fifos 0.58 umber of passes at 100MHz 256^2 data ^3 data ^3 data real-time for 2d applicatios iteractivity for 3d applicatios

19 Cofiguratio for a explicit solver for each timestep { cofigure the array for weight computatio compute weights W α,γ = G γ for ( ) ) X β each β α C γ C cofigure the array for data computatio apply weights to data } X + 1 α = W α, β α β : β α C X β

20 Cofiguratio for a implicit solver for each timestep { cofigure the array for weight computatio compute weights W α,γ = G γ for ( ) ) X β each β α C γ C cofigure the array for data computatio for each iteratio k { apply weights to data } } X + 1, k + 1 α = W α, β α β : β α C X + 1, k β

21 Solvig the weight trasmissio problem 1. Istead of pre-computig 27 weightsw α, γ, γ 1 for a 3x3x3 stecil, pre-compute oly a smaller vector of itermediate resultsw r α from which all the weights ca be quickly evaluated W ( w r ). 2. Icrease the umber of available IO chaels by shiftig the task of address geeratio ad memory access to a processor outside of the XPP array, such that all the available 8 IO chaels ca be used for data iput or output. 3. Icrease the overall umber of IO chaels, such that applicatios will be able to access more tha 6 itermediate results simultaeously. α, γ α

22 Solvig the weight trasmissio problem Aim : Maximal total - badwidth, i.e.:oe iput ad output i each clock cycle fifo caches for eighbor pixels local computatio F ( X ) β β α C ( W ) α, γ γ C dual ported access to exram exram address geerator exram

23 Solvig the weight trasmissio problem Aim : Maximal total - badwidth, i.e.:oe iput ad output i each clock cycle fifo caches for eighbor pixels local computatio F r w ( X ) α β β α C address geerator dual ported access to exram Exteral RAM

24 Overview Itroductio Data-Flow & Architectures Implemetatios o the XPP Performace & Cofiguratios Coclusios

25 Coclusios A wide rage of image processig applicatio could be accelerated. The test implemetatios at estimated 100MHz suggest a performace gai of over commo PC solutios i full-grow applicatios. I our experiece the XPP wis over other architectures such as GPUs or FPGAs either i speed or programmability. Fially, improved memory availability ad IO access would further facilitate ad accelerate image processig o the XPP.