ENES 489p. Verification and Validation: Logic and Control Synthesis
|
|
- Lesley Powell
- 6 years ago
- Views:
Transcription
1 11/18/14 1 ENES 489p Verification and Validation: Logic and Control Synthesis Mumu Xu mumu@umd.edu November 18, 2014 Institute for Systems Research Aerospace Engineering University of Maryland, College Park
2 11/18/14 2 Table of Contents Verification and Validation Logic Synthesis Reactive Control Synthesis *Slides from EECI2013 Lecture, T. Wongpiromsarn, U. Topcu, R.M. Murray
3 11/18/14 3 Verification vs. validation Verification: "Are we building the product right" The software should conform to its specification Validation: "Are we building the right product" The software should do what the user really requires V & V must be applied at each stage in the software process Two principal objectives Discovery of defects in a system Assessment of whether the system is usable in an operational situation
4 11/18/14 4 Basic Concepts Planning for V&V needs to be begin in the early stages of requirements development Fundamental law of faults Failures: externally visible incorrect behavior of a system Error: incorrect internal state Fault: mistake in a system which causes one or more errors and failures FIND AND FIX THE CAUSE OF FAILURES
5 11/18/14 5 Validation and Verification Plans Two ways to detect and remove defects Consitency checking Simulation Diversity and Redundancy Design Requirement: Weight of the item shall be less than or equal to 134 pounds Verification Requirement: The item weight shall be determined by a scale, the calibration for which is correct, with an accuracy of plus or minus 6 ounces. The item shall be placed on the scale located on a level, stable surface and a reading taken. The measured weight shall be less than 134 pounds and 11 ounces.
6 11/18/14 6 Verification Traceability Matrices Design Requirement Verification Method Test Analysis Demo Exam Verification Requirement Req 1.1 X Level of Application Req 1.2 X Req 1.3 X
7 11/18/14 7 Model Checking Process Flow The process flow of model checking Efficient model checking tools automate the process: SPIN, nusmv, TLC,...
8 11/18/14 8 Temporal Logic Temporal refers to underlying nature of time Linear Branching Two key operators <> eventually property satisfied at some point in future [] always property satisfied now and forever in future Linear Temporal Logic (LTL) Introduced in 1970s (A. Pnueli) Large collection of tools for specification, design, analysis Other temporal logics CTL Computation Tree Logic TCTL Timed CTL MTL Metric Temporal Logic (timed LTL) TLA temporal logic of actions (Leslie Lamport) μ-calculus least fixed point operator (A. Prior, 1950s)
9 11/18/14 9 Linear Temporal Logic
10 11/18/14 10 Logic (closed system) Synthesis Closed system: behaviors are generated by the system and not affected by external influences Given: Transition system P LTL formula Compute: A path = of P such that P: composition of two traffic lights 1 ; s0,s0 {g 1 } 1 {g 2 } 2 s1,s0 s0,s s1,s1 {g 1,g 2 } = (g 1 g 2 ) g 1 g 2 Sample paths of P: P 1 = (hs 0 s 0 ihs 1 s 0 ihs 1 s 1 ihs 0 s 1 i)! 2 = (hs 0 s 0 ihs 0 s 1 i)! 3 = (hs 0 s 0 ihs 1 s 0 ihs 0 s 0 ihs 0 s 1 i)! 1 2
11 11/18/14 11 A Controls Interpretation P output y Controller C is a function C : M S! Act C 1 ; s0,s0 {g 1 } 1 {g 2 } 2 s1,s0 s0,s s1,s1 {g 1,g 2 } s0,s0 1 2 P C 2 s1,s0 s0,s1 = = (hs 0 s 0 ihs 1 s 0 ihs 0 s 0 ihs 0 s 1 i)! = (g 1 g 2 ) g 1 g 2 never(both lights green) [safety] Always eventually light 1 green [liveness] Always eventually light 2 green [liveness] 1 s0,s0 2
12 11/18/14 12 A Solution Approach Closed system synthesis: non-emptiness of satisfiability problem In synthesis, interesting behaviors are good In verification, interesting behaviors are bad Construct a verification model and claim that Trace(P ) \ Words( )=; Counterexample with negative result is a path that satisfies Positive results means path does not exist
13 11/18/14 13 Traffic Light System model: P = Specification: ; TS 1 s0: red 1 1 k ; TS 2 s0: red 2 2 s1: green s1: green {g 1 } {g 2 } = (g 1 g 2 ) g 1 g 2 L! (A) =Words( ) q0 (g 1 g 2 ) g 1 g 2 (g 1 g 2 ) g1 g2 (g 1 g 2 ) q1 q2 g 1 g 2 A SPIN code: System model (asynchronous composition): bool g1 = 0, g2 = 0; active proctype TL1() { do :: atomic{ g1 == 0 -> g1 = 1} :: atomic{ g1 == 1 -> g1 = 0 } od } active proctype TL2() { do :: atomic{ g2 == 0 -> g2 = 1} :: atomic{ g2 == 1 -> g2 = 0 } od } Automaton from LTL2BA: never { T0 init: if :: (!g1) (!g2) -> goto T0 init :: (g1 &&!g2) -> goto T1 S1 fi; T1 S1: if :: (!g1) (!g2) -> goto T1 S1 :: (!g1 && g2) -> goto accept S1 fi; accept S1: if :: (!g1) (!g2) -> goto T0 init :: (g1 &&!g2) -> goto T1 S1 fi;
14 11/18/14 14 Traffic Light System model: P = Specification: ; TS 1 s0: red 1 1 k ; TS 2 s0: red 2 2 s1: green s1: green {g 1 } {g 2 } = (g 1 g 2 ) g 1 g 2 L! (A) =Words( ) q0 (g 1 g 2 ) g 1 g 2 (g 1 g 2 ) g1 g2 (g 1 g 2 ) q1 q2 g 1 g 2 A SPIN code: System model (asynchronous composition): bool g1 = 0, g2 = 0; active proctype TL1() { do :: atomic{ g1 == 0 -> g1 = 1} :: atomic{ g1 == 1 -> g1 = 0 } od } active proctype TL2() { do :: atomic{ g2 == 0 -> g2 = 1} :: atomic{ g2 == 1 -> g2 = 0 } od } s0,s0 s1,s0 s0,s0 =(hs 0 s 0 ihs 1 s 0 ihs 0 s 0 ihs 0 s 1 ihs 0 s 0 ihs 0 s 1 i)! Automaton from LTL2BA: never { T0 init: s0,s1 if s0,s0 s0,s1 :: (!g1) (!g2) -> goto T0 init :: (g1 &&!g2) -> goto T1 S1 fi; T1 S1: if :: (!g1) (!g2) -> goto T1 S1 :: (!g1 && g2) -> goto accept S1 fi; accept S1: if :: (!g1) (!g2) -> goto T0 init :: (g1 &&!g2) -> goto T1 S1 fi;
15 11/18/14 15 Example: Frog Puzzle ( Move all yellow frogs to the right side of pond, and all brown frogs to left side of pond Frogs can only jump in direction they re facing Frogs can either jump one rock forward if the rock is empty or jump over a frog if the next rock has a frog on it and the rock after it is empty
16 11/18/14 16
17 11/18/14 17 Logic Synthesis: Frog Puzzle Rock i is not occupied or occupied ri {0, 1} State of frog i: s(f i ) {s 0,s 1...,s 6 } Transition system of frog i: Overall system model: P = F 1 F 2 F 6 r 0 r 2 r 3 r 4 r 5 r 6 r 1 F i s 0 s 1 s 2 s 3 s 4 s 5 s 6 F 1 r 1 s0 r 1 r 2 s1 r 2 s2 r 2 r 3 r 3 r 4 s3 r 4 s4 r 4 r 5 r 5 r 6 s5 r 6 s6 F 2 r 2 s1 s2 r 2 r 3 r 3 r 4 r 4 s3 s4 r 4 r 5 r 5 r 6 r 6 s5 s6 F 3 r 2 r 3 s2 r 3 r 4 s3 r 4 s4 r 4 r 5 r 5 r 6 s5 r 6 s6 = s(f 1 ),s(f 2 ),s(f 3 ) {s 4,s 5,s 6 } s(f 4 ),s(f 5 ),s(f 6 ) {s 0,s 1,s 2 } true q0 p q1 true A p, s(f 1 ),s(f 2 ),s(f 3 ) {s 4,s 5,s 6 } s(f 4 ),s(f 5 ),s(f 6 ) {s 0,s 1,s 2 }
18 11/18/14 18 Open System Synthesis y P y An open system is a system whose behaviors can be affected by external influence E x E x C CP y Open (synchronous) synthesis: Given a system that describes all the possible actions - plant actions y are controllable - environment actions x are uncontrollable a specification (x, y) find a strategy f(x) for the controllable actions which will maintain the specification against all possible adversary moves, i.e., 8x (x, f(x)) time E x 0 x 1 x 2 x 3 CP y 0 = f(x 0 ) y 1 = f(x 0 x 1 ) y 2 = f(x 0 x 1 x 2 ) y 3 = f(x 0 x 1 x 2 x 3 )
19 11/18/14 19 Reactive Control Synthesis Reactive systems are open systems that maintain an ongoing interaction with their environment rather than producing an output on termination. Consider the synthesis of a reactive system with input x and output y, specified by the linear temporal formula (x, y). The system contains 2 components S1 (i.e., environment ) and S2 (i.e., reactive module ) - Only S1 can modify x - Only S2 can modify y Want to show that S2 has a winning strategy for y against all possible x scenarios the environment may present to it. - Two-person game: treat environment as adversary S2 does its best, by manipulating y, to maintain (x, y) S1 does its best, by manipulating x, to falsify (x, y) If a winning strategy for S2 exists, we say that (x, y) is realizable x S1 S2 y
20 11/18/14 20 Runner-Blocker System R B Goal Runner R tries to reach Goal. Blocker B tries to intercept and stop R.
21 11/18/14 21 Runner-Blocker System lose lose win 7
22 11/18/14 22 Solving Reactive Control Synthesis Solution given as the winning set Winning set is set of states starting from which there exists a strategy for S 2 to satisfy the specification for all possible behaviors of S 1 A winning strategy can be constructed by saving intermediate values in winning set computation Worst case complexity is double exponential 1 st exponent: Specification to nondeterministic Buchi automaton 2 nd exponent: Covert NBA into deterministic Rabin automaton Similar to closed system synthesis: construct product of system and DRA Find set of states starting from which all possible runs in product automaton are accepting Lower Complexity Cases For specifications of form p, p, p, p controller can be synthesized in O(N 2 ), with N is size of the state space.
23 11/18/14 23 Game Structures: Runner Blocker s3 Game Structure G =(V, X, Y, e, s, e, s, AP,L,') X := {x}, X = {s 0,s 1,s 2,s 3,s 4 } Y := {y}, Y = {s 0,s 1,s 3,s 4 } e := (x = s 2 ) s0 R B s2 s4 s := (y = s 0 ) e := (x = s 2 ) =) (x 0 6= s 2 ) ^ (x 6= s 2 ) =) (x 0 = s 2 ) s := (y = s 0 _ y = s 4 ) =) (y 0 = s 1 _ y 0 = s 3 ) ^ (y = s 1 _ y = s 3 ) =) (y 0 = s 0 _ y 0 = s 4 ) ^ (y 0 6= x 0 ) s1 ' describes the winning condition, e.g., (y = s 4 )
24 11/18/14 24 Runner Blocker Example Runner Blocker q3 Play: An infinite sequence = s 0 s 1... of system (blocker + runner) states such that s0 is a valid initial state and (sj, sj+1) satisfies the transition relation of the blocker and the runner q0 R B q2 q4 Strategy: A function that gives the next runner state, given a finite number of previous system states of the current play, the current system state and the next blocker state Winning state: A state starting from which there exists a strategy for the runner to satisfy the winning condition for all the possible behaviors of the blocker q1 Winning game: For any valid initial blocker state sx, there exists a valid initial runner state sy such that (sx, sy) is a winning state Solving game: Identify the set of winning states
25 11/18/14 25 Solving Game Structures Solving Game Structures General solutions are hard Worst case complexity is double exponential (roughly in number of states) Special cases are easier For a specification of the form p, p, p or p, the controller can be synthesized in O(N 2 ) time where N is the size of the state space Another special case: GR(1) formulas ' =( p 1 ^...^ p m ) =) ( q 1 ^...^ q n ) {z } {z } ' e Thm (Piterman, Sa ar, Pneuli, 2007) A game structure G with a GR(1) winning condition can be solved by a symbolic algorithm in time proportional to nm V 3 ' s More useful form: Can show that this can be converted to GR(1) form
Lecture 4 Model Checking and Logic Synthesis
Lecture 4 Model Checking and Logic Synthesis Nok Wongpiromsarn Richard M. Murray Ufuk Topcu EECI, 18 March 2013 Outline Model checking: what it is, how it works, how it is used Computational complexity
More informationLecture 7 Synthesis of Reactive Control Protocols
Lecture 7 Synthesis of Reactive Control Protocols Richard M. Murray Nok Wongpiromsarn Ufuk Topcu California Institute of Technology AFRL, 25 April 2012 Outline Review: networked control systems and cooperative
More informationLecture 9 Synthesis of Reactive Control Protocols
Lecture 9 Synthesis of Reactive Control Protocols Nok Wongpiromsarn Singapore-MIT Alliance for Research and Technology Richard M. Murray and Ufuk Topcu California Institute of Technology EECI, 16 May 2012
More informationSynthesis of Designs from Property Specifications
Synthesis of Designs from Property Specifications Amir Pnueli New York University and Weizmann Institute of Sciences FMCAD 06 San Jose, November, 2006 Joint work with Nir Piterman, Yaniv Sa ar, Research
More informationRevisiting Synthesis of GR(1) Specifications
Revisiting Synthesis of GR(1) Specifications Uri Klein & Amir Pnueli Courant Institute of Mathematical Sciences, NYU Haifa Verification Conference, October 2010 What Is Synthesis? Rather than implement
More informationA Symbolic Approach to Safety LTL Synthesis
A Symbolic Approach to Safety LTL Synthesis Shufang Zhu 1 Lucas M. Tabajara 2 Jianwen Li Geguang Pu 1 Moshe Y. Vardi 2 1 East China Normal University 2 Rice Lucas M. Tabajara (Rice University) 2 University
More informationThe State Explosion Problem
The State Explosion Problem Martin Kot August 16, 2003 1 Introduction One from main approaches to checking correctness of a concurrent system are state space methods. They are suitable for automatic analysis
More informationLecture 2 Automata Theory
Lecture 2 Automata Theory Ufuk Topcu Nok Wongpiromsarn Richard M. Murray EECI, 18 March 2013 Outline Modeling (discrete) concurrent systems: transition systems, concurrency and interleaving Linear-time
More informationLecture 2 Automata Theory
Lecture 2 Automata Theory Ufuk Topcu Nok Wongpiromsarn Richard M. Murray Outline: Transition systems Linear-time properties Regular propereties EECI, 14 May 2012 This short-course is on this picture applied
More informationAlan Bundy. Automated Reasoning LTL Model Checking
Automated Reasoning LTL Model Checking Alan Bundy Lecture 9, page 1 Introduction So far we have looked at theorem proving Powerful, especially where good sets of rewrite rules or decision procedures have
More informationReactive Synthesis. Swen Jacobs VTSA 2013 Nancy, France u
Reactive Synthesis Nancy, France 24.09.2013 u www.iaik.tugraz.at 2 Property Synthesis (You Will Never Code Again) 3 Construct Correct Systems Automatically Don t do the same
More informationAbstractions and Decision Procedures for Effective Software Model Checking
Abstractions and Decision Procedures for Effective Software Model Checking Prof. Natasha Sharygina The University of Lugano, Carnegie Mellon University Microsoft Summer School, Moscow, July 2011 Lecture
More informationIntegrating Induction and Deduction for Verification and Synthesis
Integrating Induction and Deduction for Verification and Synthesis Sanjit A. Seshia Associate Professor EECS Department UC Berkeley DATE 2013 Tutorial March 18, 2013 Bob s Vision: Exploit Synergies between
More informationTimo Latvala. March 7, 2004
Reactive Systems: Safety, Liveness, and Fairness Timo Latvala March 7, 2004 Reactive Systems: Safety, Liveness, and Fairness 14-1 Safety Safety properties are a very useful subclass of specifications.
More informationLogic Model Checking
Logic Model Checking Lecture Notes 10:18 Caltech 101b.2 January-March 2004 Course Text: The Spin Model Checker: Primer and Reference Manual Addison-Wesley 2003, ISBN 0-321-22862-6, 608 pgs. the assignment
More informationA brief history of model checking. Ken McMillan Cadence Berkeley Labs
A brief history of model checking Ken McMillan Cadence Berkeley Labs mcmillan@cadence.com Outline Part I -- Introduction to model checking Automatic formal verification of finite-state systems Applications
More informationLinear-Time Logic. Hao Zheng
Linear-Time Logic Hao Zheng Department of Computer Science and Engineering University of South Florida Tampa, FL 33620 Email: zheng@cse.usf.edu Phone: (813)974-4757 Fax: (813)974-5456 Hao Zheng (CSE, USF)
More informationAn Algebra of Hybrid Systems
Peter Höfner University of Augsburg August 22, 2008 The University of Queensland, August 2008 1 c Peter Höfner Hybrid Systems Definition hybrid systems are heterogeneous systems characterised by the interaction
More informationPSL Model Checking and Run-time Verification via Testers
PSL Model Checking and Run-time Verification via Testers Formal Methods 2006 Aleksandr Zaks and Amir Pnueli New York University Introduction Motivation (Why PSL?) A new property specification language,
More informationCIS 842: Specification and Verification of Reactive Systems. Lecture Specifications: Specification Patterns
CIS 842: Specification and Verification of Reactive Systems Lecture Specifications: Specification Patterns Copyright 2001-2002, Matt Dwyer, John Hatcliff, Robby. The syllabus and all lectures for this
More informationSynthesis of Control Protocols for Autonomous Systems
Unmanned Systems, Vol. 0, No. 0 (2013) 1 19 c World Scientific Publishing Company Synthesis of Control Protocols for Autonomous Systems Tichakorn Wongpiromsarn a, Ufuk Topcu b, Richard M. Murray c a Ministry
More informationDynamic and Adversarial Reachavoid Symbolic Planning
Dynamic and Adversarial Reachavoid Symbolic Planning Laya Shamgah Advisor: Dr. Karimoddini July 21 st 2017 Thrust 1: Modeling, Analysis and Control of Large-scale Autonomous Vehicles (MACLAV) Sub-trust
More informationGames and Synthesis. Nir Piterman University of Leicester Telč, July-Autugst 2014
Games and Synthesis Nir Piterman University of Leicester Telč, July-Autugst 2014 Games and Synthesis, EATCS Young Researchers School, Telč, Summer 2014 Games and Synthesis, EATCS Young Researchers School,
More informationEfficient Model Checking of Safety Properties
Efficient Model Checking of Safety Properties Timo Latvala timo.latvala@hut.fi Laboratory for Theoretical Computer Science Helsinki University of Technology Finland Spin 2003 p.1/16 Introduction Safety
More informationSynthesis of Switching Protocols from Temporal Logic Specifications
Submitted, 2012 American Control Conference (ACC) http://www.cds.caltech.edu/~murray/papers DRAFT 1 Synthesis of Switching Protocols from Temporal Logic Specifications Jun Liu, Necmiye Ozay, Ufuk Topcu,
More informationSanjit A. Seshia EECS, UC Berkeley
EECS 219C: Computer-Aided Verification Explicit-State Model Checking: Additional Material Sanjit A. Seshia EECS, UC Berkeley Acknowledgments: G. Holzmann Checking if M satisfies : Steps 1. Compute Buchi
More informationIntroduction. Pedro Cabalar. Department of Computer Science University of Corunna, SPAIN 2013/2014
Introduction Pedro Cabalar Department of Computer Science University of Corunna, SPAIN cabalar@udc.es 2013/2014 P. Cabalar ( Department Introduction of Computer Science University of Corunna, SPAIN2013/2014
More informationLecture 8 Receding Horizon Temporal Logic Planning & Finite-State Abstraction
Lecture 8 Receding Horizon Temporal Logic Planning & Finite-State Abstraction Ufuk Topcu Nok Wongpiromsarn Richard M. Murray AFRL, 26 April 2012 Contents of the lecture: Intro: Incorporating continuous
More informationCDS 270 (Fall 09) - Lecture Notes for Assignment 8.
CDS 270 (Fall 09) - Lecture Notes for Assignment 8. ecause this part of the course has no slides or textbook, we will provide lecture supplements that include, hopefully, enough discussion to complete
More informationTesting with model checkers: A survey
COMPETENCE NETWORK SOFTNET AUSTRIA Testing with model checkers: A survey SNA-TR-2007-P2-04 Gordon Fraser, Franz Wotawa, Paul E. Ammann SNA TECHNICAL REPORT NOVEMBER 2007 Competence Network Softnet Austria,
More informationAutomata on Infinite words and LTL Model Checking
Automata on Infinite words and LTL Model Checking Rodica Condurache Lecture 4 Lecture 4 Automata on Infinite words and LTL Model Checking 1 / 35 Labeled Transition Systems Let AP be the (finite) set of
More informationTemporal Logic Model Checking
18 Feb, 2009 Thomas Wahl, Oxford University Temporal Logic Model Checking 1 Temporal Logic Model Checking Thomas Wahl Computing Laboratory, Oxford University 18 Feb, 2009 Thomas Wahl, Oxford University
More informationAnalysis of a Boost Converter Circuit Using Linear Hybrid Automata
Analysis of a Boost Converter Circuit Using Linear Hybrid Automata Ulrich Kühne LSV ENS de Cachan, 94235 Cachan Cedex, France, kuehne@lsv.ens-cachan.fr 1 Introduction Boost converter circuits are an important
More informationCS256/Winter 2009 Lecture #1. Zohar Manna. Instructor: Zohar Manna Office hours: by appointment
CS256/Winter 2009 Lecture #1 Zohar Manna FORMAL METHODS FOR REACTIVE SYSTEMS Instructor: Zohar Manna Email: manna@cs.stanford.edu Office hours: by appointment TA: Boyu Wang Email: wangboyu@stanford.edu
More informationComparison of LTL to Deterministic Rabin Automata Translators
Comparison of LTL to Deterministic Rabin Automata Translators František Blahoudek, Mojmír Křetínský, and Jan Strejček Faculty of Informatics, Masaryk University, Brno, Czech Republic {xblahoud, kretinsky,
More informationLTL Control in Uncertain Environments with Probabilistic Satisfaction Guarantees
LTL Control in Uncertain Environments with Probabilistic Satisfaction Guarantees Xu Chu (Dennis) Ding Stephen L. Smith Calin Belta Daniela Rus Department of Mechanical Engineering, Boston University, Boston,
More informationFailure Diagnosis of Discrete Event Systems With Linear-Time Temporal Logic Specifications
Failure Diagnosis of Discrete Event Systems With Linear-Time Temporal Logic Specifications Shengbing Jiang and Ratnesh Kumar Abstract The paper studies failure diagnosis of discrete event systems with
More informationFinite-State Model Checking
EECS 219C: Computer-Aided Verification Intro. to Model Checking: Models and Properties Sanjit A. Seshia EECS, UC Berkeley Finite-State Model Checking G(p X q) Temporal logic q p FSM Model Checker Yes,
More informationarxiv: v1 [cs.lo] 6 Mar 2012
Control of Probabilistic Systems under Dynamic, Partially Known Environments with Temporal Logic Specifications Tichakorn Wongpiromsarn and Emilio Frazzoli arxiv:203.77v [cs.lo] 6 Mar 202 Abstract We consider
More informationSynthesis weakness of standard approach. Rational Synthesis
1 Synthesis weakness of standard approach Rational Synthesis 3 Overview Introduction to formal verification Reactive systems Verification Synthesis Introduction to Formal Verification of Reactive Systems
More informationBridging the Gap between Reactive Synthesis and Supervisory Control
Bridging the Gap between Reactive Synthesis and Supervisory Control Stavros Tripakis University of California, Berkeley Joint work with Ruediger Ehlers (Berkeley, Cornell), Stéphane Lafortune (Michigan)
More informationSwitching Protocol Synthesis for Temporal Logic Specifications
Switching Protocol Synthesis for Temporal Logic Specifications Jun Liu, Necmiye Ozay, Ufuk Topcu, and Richard M. Murray Abstract We consider the problem of synthesizing a robust switching controller for
More informationEffective Synthesis of Asynchronous Systems from GR(1) Specifications
Effective Synthesis of Asynchronous Systems from GR(1) Specifications Courant Institute of Mathematical Sciences, NYU - Technical Report TR2011-944 (an extended version of a VMCAI 12 paper) Uri Klein 1,
More informationAutomata-Theoretic Model Checking of Reactive Systems
Automata-Theoretic Model Checking of Reactive Systems Radu Iosif Verimag/CNRS (Grenoble, France) Thanks to Tom Henzinger (IST, Austria), Barbara Jobstmann (CNRS, Grenoble) and Doron Peled (Bar-Ilan University,
More informationDecision Procedures for CTL
Decision Procedures for CTL Oliver Friedmann and Markus Latte Dept. of Computer Science, University of Munich, Germany Abstract. We give an overview over three serious attempts to devise an effective decision
More informationAutomata, Logic and Games: Theory and Application
Automata, Logic and Games: Theory and Application 1. Büchi Automata and S1S Luke Ong University of Oxford TACL Summer School University of Salerno, 14-19 June 2015 Luke Ong Büchi Automata & S1S 14-19 June
More informationIn recent years CTL and LTL logics have been used with considerable industrial success.
Modelchecking In recent years CTL and LTL logics have been used with considerable industrial success. For example microprocessors manufacturers (like Intel, Motorola) use programs which automatically can
More informationTopics in Formal Synthesis and Modeling
Topics in Formal Synthesis and Modeling by Uri Klein A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Computer Science Courant Institute
More informationInfinite Games. Sumit Nain. 28 January Slides Credit: Barbara Jobstmann (CNRS/Verimag) Department of Computer Science Rice University
Infinite Games Sumit Nain Department of Computer Science Rice University 28 January 2013 Slides Credit: Barbara Jobstmann (CNRS/Verimag) Motivation Abstract games are of fundamental importance in mathematics
More informationHelsinki University of Technology Laboratory for Theoretical Computer Science Research Reports 66
Helsinki University of Technology Laboratory for Theoretical Computer Science Research Reports 66 Teknillisen korkeakoulun tietojenkäsittelyteorian laboratorion tutkimusraportti 66 Espoo 2000 HUT-TCS-A66
More informationTemporal Logic. Stavros Tripakis University of California, Berkeley. We have designed a system. We want to check that it is correct.
EE 244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2016 Temporal logic Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley) EE 244, Fall 2016
More informationautomata-theoretic model checking
automata-theoretic model checking Kousha Etessami Bell Labs (starting next week, my affiliation will be U. of Edinburgh) overview The purpose of my lectures: to cover the fundamental algorithms used in
More informationComplexity of infinite tree languages
Complexity of infinite tree languages when automata meet topology Damian Niwiński University of Warsaw joint work with André Arnold, Szczepan Hummel, and Henryk Michalewski Liverpool, October 2010 1 Example
More informationImpartial Anticipation in Runtime-Verification
Impartial Anticipation in Runtime-Verification Wei Dong 1, Martin Leucker 2, and Christian Schallhart 2 1 School of Computer, National University of Defense Technology, P.R.China 2 Institut für Informatik,
More informationSemi-Automatic Distributed Synthesis
Semi-Automatic Distributed Synthesis Bernd Finkbeiner and Sven Schewe Universität des Saarlandes, 66123 Saarbrücken, Germany {finkbeiner schewe}@cs.uni-sb.de Abstract. We propose a sound and complete compositional
More informationSynthesis of Reactive Control Protocols for Differentially Flat Systems
DRAFT 1 Synthesis of Reactive Control Protocols for Differentially Flat Systems Jun Liu, Ufuk Topcu, Necmiye Ozay, and Richard M. Murray Abstract We propose a procedure for the synthesis of control protocols
More informationIntroduction to Temporal Logic. The purpose of temporal logics is to specify properties of dynamic systems. These can be either
Introduction to Temporal Logic The purpose of temporal logics is to specify properties of dynamic systems. These can be either Desired properites. Often liveness properties like In every infinite run action
More informationAutomatic Synthesis of Distributed Protocols
Automatic Synthesis of Distributed Protocols Rajeev Alur Stavros Tripakis 1 Introduction Protocols for coordination among concurrent processes are an essential component of modern multiprocessor and distributed
More information2. Elements of the Theory of Computation, Lewis and Papadimitrou,
Introduction Finite Automata DFA, regular languages Nondeterminism, NFA, subset construction Regular Epressions Synta, Semantics Relationship to regular languages Properties of regular languages Pumping
More informationRevising UNITY Programs: Possibilities and Limitations 1
Revising UNITY Programs: Possibilities and Limitations 1 Ali Ebnenasir, Sandeep S. Kulkarni, and Borzoo Bonakdarpour Software Engineering and Network Systems Laboratory Department of Computer Science and
More informationT Reactive Systems: Temporal Logic LTL
Tik-79.186 Reactive Systems 1 T-79.186 Reactive Systems: Temporal Logic LTL Spring 2005, Lecture 4 January 31, 2005 Tik-79.186 Reactive Systems 2 Temporal Logics Temporal logics are currently the most
More informationTechniques to solve computationally hard problems in automata theory
Techniques to solve computationally hard problems in automata theory Richard Mayr University of Edinburgh, UK IST Vienna, 4. Nov. 2014 Resources: www.languageinclusion.org Mayr (Edinburgh) Hard Problems
More informationComputer-Aided Program Design
Computer-Aided Program Design Spring 2015, Rice University Unit 3 Swarat Chaudhuri February 5, 2015 Temporal logic Propositional logic is a good language for describing properties of program states. However,
More informationFAIRNESS FOR INFINITE STATE SYSTEMS
FAIRNESS FOR INFINITE STATE SYSTEMS Heidy Khlaaf University College London 1 FORMAL VERIFICATION Formal verification is the process of establishing whether a system satisfies some requirements (properties),
More informationAlgorithmic Verification of Stability of Hybrid Systems
Algorithmic Verification of Stability of Hybrid Systems Pavithra Prabhakar Kansas State University University of Kansas February 24, 2017 1 Cyber-Physical Systems (CPS) Systems in which software "cyber"
More informationOptimal Control of Non-deterministic Systems for a Computationally Efficient Fragment of Temporal Logic
Submitted, 2013 Conference on Decison and Control (CDC) http://www.cds.caltech.edu/~murray/papers/wtm13-cdc.html Optimal Control of Non-deterministic Systems for a Computationally Efficient Fragment of
More informationModel Checking. Boris Feigin March 9, University College London
b.feigin@cs.ucl.ac.uk University College London March 9, 2005 Outline 1 2 Techniques Symbolic 3 Software 4 Vs. Deductive Verification Summary Further Reading In a nutshell... Model checking is a collection
More informationSynthesis of Reactive Switching Protocols from Temporal Logic Specifications
1 Synthesis of Reactive Switching Protocols from Temporal Logic Specifications Jun Liu, Necmiye Ozay, Ufuk Topcu, and Richard M. Murray Abstract We propose formal means for synthesizing switching protocols
More informationChapter 5: Linear Temporal Logic
Chapter 5: Linear Temporal Logic Prof. Ali Movaghar Verification of Reactive Systems Spring 94 Outline We introduce linear temporal logic (LTL), a logical formalism that is suited for specifying LT properties.
More informationModel Checking: An Introduction
Model Checking: An Introduction Meeting 3, CSCI 5535, Spring 2013 Announcements Homework 0 ( Preliminaries ) out, due Friday Saturday This Week Dive into research motivating CSCI 5535 Next Week Begin foundations
More informationSynthesis of Winning Strategies for Interaction under Partial Information
Synthesis of Winning Strategies for Interaction under Partial Information Oberseminar Informatik Bernd Puchala RWTH Aachen University June 10th, 2013 1 Introduction Interaction Strategy Synthesis 2 Main
More informationOnline Horizon Selection in Receding Horizon Temporal Logic Planning
Online Horizon Selection in Receding Horizon Temporal Logic Planning Vasumathi Raman 1 and Mattias Fält 2 and Tichakorn Wongpiromsarn 3 and Richard M. Murray 1 Abstract Temporal logics have proven effective
More informationLTL Model Checking. Wishnu Prasetya.
LTL Model Checking Wishnu Prasetya wishnu@cs.uu.nl www.cs.uu.nl/docs/vakken/pv Overview This pack : Abstract model of programs Temporal properties Verification (via model checking) algorithm Concurrency
More informationScenario Graphs and Attack Graphs
Scenario Graphs and Attack Graphs Oleg Mikhail Sheyner CMU-CS-04-122 April 14, 2004 School of Computer Science Computer Science Department Carnegie Mellon University Pittsburgh, PA Thesis Committee: Jeannette
More informationTemporal logics and explicit-state model checking. Pierre Wolper Université de Liège
Temporal logics and explicit-state model checking Pierre Wolper Université de Liège 1 Topics to be covered Introducing explicit-state model checking Finite automata on infinite words Temporal Logics and
More informationTimo Latvala. February 4, 2004
Reactive Systems: Temporal Logic LT L Timo Latvala February 4, 2004 Reactive Systems: Temporal Logic LT L 8-1 Temporal Logics Temporal logics are currently the most widely used specification formalism
More informationOverview. Discrete Event Systems Verification of Finite Automata. What can finite automata be used for? What can finite automata be used for?
Computer Engineering and Networks Overview Discrete Event Systems Verification of Finite Automata Lothar Thiele Introduction Binary Decision Diagrams Representation of Boolean Functions Comparing two circuits
More informationTowards Algorithmic Synthesis of Synchronization for Shared-Memory Concurrent Programs
Towards Algorithmic Synthesis of Synchronization for Shared-Memory Concurrent Programs Roopsha Samanta The University of Texas at Austin July 6, 2012 Roopsha Samanta Algorithmic Synthesis of Synchronization
More informationDouble Header. Model Checking. Model Checking. Overarching Plan. Take-Home Message. Spoiler Space. Topic: (Generic) Model Checking
Double Header Model Checking #1 Two Lectures Model Checking SoftwareModel Checking SLAM and BLAST Flying Boxes It is traditional to describe this stuff (especially SLAM and BLAST) with high-gloss animation
More informationAdmissible Strategies for Synthesizing Systems
Admissible Strategies for Synthesizing Systems Ocan Sankur Univ Rennes, Inria, CNRS, IRISA, Rennes Joint with Romain Brenguier (DiffBlue), Guillermo Pérez (Antwerp), and Jean-François Raskin (ULB) (Multiplayer)
More informationTemporal Logic. M φ. Outline. Why not standard logic? What is temporal logic? LTL CTL* CTL Fairness. Ralf Huuck. Kripke Structure
Outline Temporal Logic Ralf Huuck Why not standard logic? What is temporal logic? LTL CTL* CTL Fairness Model Checking Problem model, program? M φ satisfies, Implements, refines property, specification
More informationSemantic Equivalences and the. Verification of Infinite-State Systems 1 c 2004 Richard Mayr
Semantic Equivalences and the Verification of Infinite-State Systems Richard Mayr Department of Computer Science Albert-Ludwigs-University Freiburg Germany Verification of Infinite-State Systems 1 c 2004
More informationIntroduction to Model Checking. Debdeep Mukhopadhyay IIT Madras
Introduction to Model Checking Debdeep Mukhopadhyay IIT Madras How good can you fight bugs? Comprising of three parts Formal Verification techniques consist of three parts: 1. A framework for modeling
More informationLecture Notes on Emptiness Checking, LTL Büchi Automata
15-414: Bug Catching: Automated Program Verification Lecture Notes on Emptiness Checking, LTL Büchi Automata Matt Fredrikson André Platzer Carnegie Mellon University Lecture 18 1 Introduction We ve seen
More informationLinear Temporal Logic and Büchi Automata
Linear Temporal Logic and Büchi Automata Yih-Kuen Tsay Department of Information Management National Taiwan University FLOLAC 2009 Yih-Kuen Tsay (SVVRL @ IM.NTU) Linear Temporal Logic and Büchi Automata
More informationSynthesis of Correct-by-Construction Behavior Trees
Submitted, 2017 IEEE/RSJ International Conference on Intelligent Robots Systems (IROS) http://www.cds.caltech.edu/~murray/preprints/cmo17-iros_s.pdf Synthesis of Correct-by-Construction Behavior Trees
More informationSynthesis of Reactive(1) Designs
Synthesis of Reactive(1) Designs Nir Piterman 1, Amir Pnueli 2, and Yaniv Sa ar 3 1 EPFL - I&C - MTC, 1015, Lausanne, Switzerland. firstname.lastname@epfl.ch 2 Department of Computer Science, Weizmann
More informationModel Checking I. What are LTL and CTL? dack. and. dreq. and. q0bar
Model Checking I What are LTL and CTL? q0 or and dack dreq q0bar and 1 View circuit as a transition system (dreq, q0, dack) (dreq, q0, dack ) q0 = dreq and dack = dreq & (q0 + ( q0 & dack)) q0 or and D
More informationMODEL CHECKING. Arie Gurfinkel
1 MODEL CHECKING Arie Gurfinkel 2 Overview Kripke structures as models of computation CTL, LTL and property patterns CTL model-checking and counterexample generation State of the Art Model-Checkers 3 SW/HW
More informationReceding Horizon Temporal Logic Planning
1 Receding Horizon Temporal Logic Planning Tichaorn Wongpiromsarn, Ufu Topcu, and Richard M. Murray Abstract We present a methodology for automatic synthesis of embedded control software that incorporates
More informationLearning Regular ω-languages
Learning Regular ω-languages 1 2 Overview Motivation Background (ω-automata) 2014 Previous work on learning regular ω-languages Why is it difficult to extend L* [Angluin] to ω- languages? L* works due
More informationIC3 and Beyond: Incremental, Inductive Verification
IC3 and Beyond: Incremental, Inductive Verification Aaron R. Bradley ECEE, CU Boulder & Summit Middle School IC3 and Beyond: Incremental, Inductive Verification 1/62 Induction Foundation of verification
More informationComplexity Issues in Automated Addition of Time-Bounded Liveness Properties 1
Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Borzoo Bonakdarpour and Sandeep S. Kulkarni Software Engineering and Network Systems Laboratory, Department of Computer Science
More informationTHE objective of this paper is to synthesize switching. Synthesis of Reactive Switching Protocols from Temporal Logic Specifications
Synthesis of Reactive Switching Protocols from Temporal Logic Specifications Jun Liu, Member, IEEE, Necmiye Ozay, Member, IEEE, Ufuk Topcu, Member, IEEE, and Richard M Murray, Fellow, IEEE Abstract We
More informationRequirements Validation. Content. What the standards say (*) ?? Validation, Verification, Accreditation!! Correctness and completeness
Requirements Validation Requirements Management Requirements Validation?? Validation, Verification, Accreditation!! Check if evrything is OK With respect to what? Mesurement associated with requirements
More informationReceding Horizon Control for Temporal Logic Specifications
Receding Horizon Control for Temporal Logic Specifications Tichaorn Wongpiromsarn California Institute of Technology Pasadena, CA no@caltech.edu Ufu Topcu California Institute of Technology Pasadena, CA
More informationRegister machines L2 18
Register machines L2 18 Algorithms, informally L2 19 No precise definition of algorithm at the time Hilbert posed the Entscheidungsproblem, just examples. Common features of the examples: finite description
More informationLecture Notes on Inductive Definitions
Lecture Notes on Inductive Definitions 15-312: Foundations of Programming Languages Frank Pfenning Lecture 2 September 2, 2004 These supplementary notes review the notion of an inductive definition and
More informationAlternating nonzero automata
Alternating nonzero automata Application to the satisfiability of CTL [,, P >0, P =1 ] Hugo Gimbert, joint work with Paulin Fournier LaBRI, Université de Bordeaux ANR Stoch-MC 06/07/2017 Control and verification
More information3-Valued Abstraction-Refinement
3-Valued Abstraction-Refinement Sharon Shoham Academic College of Tel-Aviv Yaffo 1 Model Checking An efficient procedure that receives: A finite-state model describing a system A temporal logic formula
More information