In recent years CTL and LTL logics have been used with considerable industrial success.

Size: px
Start display at page:

Download "In recent years CTL and LTL logics have been used with considerable industrial success."

Transcription

1 Modelchecking In recent years CTL and LTL logics have been used with considerable industrial success. For example microprocessors manufacturers (like Intel, Motorola) use programs which automatically can check if some features are correctly implemented on a chip. These programs are called modelcheckers. 1

2 Informally a modelchecker is a program that takes a KTS describing a system, a temporal logical formula and returns either a counterexample if the formula is false in that KTS or true if the formula is satisfied in that KTS KTS model of a system Yes, formula true Modelchecker Temporal logical formula No, counterexample 2

3 We are now going to see the Spin modelchecker at work. You can find material on spin at there are tutorials, manuals, and the program itself which is free to download. Most applications of modelchecking are highly technical (hardware veryification, concurrent protocols verification etc..). We will consider a simple non technical problem just to give a flavour how modelchecking works 3

4 We are going to proceed as follows: We take a problem (the ferryman problem) for which we want a solution We describe all possible behaviours of the system with a transition system We express the solution in terms of a LTL formula We ask the system to verify that the solution is impossible The modelchecker will tell us that it is not true that the solution is impossible by providing a counterexample The counterexample will constitute the solution. 4

5 The problem A ferryman has to transport a piece of cabbage, a goat and a wolf across a river. On each journey he can carry at most one item. However he cannot leave unattended on the same side the cabbage and the goat or the goat and wolf (because the goat would eat the cabbage or the wolf would eat the goat). How can he do it? 5

6 The first few states of the transition system representing the system are as follows (the two river banks are denoted by 0 and 1): F=G=C=W=0 F=W=1 F=C=1 F=G=1 F=1 G=C=0 G=W=0 W=C=0 G=W=C=0 Notice that the only transition the doesn t violate the rules is the one where the ferryman transports the goat across the river. 6

7 The transition system representing the system is described by the following process: In the initial state C,G,W,F are on the same river bank Given a state s in the system if F and X (X is any of C,G,W) are on the same side then there is also the transition s s where s is the state like s except for F and X which are now on the opposite side. Given a state s in the system there is also the transition s s where s is the state like s except for F which is now on the opposite side 7

8 Let s now formulate the solution in terms of LTL: We want F,G,W,C to end up on the opposite river bank from which they started. That is we want F=G=W=C=1 to be true. This is the liveness condition. Moreover following the rules we do not want to go across states where G=W F or C=G F. This is the same as saying (G=W C=G) G=F And constitutes our safety condition 8

9 The solution is then a path in the transition system where there is a state which satisfy liveness and all previous states satisfy safety, i.e. we want the following formula to be true: ((G=W C=G) G=F) U (F=G=W=C=1) However if we ask the modelchecker to verify this formula we won t get anything interesting, just yes it is true, so what we will do is ask the modelchecker to verify the negation of the formula, 9

10 Now if the formula is true its negation will be false so the modelchecker will provide a counterexample, i.e. a trace in the transition system which is a counterexample to (((G=W C=G) G=F) U (F=G=W=C=1)) Such a trace will hence satisfy ((G=W C=G) G=F) U (F=G=W=C=1) i.e. it will be a sequence of states where at some point F=G=W=C=1 and beforehand (G=W C=G) G=F that is a solution to our initial problem. 10

11 the ferryman problem in Promela (the spin language for describing systems): bit ferryman=0,goat=0,cabbage=0,wolf=0 ; proctype Ferryman() { do ::(ferryman == goat) -> atomic{ferryman=1-goat; goat=1-goat} ::(ferryman == wolf) -> atomic{ferryman=1-wolf; wolf=1-wolf } ::(ferryman == cabbage) -> atomic{ferryman=1-cabbage; cabbage= :: ferryman=1-ferryman ::((ferryman==wolf)&&(wolf==cabbage)&&(cabbage==goat) &&(wolf==1)) -> goto accept all od; accept all: skip } init{ run Ferryman() } 11

12 The solution in spin [(run Ferryman())] ((ferryman==goat)) ferryman = (1-goat) goat = (1-goat) ferryman = (1-ferryman) ((ferryman==wolf)) ferryman = (1-wolf) wolf = (1-wolf) ((ferryman==goat)) ferryman = (1-goat) goat = (1-goat) ((ferryman==cabbage)) 12

13 ferryman = (1-cabbage) cabbage = (1-cabbage) ferryman = (1-ferryman) ((ferryman==goat)) ferryman = (1-goat) goat = (1-goat) ((ferryman==goat))

14 As you can see Promela, the language to describe the transition system for the spin modelchecker is somehow similar to Java; you can declare variables, Processes play a similar role to java classes constructors, the process init is similar to the java main method. An important Promela feature is the structure channel. Channels are used by processes to communicate with each other by sending and receiving messages. Basic informations about Promela and channels are available in the first few pages of the spin slides. 13

Lecture 4 Model Checking and Logic Synthesis

Lecture 4 Model Checking and Logic Synthesis Lecture 4 Model Checking and Logic Synthesis Nok Wongpiromsarn Richard M. Murray Ufuk Topcu EECI, 18 March 2013 Outline Model checking: what it is, how it works, how it is used Computational complexity

More information

Introduction to Model Checking. Debdeep Mukhopadhyay IIT Madras

Introduction to Model Checking. Debdeep Mukhopadhyay IIT Madras Introduction to Model Checking Debdeep Mukhopadhyay IIT Madras How good can you fight bugs? Comprising of three parts Formal Verification techniques consist of three parts: 1. A framework for modeling

More information

Logic Model Checking

Logic Model Checking Logic Model Checking Lecture Notes 10:18 Caltech 101b.2 January-March 2004 Course Text: The Spin Model Checker: Primer and Reference Manual Addison-Wesley 2003, ISBN 0-321-22862-6, 608 pgs. the assignment

More information

Model Checking. Boris Feigin March 9, University College London

Model Checking. Boris Feigin March 9, University College London b.feigin@cs.ucl.ac.uk University College London March 9, 2005 Outline 1 2 Techniques Symbolic 3 Software 4 Vs. Deductive Verification Summary Further Reading In a nutshell... Model checking is a collection

More information

SMV the Symbolic Model Verifier. Example: the alternating bit protocol. LTL Linear Time temporal Logic

SMV the Symbolic Model Verifier. Example: the alternating bit protocol. LTL Linear Time temporal Logic Model Checking (I) SMV the Symbolic Model Verifier Example: the alternating bit protocol LTL Linear Time temporal Logic CTL Fixed Points Correctness Slide 1 SMV - Symbolic Model Verifier SMV - Symbolic

More information

Probabilistic Model Checking Michaelmas Term Dr. Dave Parker. Department of Computer Science University of Oxford

Probabilistic Model Checking Michaelmas Term Dr. Dave Parker. Department of Computer Science University of Oxford Probabilistic Model Checking Michaelmas Term 2011 Dr. Dave Parker Department of Computer Science University of Oxford Overview Temporal logic Non-probabilistic temporal logic CTL Probabilistic temporal

More information

Alan Bundy. Automated Reasoning LTL Model Checking

Alan Bundy. Automated Reasoning LTL Model Checking Automated Reasoning LTL Model Checking Alan Bundy Lecture 9, page 1 Introduction So far we have looked at theorem proving Powerful, especially where good sets of rewrite rules or decision procedures have

More information

The State Explosion Problem

The State Explosion Problem The State Explosion Problem Martin Kot August 16, 2003 1 Introduction One from main approaches to checking correctness of a concurrent system are state space methods. They are suitable for automatic analysis

More information

Monitoring Distributed Controllers

Monitoring Distributed Controllers Monitoring Distributed Controllers When an Efficient LTL Algorithm on Sequences is Needed to Model-Check Traces A. Genon T. Massart C. Meuter Université Libre de Bruxelles Département d Informatique August

More information

LTL Model Checking. Wishnu Prasetya.

LTL Model Checking. Wishnu Prasetya. LTL Model Checking Wishnu Prasetya wishnu@cs.uu.nl www.cs.uu.nl/docs/vakken/pv Overview This pack : Abstract model of programs Temporal properties Verification (via model checking) algorithm Concurrency

More information

Semantic Equivalences and the. Verification of Infinite-State Systems 1 c 2004 Richard Mayr

Semantic Equivalences and the. Verification of Infinite-State Systems 1 c 2004 Richard Mayr Semantic Equivalences and the Verification of Infinite-State Systems Richard Mayr Department of Computer Science Albert-Ludwigs-University Freiburg Germany Verification of Infinite-State Systems 1 c 2004

More information

ENES 489p. Verification and Validation: Logic and Control Synthesis

ENES 489p. Verification and Validation: Logic and Control Synthesis 11/18/14 1 ENES 489p Verification and Validation: Logic and Control Synthesis Mumu Xu mumu@umd.edu November 18, 2014 Institute for Systems Research Aerospace Engineering University of Maryland, College

More information

Introduction. Pedro Cabalar. Department of Computer Science University of Corunna, SPAIN 2013/2014

Introduction. Pedro Cabalar. Department of Computer Science University of Corunna, SPAIN 2013/2014 Introduction Pedro Cabalar Department of Computer Science University of Corunna, SPAIN cabalar@udc.es 2013/2014 P. Cabalar ( Department Introduction of Computer Science University of Corunna, SPAIN2013/2014

More information

Helsinki University of Technology Laboratory for Theoretical Computer Science Research Reports 66

Helsinki University of Technology Laboratory for Theoretical Computer Science Research Reports 66 Helsinki University of Technology Laboratory for Theoretical Computer Science Research Reports 66 Teknillisen korkeakoulun tietojenkäsittelyteorian laboratorion tutkimusraportti 66 Espoo 2000 HUT-TCS-A66

More information

A Brief Introduction to Model Checking

A Brief Introduction to Model Checking A Brief Introduction to Model Checking Jan. 18, LIX Page 1 Model Checking A technique for verifying finite state concurrent systems; a benefit on this restriction: largely automatic; a problem to fight:

More information

Model Checking I. What are LTL and CTL? dack. and. dreq. and. q0bar

Model Checking I. What are LTL and CTL? dack. and. dreq. and. q0bar Model Checking I What are LTL and CTL? q0 or and dack dreq q0bar and 1 View circuit as a transition system (dreq, q0, dack) (dreq, q0, dack ) q0 = dreq and dack = dreq & (q0 + ( q0 & dack)) q0 or and D

More information

Where does it come from?

Where does it come from? 1 Course organization Textbook J.E. Hopcroft, R. Motwani, J.D. Ullman Introduction to Automata Theory, Languages, and Computation Second Edition, Addison-Wesley, New York, 2001 We shall cover Chapters

More information

Automatic Synthesis of Distributed Protocols

Automatic Synthesis of Distributed Protocols Automatic Synthesis of Distributed Protocols Rajeev Alur Stavros Tripakis 1 Introduction Protocols for coordination among concurrent processes are an essential component of modern multiprocessor and distributed

More information

On the Synergy of Probabilistic Causality Computation and Causality Checking

On the Synergy of Probabilistic Causality Computation and Causality Checking Technical Report soft-13-01, Chair for Software Engineering, University of Konstanz, Copyright by the Authors 2013 On the Synergy of Probabilistic Causality Computation and Causality Checking Florian Leitner-Fischer

More information

Linear Temporal Logic (LTL)

Linear Temporal Logic (LTL) Chapter 9 Linear Temporal Logic (LTL) This chapter introduces the Linear Temporal Logic (LTL) to reason about state properties of Labelled Transition Systems defined in the previous chapter. We will first

More information

Automatic Symmetry Detection for Model Checking Using Computational Group Theory

Automatic Symmetry Detection for Model Checking Using Computational Group Theory Automatic Symmetry Detection for Model Checking Using Computational Group Theory A.F. Donaldson and A. Miller Department of Computing Science University of Glasgow Glasgow, Scotland. {ally,alice}@dcs.gla.ac.uk

More information

Formal Verification of Mobile Network Protocols

Formal Verification of Mobile Network Protocols Dipartimento di Informatica, Università di Pisa, Italy milazzo@di.unipi.it Pisa April 26, 2005 Introduction Modelling Systems Specifications Examples Algorithms Introduction Design validation ensuring

More information

PRISM An overview. automatic verification of systems with stochastic behaviour e.g. due to unreliability, uncertainty, randomisation,

PRISM An overview. automatic verification of systems with stochastic behaviour e.g. due to unreliability, uncertainty, randomisation, PRISM An overview PRISM is a probabilistic model checker automatic verification of systems with stochastic behaviour e.g. due to unreliability, uncertainty, randomisation, Construction/analysis of probabilistic

More information

MODEL CHECKING. Arie Gurfinkel

MODEL CHECKING. Arie Gurfinkel 1 MODEL CHECKING Arie Gurfinkel 2 Overview Kripke structures as models of computation CTL, LTL and property patterns CTL model-checking and counterexample generation State of the Art Model-Checkers 3 SW/HW

More information

Abstractions and Decision Procedures for Effective Software Model Checking

Abstractions and Decision Procedures for Effective Software Model Checking Abstractions and Decision Procedures for Effective Software Model Checking Prof. Natasha Sharygina The University of Lugano, Carnegie Mellon University Microsoft Summer School, Moscow, July 2011 Lecture

More information

Timo Latvala. March 7, 2004

Timo Latvala. March 7, 2004 Reactive Systems: Safety, Liveness, and Fairness Timo Latvala March 7, 2004 Reactive Systems: Safety, Liveness, and Fairness 14-1 Safety Safety properties are a very useful subclass of specifications.

More information

Building a Computer Adder

Building a Computer Adder Logic Gates are used to translate Boolean logic into circuits. In the abstract it is clear that we can build AND gates that perform the AND function and OR gates that perform the OR function and so on.

More information

Double Header. Model Checking. Model Checking. Overarching Plan. Take-Home Message. Spoiler Space. Topic: (Generic) Model Checking

Double Header. Model Checking. Model Checking. Overarching Plan. Take-Home Message. Spoiler Space. Topic: (Generic) Model Checking Double Header Model Checking #1 Two Lectures Model Checking SoftwareModel Checking SLAM and BLAST Flying Boxes It is traditional to describe this stuff (especially SLAM and BLAST) with high-gloss animation

More information

Logic Programming. Prolog : 3

Logic Programming. Prolog : 3 Logic Programming Prolog : 3 Review We don't write normal functions in Prolog. Instead we relate the input and the output e.g. factorial: factorial(0, 1). factorial(n, V) : N > 0, N1 is N 1, factorial(n1,

More information

A brief history of model checking. Ken McMillan Cadence Berkeley Labs

A brief history of model checking. Ken McMillan Cadence Berkeley Labs A brief history of model checking Ken McMillan Cadence Berkeley Labs mcmillan@cadence.com Outline Part I -- Introduction to model checking Automatic formal verification of finite-state systems Applications

More information

State-Space Exploration. Stavros Tripakis University of California, Berkeley

State-Space Exploration. Stavros Tripakis University of California, Berkeley EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2014 State-Space Exploration Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley) EE

More information

Chap. 2 Finite Automata

Chap. 2 Finite Automata Chap. 2 Finite Automata 2.1 An Informal Picture of Finite Automata (See 2nd Edition) A man with a wolf, goat, and cabbage is on the left bank of a river A boat carries one man and only one of the other

More information

Integer Linear Programming Based Property Checking for Asynchronous Reactive Systems

Integer Linear Programming Based Property Checking for Asynchronous Reactive Systems IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 1 Integer Linear Programming Based Property Checking for Asynchronous Reactive Systems Stefan Leue Department of Computer and Information Science University of

More information

Chap. 2 Finite Automata

Chap. 2 Finite Automata Chap. 2 Finite Automata 2.1 An Informal Picture of Finite Automata (See 2nd Edition) A man with a wolf, goat, and cabbage is on the left bank of a river A boat carries one man and only one of the other

More information

Model Checking I. What are LTL and CTL? dack. and. dreq. and. q0bar

Model Checking I. What are LTL and CTL? dack. and. dreq. and. q0bar Model Checking I What are LTL and CTL? and dack q0 or D dreq D q0bar and 1 View circuit as a transition system (dreq, q0, dack) (dreq, q0, dack ) q0 = dreq dack = dreq and (q0 or (not q0 and dack)) q0

More information

Overview. Discrete Event Systems Verification of Finite Automata. What can finite automata be used for? What can finite automata be used for?

Overview. Discrete Event Systems Verification of Finite Automata. What can finite automata be used for? What can finite automata be used for? Computer Engineering and Networks Overview Discrete Event Systems Verification of Finite Automata Lothar Thiele Introduction Binary Decision Diagrams Representation of Boolean Functions Comparing two circuits

More information

Formal Verification of Systems-on-Chip

Formal Verification of Systems-on-Chip Formal Verification of Systems-on-Chip Wolfgang Kunz Department of Electrical & Computer Engineering University of Kaiserslautern, Germany Slide 1 Industrial Experiences Formal verification of Systems-on-Chip

More information

Temporal Logic. Stavros Tripakis University of California, Berkeley. We have designed a system. We want to check that it is correct.

Temporal Logic. Stavros Tripakis University of California, Berkeley. We have designed a system. We want to check that it is correct. EE 244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2016 Temporal logic Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley) EE 244, Fall 2016

More information

Chap. 2 Finite Automata

Chap. 2 Finite Automata Chap. 2 Finite Automata 2.1 An Informal Picture of Finite Automata A man with a wolf, goat, and cabbage is on the left bank of a river A boat carries one man and only one of the other three. The wolf eats

More information

Modeling Concurrent Systems

Modeling Concurrent Systems Modeling Concurrent Systems Wolfgang Schreiner Wolfgang.Schreiner@risc.uni-linz.ac.at Research Institute for Symbolic Computation (RISC) Johannes Kepler University, Linz, Austria http://www.risc.uni-linz.ac.at

More information

MA103 STATEMENTS, PROOF, LOGIC

MA103 STATEMENTS, PROOF, LOGIC MA103 STATEMENTS, PROOF, LOGIC Abstract Mathematics is about making precise mathematical statements and establishing, by proof or disproof, whether these statements are true or false. We start by looking

More information

The Expressivity of Universal Timed CCP: Undecidability of Monadic FLTL and Closure Operators for Security

The Expressivity of Universal Timed CCP: Undecidability of Monadic FLTL and Closure Operators for Security The Expressivity of Universal Timed CCP: Undecidability of Monadic FLTL and Closure Operators for Security Carlos Olarte and Frank D. Valencia INRIA /CNRS and LIX, Ecole Polytechnique Motivation Concurrent

More information

MATH 1090 Problem Set #3 Solutions March York University

MATH 1090 Problem Set #3 Solutions March York University York University Faculties of Science and Engineering, Arts, Atkinson MATH 1090. Problem Set #3 Solutions Section M 1. Use Resolution (possibly in combination with the Deduction Theorem, Implication as

More information

COEN6551: Formal Hardware Verification

COEN6551: Formal Hardware Verification COEN6551: Formal Hardware Verification Prof. Sofiène Tahar Hardware Verification Group Electrical and Computer Engineering Concordia University Montréal, Quebec CANADA Accident at Carbide plant, India

More information

FAIRNESS FOR INFINITE STATE SYSTEMS

FAIRNESS FOR INFINITE STATE SYSTEMS FAIRNESS FOR INFINITE STATE SYSTEMS Heidy Khlaaf University College London 1 FORMAL VERIFICATION Formal verification is the process of establishing whether a system satisfies some requirements (properties),

More information

CTL Model checking. 1. finite number of processes, each having a finite number of finite-valued variables. Model-Checking

CTL Model checking. 1. finite number of processes, each having a finite number of finite-valued variables. Model-Checking CTL Model checking Assumptions:. finite number of processes, each having a finite number of finite-valued variables.. finite length of CTL formula Problem:Determine whether formula f 0 is true in a finite

More information

Formal Verification of Systems-on-Chip Industrial Practices

Formal Verification of Systems-on-Chip Industrial Practices Formal Verification of Systems-on-Chip Industrial Practices Wolfgang Kunz Department of Electrical & Computer Engineering University of Kaiserslautern, Germany Slide 1 Industrial Experiences Formal verification

More information

Finite-State Model Checking

Finite-State Model Checking EECS 219C: Computer-Aided Verification Intro. to Model Checking: Models and Properties Sanjit A. Seshia EECS, UC Berkeley Finite-State Model Checking G(p X q) Temporal logic q p FSM Model Checker Yes,

More information

FORMAL METHODS LECTURE III: LINEAR TEMPORAL LOGIC

FORMAL METHODS LECTURE III: LINEAR TEMPORAL LOGIC Alessandro Artale (FM First Semester 2007/2008) p. 1/39 FORMAL METHODS LECTURE III: LINEAR TEMPORAL LOGIC Alessandro Artale Faculty of Computer Science Free University of Bolzano artale@inf.unibz.it http://www.inf.unibz.it/

More information

An Introduction to Proofs in Mathematics

An Introduction to Proofs in Mathematics An Introduction to Proofs in Mathematics The subject of mathematics is often regarded as a pinnacle in the achievement of human reasoning. The reason that mathematics is so highly regarded in the realm

More information

Model checking the basic modalities of CTL with Description Logic

Model checking the basic modalities of CTL with Description Logic Model checking the basic modalities of CTL with Description Logic Shoham Ben-David Richard Trefler Grant Weddell David R. Cheriton School of Computer Science University of Waterloo Abstract. Model checking

More information

Homework 2: Temporal logic

Homework 2: Temporal logic ICS-E5010 Computer-Aided Verification and Synthesis, Spring 2016 Stavros Tripakis Homework 2: Temporal logic Assigned: January 20, 2016 Due: February 1, 2016 Total: 235 points. 1. (20 points) Two formulae

More information

PSPACE-completeness of LTL/CTL model checking

PSPACE-completeness of LTL/CTL model checking PSPACE-completeness of LTL/CTL model checking Peter Lohmann April 10, 2007 Abstract This paper will give a proof for the PSPACE-completeness of LTLsatisfiability and for the PSPACE-completeness of the

More information

When working with probabilities we often perform more than one event in a sequence - this is called a compound probability.

When working with probabilities we often perform more than one event in a sequence - this is called a compound probability. + Independence + Compound Events When working with probabilities we often perform more than one event in a sequence - this is called a compound probability. Compound probabilities are more complex than

More information

1 Reducability. CSCC63 Worksheet Reducability. For your reference, A T M is defined to be the language { M, w M accepts w}. Theorem 5.

1 Reducability. CSCC63 Worksheet Reducability. For your reference, A T M is defined to be the language { M, w M accepts w}. Theorem 5. CSCC63 Worksheet Reducability For your reference, A T M is defined to be the language { M, w M accepts w}. 1 Reducability Theorem 5.1 HALT TM = { M, w M is a T M that halts on input w} is undecidable.

More information

Introduction to Embedded Systems

Introduction to Embedded Systems Introduction to Embedded Systems Sanjit A. Seshia UC Berkeley EECS 149/249A Fall 2015 2008-2015: E. A. Lee, A. L. Sangiovanni-Vincentelli, S. A. Seshia. All rights reserved. Chapter 13: Specification and

More information

Model Checking. Temporal Logic. Fifth International Symposium in Programming, volume. of concurrent systems in CESAR. In Proceedings of the

Model Checking. Temporal Logic. Fifth International Symposium in Programming, volume. of concurrent systems in CESAR. In Proceedings of the Sérgio Campos, Edmund Why? Advantages: No proofs Fast Counter-examples No problem with partial specifications can easily express many concurrency properties Main Disadvantage: State Explosion Problem Too

More information

Logic in Automatic Verification

Logic in Automatic Verification Logic in Automatic Verification Javier Esparza Sofware Reliability and Security Group Institute for Formal Methods in Computer Science University of Stuttgart Many thanks to Abdelwaheb Ayari, David Basin,

More information

Reasoning About Imperative Programs. COS 441 Slides 10b

Reasoning About Imperative Programs. COS 441 Slides 10b Reasoning About Imperative Programs COS 441 Slides 10b Last time Hoare Logic: { P } C { Q } Agenda If P is true in the initial state s. And C in state s evaluates to s. Then Q must be true in s. Program

More information

Symbolic Trajectory Evaluation (STE): Orna Grumberg Technion, Israel

Symbolic Trajectory Evaluation (STE): Orna Grumberg Technion, Israel Symbolic Trajectory Evaluation (STE): Automatic Refinement and Vacuity Detection Orna Grumberg Technion, Israel Marktoberdort 2007 1 Agenda Model checking Symbolic Trajectory Evaluation Basic Concepts

More information

Using Patterns and Composite Propositions to Automate the Generation of LTL Specifications

Using Patterns and Composite Propositions to Automate the Generation of LTL Specifications Using Patterns and Composite Propositions to Automate the Generation of LTL Specifications Salamah Salamah, Ann Q. Gates, Vladik Kreinovich, and Steve Roach Dept. of Computer Science, University of Texas

More information

Verification of a Dynamic Channel Model using the SPIN Model Checker

Verification of a Dynamic Channel Model using the SPIN Model Checker Verification of a Dynamic Channel Model using the SPIN Model Checker Rune Møllegaard FRIBORG a,1 and Brian VINTER b a escience Center, University of Copenhagen b Niels Bohr Institute, University of Copenhagen

More information

Automata and Formal Languages - CM0081 Determinist Finite Automata

Automata and Formal Languages - CM0081 Determinist Finite Automata Automata and Formal Languages - CM0081 Determinist Finite Automata Andrés Sicard-Ramírez Universidad EAFIT Semester 2018-2 Formal Languages: Origins Source areas [Greibach 1981, p. 14] Logic and recursive-function

More information

automata-theoretic model checking

automata-theoretic model checking automata-theoretic model checking Kousha Etessami Bell Labs (starting next week, my affiliation will be U. of Edinburgh) overview The purpose of my lectures: to cover the fundamental algorithms used in

More information

Model for reactive systems/software

Model for reactive systems/software Temporal Logics CS 5219 Abhik Roychoudhury National University of Singapore The big picture Software/ Sys. to be built (Dream) Properties to Satisfy (caution) Today s lecture System Model (Rough Idea)

More information

Predicate Abstraction: A Tutorial

Predicate Abstraction: A Tutorial Predicate Abstraction: A Tutorial Predicate Abstraction Daniel Kroening May 28 2012 Outline Introduction Existential Abstraction Predicate Abstraction for Software Counterexample-Guided Abstraction Refinement

More information

Deterministic Finite Automata

Deterministic Finite Automata Deterministic Finite Automata COMP2600 Formal Methods for Software Engineering Ranald Clouston Australian National University Semester 2, 2013 COMP 2600 Deterministic Finite Automata 1 Pop quiz What is

More information

Slides for Chapter 14: Time and Global States

Slides for Chapter 14: Time and Global States Slides for Chapter 14: Time and Global States From Coulouris, Dollimore, Kindberg and Blair Distributed Systems: Concepts and Design Edition 5, Addison-Wesley 2012 Overview of Chapter Introduction Clocks,

More information

Stochastic, Hybrid and Real-Time Systems: From Foundations To Applications with Modest

Stochastic, Hybrid and Real-Time Systems: From Foundations To Applications with Modest LCCC WORKSHOP 2013, LUND Stochastic, Hybrid and Real-Time Systems: From Foundations To Applications with Modest, Arnd Hartmanns Saarland University, Germany based on joint work with Jonathan Bogdoll, Henrik

More information

To every formula scheme there corresponds a property of R. This relationship helps one to understand the logic being studied.

To every formula scheme there corresponds a property of R. This relationship helps one to understand the logic being studied. Modal Logic (2) There appeared to be a correspondence between the validity of Φ Φ and the property that the accessibility relation R is reflexive. The connection between them is that both relied on the

More information

On the Synergy of Probabilistic Causality Computation and Causality Checking

On the Synergy of Probabilistic Causality Computation and Causality Checking On the Synergy of Probabilistic Causality Computation and Causality Checking Florian Leitner-Fischer and Stefan Leue University of Konstanz, Germany Abstract. In recent work on the safety analysis of systems

More information

CSCI3390-Lecture 6: An Undecidable Problem

CSCI3390-Lecture 6: An Undecidable Problem CSCI3390-Lecture 6: An Undecidable Problem September 21, 2018 1 Summary The language L T M recognized by the universal Turing machine is not decidable. Thus there is no algorithm that determines, yes or

More information

control in out in out Figure 1. Binary switch: (a) opened or off; (b) closed or on.

control in out in out Figure 1. Binary switch: (a) opened or off; (b) closed or on. Chapter 2 Digital Circuits Page 1 of 18 2. Digital Circuits Our world is an analog world. Measurements that we make of the physical objects around us are never in discrete units but rather in a continuous

More information

Model checking (III)

Model checking (III) Theory and Algorithms Model checking (III) Alternatives andextensions Rafael Ramirez rafael@iua.upf.es Trimester1, Oct2003 Slide 9.1 Logics for reactive systems The are many specification languages for

More information

Description Logics. Foundations of Propositional Logic. franconi. Enrico Franconi

Description Logics. Foundations of Propositional Logic.   franconi. Enrico Franconi (1/27) Description Logics Foundations of Propositional Logic Enrico Franconi franconi@cs.man.ac.uk http://www.cs.man.ac.uk/ franconi Department of Computer Science, University of Manchester (2/27) Knowledge

More information

Causality Checking for Complex System Models

Causality Checking for Complex System Models Technical Report soft-12-02, Revision 2, Chair for Software Engineering, University of Konstanz, Copyright by the Authors 2012 Causality Checking for Complex System Models Florian Leitner-Fischer and Stefan

More information

Chapter 4: Classical Propositional Semantics

Chapter 4: Classical Propositional Semantics Chapter 4: Classical Propositional Semantics Language : L {,,, }. Classical Semantics assumptions: TWO VALUES: there are only two logical values: truth (T) and false (F), and EXTENSIONALITY: the logical

More information

Logic and Truth Tables

Logic and Truth Tables Logic and Truth Tables What is a Truth Table? A truth table is a tool that helps you analyze statements or arguments in order to verify whether or not they are logical, or true. There are five basic operations

More information

EAHyper: Satisfiability, Implication, and Equivalence Checking of Hyperproperties

EAHyper: Satisfiability, Implication, and Equivalence Checking of Hyperproperties EAHyper: Satisfiability, Implication, and Equivalence Checking of Hyperproperties Bernd Finkbeiner, Christopher Hahn, and Marvin Stenger Saarland Informatics Campus, Saarland University, Saarbrücken, Germany

More information

Logic, Sets, and Proofs

Logic, Sets, and Proofs Logic, Sets, and Proofs David A. Cox and Catherine C. McGeoch Amherst College 1 Logic Logical Operators. A logical statement is a mathematical statement that can be assigned a value either true or false.

More information

Logic: Propositional Logic (Part I)

Logic: Propositional Logic (Part I) Logic: Propositional Logic (Part I) Alessandro Artale Free University of Bozen-Bolzano Faculty of Computer Science http://www.inf.unibz.it/ artale Descrete Mathematics and Logic BSc course Thanks to Prof.

More information

3-Valued Abstraction-Refinement

3-Valued Abstraction-Refinement 3-Valued Abstraction-Refinement Sharon Shoham Academic College of Tel-Aviv Yaffo 1 Model Checking An efficient procedure that receives: A finite-state model describing a system A temporal logic formula

More information

Introduction to Statistics

Introduction to Statistics MTH4106 Introduction to Statistics Notes 6 Spring 2013 Testing Hypotheses about a Proportion Example Pete s Pizza Palace offers a choice of three toppings. Pete has noticed that rather few customers ask

More information

A Symbolic Approach to Safety LTL Synthesis

A Symbolic Approach to Safety LTL Synthesis A Symbolic Approach to Safety LTL Synthesis Shufang Zhu 1 Lucas M. Tabajara 2 Jianwen Li Geguang Pu 1 Moshe Y. Vardi 2 1 East China Normal University 2 Rice Lucas M. Tabajara (Rice University) 2 University

More information

Algorithmic verification

Algorithmic verification Algorithmic verification Ahmed Rezine IDA, Linköpings Universitet Hösttermin 2018 Outline Overview Model checking Symbolic execution Outline Overview Model checking Symbolic execution Program verification

More information

1.10 Continuity Brian E. Veitch

1.10 Continuity Brian E. Veitch 1.10 Continuity Definition 1.5. A function is continuous at x = a if 1. f(a) exists 2. lim x a f(x) exists 3. lim x a f(x) = f(a) If any of these conditions fail, f is discontinuous. Note: From algebra

More information

ESE601: Hybrid Systems. Introduction to verification

ESE601: Hybrid Systems. Introduction to verification ESE601: Hybrid Systems Introduction to verification Spring 2006 Suggested reading material Papers (R14) - (R16) on the website. The book Model checking by Clarke, Grumberg and Peled. What is verification?

More information

Using Patterns and Composite Propositions to Automate the Generation of Complex LTL Specifications

Using Patterns and Composite Propositions to Automate the Generation of Complex LTL Specifications Using Patterns and Composite Propositions to Automate the Generation of Complex LTL Specifications Salamah Salamah, Ann Q. Gates, Vladik Kreinovich, and Steve Roach Dept. of Computer Science, University

More information

Lecture 16: Computation Tree Logic (CTL)

Lecture 16: Computation Tree Logic (CTL) Lecture 16: Computation Tree Logic (CTL) 1 Programme for the upcoming lectures Introducing CTL Basic Algorithms for CTL CTL and Fairness; computing strongly connected components Basic Decision Diagrams

More information

Intelligent Agents. Pınar Yolum Utrecht University

Intelligent Agents. Pınar Yolum Utrecht University Intelligent Agents Pınar Yolum p.yolum@uu.nl Utrecht University Logical Agents (Based mostly on the course slides from http://aima.cs.berkeley.edu/) Outline Knowledge-based agents Wumpus world Logic in

More information

1. Prove that the number cannot be represented as a 2 +3b 2 for any integers a and b. (Hint: Consider the remainder mod 3).

1. Prove that the number cannot be represented as a 2 +3b 2 for any integers a and b. (Hint: Consider the remainder mod 3). 1. Prove that the number 123456782 cannot be represented as a 2 +3b 2 for any integers a and b. (Hint: Consider the remainder mod 3). Solution: First, note that 123456782 2 mod 3. How did we find out?

More information

MODEL CHECKING FOR DYNAMIC ALLOCATION AND DEALLOCATION Extended Abstract

MODEL CHECKING FOR DYNAMIC ALLOCATION AND DEALLOCATION Extended Abstract MODEL CHECKING FOR DYNAMIC ALLOCATION AND DEALLOCATION Extended Abstract Dino Distefano, Arend Rensink, Joost-Pieter Katoen Department of Computer Science, University of Twente P.O. Box 217, 7500 AE Enschede,

More information

Some Remarks on Alternating Temporal Epistemic Logic

Some Remarks on Alternating Temporal Epistemic Logic Some Remarks on Alternating Temporal Epistemic Logic Corrected version: July 2003 Wojciech Jamroga Parlevink Group, University of Twente, Netherlands Institute of Mathematics, University of Gdansk, Poland

More information

Course Runtime Verification

Course Runtime Verification Course Martin Leucker (ISP) Volker Stolz (Høgskolen i Bergen, NO) INF5140 / V17 Chapters of the Course Chapter 1 Recall in More Depth Chapter 2 Specification Languages on Words Chapter 3 LTL on Finite

More information

Model Checking: An Introduction

Model Checking: An Introduction Model Checking: An Introduction Meeting 3, CSCI 5535, Spring 2013 Announcements Homework 0 ( Preliminaries ) out, due Friday Saturday This Week Dive into research motivating CSCI 5535 Next Week Begin foundations

More information

Computer-Aided Program Design

Computer-Aided Program Design Computer-Aided Program Design Spring 2015, Rice University Unit 3 Swarat Chaudhuri February 5, 2015 Temporal logic Propositional logic is a good language for describing properties of program states. However,

More information

Definition: Alternating time and space Game Semantics: State of machine determines who

Definition: Alternating time and space Game Semantics: State of machine determines who CMPSCI 601: Recall From Last Time Lecture 3 Definition: Alternating time and space Game Semantics: State of machine determines who controls, White wants it to accept, Black wants it to reject. White wins

More information

Testing with model checkers: A survey

Testing with model checkers: A survey COMPETENCE NETWORK SOFTNET AUSTRIA Testing with model checkers: A survey SNA-TR-2007-P2-04 Gordon Fraser, Franz Wotawa, Paul E. Ammann SNA TECHNICAL REPORT NOVEMBER 2007 Competence Network Softnet Austria,

More information

A review on quantum teleportation based on: Teleporting an unknown quantum state via dual classical and Einstein- Podolsky-Rosen channels

A review on quantum teleportation based on: Teleporting an unknown quantum state via dual classical and Einstein- Podolsky-Rosen channels JOURNAL OF CHEMISTRY 57 VOLUME NUMBER DECEMBER 8 005 A review on quantum teleportation based on: Teleporting an unknown quantum state via dual classical and Einstein- Podolsky-Rosen channels Miri Shlomi

More information

SFM-11:CONNECT Summer School, Bertinoro, June 2011

SFM-11:CONNECT Summer School, Bertinoro, June 2011 SFM-:CONNECT Summer School, Bertinoro, June 20 EU-FP7: CONNECT LSCITS/PSS VERIWARE Part 3 Markov decision processes Overview Lectures and 2: Introduction 2 Discrete-time Markov chains 3 Markov decision

More information