Monitoring Distributed Controllers

Size: px
Start display at page:

Download "Monitoring Distributed Controllers"

Transcription

1 Monitoring Distributed Controllers When an Efficient LTL Algorithm on Sequences is Needed to Model-Check Traces A. Genon T. Massart C. Meuter Université Libre de Bruxelles Département d Informatique August 25, 2006

2 Need for validation Need for validation Monitoring Centralized v.s. Distributed Systems Related Works Distributed control systems concurrent processes running on physically distributed hardware hard to design in nature critical systems (e.g. plant control system,...)

3 Need for validation Need for validation Monitoring Centralized v.s. Distributed Systems Related Works Distributed control systems concurrent processes running on physically distributed hardware hard to design in nature critical systems (e.g. plant control system,...) Validation techniques Model-Checking: exhaustive verification but: not (yet) scalable to real-sized systems Testing and Monitoring: non-exhaustive verification scalable for real-sized systems widely used in industry

4 Monitoring Need for validation Monitoring Centralized v.s. Distributed Systems Related Works The system distributed and asynchronous instrumented to emit relevant events (e.g. variable assignments, message transfer) an execution trace is collected

5 Monitoring Need for validation Monitoring Centralized v.s. Distributed Systems Related Works The system distributed and asynchronous instrumented to emit relevant events (e.g. variable assignments, message transfer) an execution trace is collected The monitor seperate process which collects those events checks whether a certain property holds can be done online or offline

6 Centralized v.s. Distributed Systems Need for validation Monitoring Centralized v.s. Distributed Systems Related Works Centralized System only one process events are totally ordered φ The OK e1 e2 e3 e4 Monitor KO

7 Centralized v.s. Distributed Systems Need for validation Monitoring Centralized v.s. Distributed Systems Related Works Centralized System only one process events are totally ordered φ The OK e1 e2 e3 e4 Monitor KO Distributed System multiple processes events are not totally ordered but a partial order can be obtained using vector clocks [Lam78, Mat89] P3 e2 e1 e3 e5 e6 e4 φ The Monitor OK KO

8 Related Works Need for validation Monitoring Centralized v.s. Distributed Systems Related Works Global predicate detection Several classes of predicate have been studied: Stable predicates [CL85] (once true, remains true) Disjunctive predicates (of the form lp 1 lp 2 lp n) Conjunctive predicates [GW94, GW96] (of the form lp 1 lp 2 lp n) Observer independent predicates [CDF95] (such that φ φ) Linear, semi-linear [CG98] or regular predicates (RCTL logic) [GM01, SG03]

9 Related Works Need for validation Monitoring Centralized v.s. Distributed Systems Related Works Global predicate detection Several classes of predicate have been studied: Stable predicates [CL85] (once true, remains true) Disjunctive predicates (of the form lp 1 lp 2 lp n) Conjunctive predicates [GW94, GW96] (of the form lp 1 lp 2 lp n) Observer independent predicates [CDF95] (such that φ φ) Linear, semi-linear [CG98] or regular predicates (RCTL logic) [GM01, SG03] Trace model checking Temporal logics for Mazurkiewicz traces: TrPTL [Thi94] TCL [APP95] LTrL [TW02] LTL over traces [DG02] = = our approach

10 Traces and Monitors Traces and Monitors The problem Complexity result Traces partially ordered set of events events are labelled with assignments finite number of events

11 Traces and Monitors Traces and Monitors The problem Complexity result Traces partially ordered set of events events are labelled with assignments finite number of events Monitor non-deterministic finite automaton with guards on transitions built from an LTL formula using tableau construction [VW86] loop transitions are ommitted and the monitor never blocks each guard is a boolean formula on one variable some states are marked as bad x > 0 init tmp w = 0 bad

12 The problem Traces and Monitors The problem Complexity result Question Does there exist an interleaving (i.e. total order) of events compatible with the partial order, leading the monitor to a bad state?

13 The problem Traces and Monitors The problem Complexity result Question Does there exist an interleaving (i.e. total order) of events compatible with the partial order, leading the monitor to a bad state? Example init x > 0 tmp w = 0 bad

14 The problem Traces and Monitors The problem Complexity result Question Does there exist an interleaving (i.e. total order) of events compatible with the partial order, leading the monitor to a bad state? Example init x > 0 tmp w = 0 bad

15 The problem Traces and Monitors The problem Complexity result Question Does there exist an interleaving (i.e. total order) of events compatible with the partial order, leading the monitor to a bad state? Example init x > 0 tmp w = 0 bad x:=0

16 The problem Traces and Monitors The problem Complexity result Question Does there exist an interleaving (i.e. total order) of events compatible with the partial order, leading the monitor to a bad state? Example init x > 0 tmp w = 0 bad x:=0;

17 The problem Traces and Monitors The problem Complexity result Question Does there exist an interleaving (i.e. total order) of events compatible with the partial order, leading the monitor to a bad state? Example init x > 0 tmp w = 0 bad x:=0; ; y:=3

18 The problem Traces and Monitors The problem Complexity result Question Does there exist an interleaving (i.e. total order) of events compatible with the partial order, leading the monitor to a bad state? Example init x > 0 tmp w = 0 bad x:=0; ; y:=3; x:=5

19 The problem Traces and Monitors The problem Complexity result Question Does there exist an interleaving (i.e. total order) of events compatible with the partial order, leading the monitor to a bad state? Example init x > 0 tmp w = 0 bad x:=0; ; y:=3; x:=5;

20 The problem Traces and Monitors The problem Complexity result A simple solution Compose the trace with the monitor to explore all possibilities: init x > 0 tmp w = 0 bad

21 The problem Traces and Monitors The problem Complexity result A simple solution Compose the trace with the monitor to explore all possibilities: init x > 0 tmp w = 0 bad ([0,0],init) x := 0 ([1,0],init) y:= 3 ([2,0],init) x:=5 ([3,0],tmp) ([0,1],init) x := 0 ([1,1],init) y:=3 ([2,1],init) x:=5 ([3,1],tmp) ([3,2],bad) ([2,2],init) x:=5 ([3,2],tmp)

22 The problem Traces and Monitors The problem Complexity result A simple solution Compose the trace with the monitor to explore all possibilities: x > 0 w = 0 Cut init tmp bad ([0,0],init) x := 0 ([1,0],init) y:= 3 ([2,0],init) x:=5 ([3,0],tmp) ([0,1],init) x := 0 ([1,1],init) y:=3 ([2,1],init) x:=5 ([3,1],tmp) ([1,1],init) Configuration = Cut + Monitor State ([2,2],init) x:=5 ([3,2],bad) ([3,2],tmp)

23 The problem Traces and Monitors The problem Complexity result A simple solution Compose the trace with the monitor to explore all possibilities: x > 0 w = 0 Cut init tmp bad ([0,0],init) x := 0 ([1,0],init) y:= 3 ([2,0],init) x:=5 ([3,0],tmp) ([0,1],init) x := 0 ([1,1],init) y:=3 ([2,1],init) x:=5 ([3,1],tmp) ([1,1],init) Configuration = Cut + Monitor State ([2,2],init) x:=5 ([3,2],bad) ([3,2],tmp) Problem: exponential number of interleavings/configurations! = Can we do better?

24 Complexity result Traces and Monitors The problem Complexity result Theorem The trace monitoring problem is NP-Complete

25 Complexity result Traces and Monitors The problem Complexity result Theorem The trace monitoring problem is NP-Complete NP-easyness Simple non-deterministic algorithm: guess an interleaving of the events in the trace check in polynomial time if it leads the monitor to a bad state

26 Complexity result Traces and Monitors The problem Complexity result Theorem The trace monitoring problem is NP-Complete NP-easyness Simple non-deterministic algorithm: guess an interleaving of the events in the trace check in polynomial time if it leads the monitor to a bad state NP-hardness Reduction from 3-SAT problem: use the monitor to encode the formula φ use the trace to encode all possible valuations a valuation satisfying φ iff the bad state is reachable

27 Sensitive events Sensitive events Observation The monitor is not always sensitive to all events:... x:=3... x < 6 m... z:=5... w < 5

28 Sensitive events Sensitive events Observation The monitor is not always sensitive to all events:... x:=3... x < 6 m... z:=5... w < 5

29 Sensitive events Sensitive events Observation The monitor is not always sensitive to all events:... x:=3... x < 6 m... z:=5... w < 5 Firing non-sensitive events has no effect on the monitor state

30 Sensitive events Sensitive events Observation The monitor is not always sensitive to all events:... x:=3... x < 6 m... z:=5... w < 5 Firing non-sensitive events has no effect on the monitor state Can we do something about it? Exploring all interleavings of non-sensitive events is not necessary = explore only one arbitrary interleaving But : those events might be interesting in another state of the monitor = keep them seperate during exploration

31 Sensitive events Idea 1 First all non-sensitive events are fired in an arbitrary order init x > 0 tmp w = 0 bad

32 Sensitive events Idea 1 First all non-sensitive events are fired in an arbitrary order init x > 0 tmp w = 0 bad

33 Sensitive events Idea 1 First all non-sensitive events are fired in an arbitrary order init x > 0 tmp w = 0 bad

34 Sensitive events Idea 1 First all non-sensitive events are fired in an arbitrary order 2 Both the origin cut and the final cut are kept init x > 0 tmp w = 0 bad [1,0] [2,2]

35 Sensitive events Idea 1 First all non-sensitive events are fired in an arbitrary order 2 Both the origin cut and the final cut are kept 3 Then, sensitive events are fired on all the cuts in between, in one step init x > 0 tmp w = 0 bad [1,0] [2,2]

36 Sensitive events Idea 1 First all non-sensitive events are fired in an arbitrary order 2 Both the origin cut and the final cut are kept 3 Then, sensitive events are fired on all the cuts in between, in one step init x > 0 tmp w = 0 bad [3,0] [3,2]

37 Sensitive events Idea 1 First all non-sensitive events are fired in an arbitrary order 2 Both the origin cut and the final cut are kept 3 Then, sensitive events are fired on all the cuts in between, in one step 4 Some previously non-sensitive events become sensitive = they must be explored! init x > 0 tmp w = 0 bad [3,0] [3,2]

38 Sensitive events Idea 1 First all non-sensitive events are fired in an arbitrary order 2 Both the origin cut and the final cut are kept 3 Then, sensitive events are fired on all the cuts in between, in one step 4 Some previously non-sensitive events become sensitive = they must be explored! init x > 0 tmp w = 0 bad [3,0] [3,2]

39 Sensitive events Idea 1 First all non-sensitive events are fired in an arbitrary order 2 Both the origin cut and the final cut are kept 3 Then, sensitive events are fired on all the cuts in between, in one step 4 Some previously non-sensitive events become sensitive = they must be explored! init x > 0 tmp w = 0 bad [3,2] [3,2]

40 (cont d) Sensitive events Symbolic Composition Symbolically compose the trace with the monitor to explore all possibilities: init x > 0 tmp w = 0 bad

41 (cont d) Sensitive events Symbolic Composition Symbolically compose the trace with the monitor to explore all possibilities: init x > 0 tmp w = 0 bad x := 0 x:=5 ([0,0],[0,1],init) ([1,0],[2,2],init) ([3,0],[3,2],init) ([1,0],[2,2],init)] ([3,1],[3,1],init) ([3,2],[3,2],bad)

42 (cont d) Sensitive events Symbolic Composition Symbolically compose the trace with the monitor to explore all possibilities: init x > 0 tmp w = 0 bad x := 0 x:=5 ([0,0],[0,1],init) ([1,0],[2,2],init) ([3,0],[3,2],init) ([1,0],[2,2],init)] ([3,1],[3,1],init) ([3,2],[3,2],bad) Symbolic Configuration = Origin Cut + Final Cut + Monitor State

43 (cont d) Sensitive events Symbolic Composition Symbolically compose the trace with the monitor to explore all possibilities: init x > 0 tmp w = 0 bad x := 0 x:=5 ([0,0],[0,1],init) ([1,0],[2,2],init) ([3,0],[3,2],init) ([1,0],[2,2],init)] ([3,1],[3,1],init) ([3,2],[3,2],bad) Symbolic Configuration = Origin Cut + Final Cut + Monitor State One symbolic configuration represents a set of configurations: ([1,0],[2,2],init) { ([1,0],init), ([1,1],init), ([1,2],init), ([2,2],init) }

44 (cont d) Sensitive events Symbolic Composition Symbolically compose the trace with the monitor to explore all possibilities: init x > 0 tmp w = 0 bad x := 0 x:=5 ([0,0],[0,1],init) ([1,0],[2,2],init) ([3,0],[3,2],init) ([1,0],[2,2],init)] ([3,1],[3,1],init) ([3,2],[3,2],bad) Symbolic Configuration = Origin Cut + Final Cut + Monitor State One symbolic configuration represents a set of configurations: ([1,0],[2,2],init) { ([1,0],init), ([1,1],init), ([1,2],init), ([2,2],init) } Symbolic composition is both sound and complete!

45 In practice In practice Does it work? Algorithm input : T = (E, λ, ), M = (M, m 0, B, m) output: reachable s(,, m 0 ) B begin T, W {(,, m 0 )} while W do let (t, w, m) W W W \ {(t, w, m)} T T (t, w, m) repeat x w w w {e enabled(w) e sensitive(m)} until (w = x) if (w = E) (m B) then return false return true end forall (t, w, m ) : (t, w, m) e s (t, w, m ) (t, w, m ) T do W W {(t, w, m )}

46 In practice In practice Does it work? Algorithm input : T = (E, λ, ), M = (M, m 0, B, m) output: reachable s(,, m 0 ) B begin { } T, W {(,, m 0 )} while let (t, W w, m) do W let (t, w, m) W WW W \{(t, {(t, w, w, m)} m)} T T T (t, w, w, m) m) repeat x w w w {e enabled(w) e sensitive(m)} until (w = x) if (w = E) (m B) then return false return true end 1 pick a symbolic configuration forall (t, w, m ) : (t, w, m) e s (t, w, m ) (t, w, m ) T do W W {(t, w, m )}

47 In practice In practice Does it work? Algorithm input : T = (E, λ, ), M = (M, m 0, B, m) output: reachable s(,, m 0 ) B begin T, W {(,, m 0 )} while W do let (t, w, m) W W W \ {(t, w, m)} T T (t, w, m) repeat repeat xx w w w {e enabled(w) e sensitive(m)} until x) until (w = x) if (w = E) (m B) then return false return true end w w {e enabled(w) e sensitive(m)} 1 pick a symbolic configuration 2 extend it with non-sensitive events forall (t, w, m ) : (t, w, m) e s (t, w, m ) (t, w, m ) T do W W {(t, w, m )}

48 In practice In practice Does it work? Algorithm input : T = (E, λ, ), M = (M, m 0, B, m) output: reachable s(,, m 0 ) B begin T, W {(,, m 0 )} while W do let (t, w, m) W W W \ {(t, w, m)} T T (t, w, m) repeat x w w w {e enabled(w) e sensitive(m)} until (w = x) if if (w (w = E) (m (m B) B) then then return false return true end return false 1 pick a symbolic configuration 2 extend it with non-sensitive events 3 check if a bad state is reached forall (t, w, m ) : (t, w, m) e s (t, w, m ) (t, w, m ) T do W W {(t, w, m )}

49 In practice In practice Does it work? Algorithm input : T = (E, λ, ), M = (M, m 0, B, m) output: reachable s(,, m 0 ) B begin T, W {(,, m 0 )} while W do let (t, w, m) W W W \ {(t, w, m)} T T (t, w, m) repeat x w w w {e enabled(w) e sensitive(m)} until (w = x) if (w = E) (m B) then return false forall (t, w,, m ) :)(t, : w, (t, m) w, e m) s (t e, w, m ) (t, w, m s (t, w, m ) )(t T, w do, m ) T do {(t, w, m )} W W {(t, w, m )} return true end 1 pick a symbolic configuration 2 extend it with non-sensitive events 3 check if a bad state is reached 4 fire symbolically sensitive events

50 Does it work? In practice Does it work? Early results Experiment Explicit Symbolic Spin Model Processes Events Property Error Time Conf. Error Time Conf. Time Peterson Mutex NO 1.39s NO 0.35s s Mutex NO 16.88s NO 3.45s s Mutex NO 34.75s s Peterson Mutex YES 1.11s YES 0.01s s Faulty Mutex YES 15.95s YES 0.05s s Mutex YES 0.53s s ABProtocol Received NO 2.17s NO 0.42s s Received NO 31.08s NO 4.25s s Received NO 43.09s s ABProtocol Received YES 2.06s YES 0.01s s Faulty Received YES 29.70s YES 0.06s s Received YES 0.53s s Philosopher Fork NO 1.03s 6190 NO 0.05s s Fork NO 87.02s NO 0.21s s Fork NO 1.52s Philosopher Fork YES 0.09s 1187 YES 0.01s s Faulty Fork YES 78.72s YES 0.01s s Fork YES 0.01s 55 - Table 1. s ( - means that the execution ran out of memory)

51 What has been achieved? we proposed a symbolic method to monitor distributed systems has been implemented and works well in practice a tool, TraX (Trace explorer) is available:

52 What has been achieved? we proposed a symbolic method to monitor distributed systems has been implemented and works well in practice a tool, TraX (Trace explorer) is available: Future Work integrate the method into our distributed controler development environment dsl [DGMM05] apply the method to similar models, such as MSC extend the method to do model-checking, using McMillan s unfoldings

Monitoring Distributed Controllers: When an Efficient LTL Algorithm on Sequences is Needed to Model-Check Traces

Monitoring Distributed Controllers: When an Efficient LTL Algorithm on Sequences is Needed to Model-Check Traces Monitoring Distributed Controllers: When an Efficient LTL Algorithm on Sequences is Needed to Model-Check Traces Alexandre Genon, Thierry Massart, and Cédric Meuter Université Libre de Bruxelles Abstract.

More information

Efficient online monitoring of Ltl properties for asynchronous distributed systems

Efficient online monitoring of Ltl properties for asynchronous distributed systems Efficient online monitoring of Ltl properties for asynchronous distributed systems Thierry Massart and Cédric Meuter Université Libre de Bruxelles Abstract. We define an efficient online method to monitor

More information

Formal Verification Techniques. Riccardo Sisto, Politecnico di Torino

Formal Verification Techniques. Riccardo Sisto, Politecnico di Torino Formal Verification Techniques Riccardo Sisto, Politecnico di Torino State exploration State Exploration and Theorem Proving Exhaustive exploration => result is certain (correctness or noncorrectness proof)

More information

Sanjit A. Seshia EECS, UC Berkeley

Sanjit A. Seshia EECS, UC Berkeley EECS 219C: Computer-Aided Verification Explicit-State Model Checking: Additional Material Sanjit A. Seshia EECS, UC Berkeley Acknowledgments: G. Holzmann Checking if M satisfies : Steps 1. Compute Buchi

More information

Abstractions and Decision Procedures for Effective Software Model Checking

Abstractions and Decision Procedures for Effective Software Model Checking Abstractions and Decision Procedures for Effective Software Model Checking Prof. Natasha Sharygina The University of Lugano, Carnegie Mellon University Microsoft Summer School, Moscow, July 2011 Lecture

More information

Double Header. Model Checking. Model Checking. Overarching Plan. Take-Home Message. Spoiler Space. Topic: (Generic) Model Checking

Double Header. Model Checking. Model Checking. Overarching Plan. Take-Home Message. Spoiler Space. Topic: (Generic) Model Checking Double Header Model Checking #1 Two Lectures Model Checking SoftwareModel Checking SLAM and BLAST Flying Boxes It is traditional to describe this stuff (especially SLAM and BLAST) with high-gloss animation

More information

Automata-Theoretic Model Checking of Reactive Systems

Automata-Theoretic Model Checking of Reactive Systems Automata-Theoretic Model Checking of Reactive Systems Radu Iosif Verimag/CNRS (Grenoble, France) Thanks to Tom Henzinger (IST, Austria), Barbara Jobstmann (CNRS, Grenoble) and Doron Peled (Bar-Ilan University,

More information

Model Checking: An Introduction

Model Checking: An Introduction Model Checking: An Introduction Meeting 3, CSCI 5535, Spring 2013 Announcements Homework 0 ( Preliminaries ) out, due Friday Saturday This Week Dive into research motivating CSCI 5535 Next Week Begin foundations

More information

Linear-time Temporal Logic

Linear-time Temporal Logic Linear-time Temporal Logic Pedro Cabalar Department of Computer Science University of Corunna, SPAIN cabalar@udc.es 2015/2016 P. Cabalar ( Department Linear oftemporal Computer Logic Science University

More information

Models for Efficient Timed Verification

Models for Efficient Timed Verification Models for Efficient Timed Verification François Laroussinie LSV / ENS de Cachan CNRS UMR 8643 Monterey Workshop - Composition of embedded systems Model checking System Properties Formalizing step? ϕ Model

More information

Modal and Temporal Logics

Modal and Temporal Logics Modal and Temporal Logics Colin Stirling School of Informatics University of Edinburgh July 23, 2003 Why modal and temporal logics? 1 Computational System Modal and temporal logics Operational semantics

More information

Chapter 2. Reductions and NP. 2.1 Reductions Continued The Satisfiability Problem (SAT) SAT 3SAT. CS 573: Algorithms, Fall 2013 August 29, 2013

Chapter 2. Reductions and NP. 2.1 Reductions Continued The Satisfiability Problem (SAT) SAT 3SAT. CS 573: Algorithms, Fall 2013 August 29, 2013 Chapter 2 Reductions and NP CS 573: Algorithms, Fall 2013 August 29, 2013 2.1 Reductions Continued 2.1.1 The Satisfiability Problem SAT 2.1.1.1 Propositional Formulas Definition 2.1.1. Consider a set of

More information

Chapter 4: Computation tree logic

Chapter 4: Computation tree logic INFOF412 Formal verification of computer systems Chapter 4: Computation tree logic Mickael Randour Formal Methods and Verification group Computer Science Department, ULB March 2017 1 CTL: a specification

More information

Bounded Model Checking with SAT/SMT. Edmund M. Clarke School of Computer Science Carnegie Mellon University 1/39

Bounded Model Checking with SAT/SMT. Edmund M. Clarke School of Computer Science Carnegie Mellon University 1/39 Bounded Model Checking with SAT/SMT Edmund M. Clarke School of Computer Science Carnegie Mellon University 1/39 Recap: Symbolic Model Checking with BDDs Method used by most industrial strength model checkers:

More information

Linear Temporal Logic and Büchi Automata

Linear Temporal Logic and Büchi Automata Linear Temporal Logic and Büchi Automata Yih-Kuen Tsay Department of Information Management National Taiwan University FLOLAC 2009 Yih-Kuen Tsay (SVVRL @ IM.NTU) Linear Temporal Logic and Büchi Automata

More information

State-Space Exploration. Stavros Tripakis University of California, Berkeley

State-Space Exploration. Stavros Tripakis University of California, Berkeley EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2014 State-Space Exploration Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley) EE

More information

Finite-State Model Checking

Finite-State Model Checking EECS 219C: Computer-Aided Verification Intro. to Model Checking: Models and Properties Sanjit A. Seshia EECS, UC Berkeley Finite-State Model Checking G(p X q) Temporal logic q p FSM Model Checker Yes,

More information

The algorithmic analysis of hybrid system

The algorithmic analysis of hybrid system The algorithmic analysis of hybrid system Authors: R.Alur, C. Courcoubetis etc. Course teacher: Prof. Ugo Buy Xin Li, Huiyong Xiao Nov. 13, 2002 Summary What s a hybrid system? Definition of Hybrid Automaton

More information

Propositional Logic: Models and Proofs

Propositional Logic: Models and Proofs Propositional Logic: Models and Proofs C. R. Ramakrishnan CSE 505 1 Syntax 2 Model Theory 3 Proof Theory and Resolution Compiled at 11:51 on 2016/11/02 Computing with Logic Propositional Logic CSE 505

More information

Formal Verification of Mobile Network Protocols

Formal Verification of Mobile Network Protocols Dipartimento di Informatica, Università di Pisa, Italy milazzo@di.unipi.it Pisa April 26, 2005 Introduction Modelling Systems Specifications Examples Algorithms Introduction Design validation ensuring

More information

The State Explosion Problem

The State Explosion Problem The State Explosion Problem Martin Kot August 16, 2003 1 Introduction One from main approaches to checking correctness of a concurrent system are state space methods. They are suitable for automatic analysis

More information

EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization

EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Discrete Systems Lecture: State-Space Exploration Stavros Tripakis University of California, Berkeley Stavros Tripakis:

More information

Computer-Aided Program Design

Computer-Aided Program Design Computer-Aided Program Design Spring 2015, Rice University Unit 3 Swarat Chaudhuri February 5, 2015 Temporal logic Propositional logic is a good language for describing properties of program states. However,

More information

Embedded Systems 2. REVIEW: Actor models. A system is a function that accepts an input signal and yields an output signal.

Embedded Systems 2. REVIEW: Actor models. A system is a function that accepts an input signal and yields an output signal. Embedded Systems 2 REVIEW: Actor models A system is a function that accepts an input signal and yields an output signal. The domain and range of the system function are sets of signals, which themselves

More information

Chapter 3: Linear temporal logic

Chapter 3: Linear temporal logic INFOF412 Formal verification of computer systems Chapter 3: Linear temporal logic Mickael Randour Formal Methods and Verification group Computer Science Department, ULB March 2017 1 LTL: a specification

More information

Reduced Ordered Binary Decision Diagrams

Reduced Ordered Binary Decision Diagrams Reduced Ordered Binary Decision Diagrams Lecture #12 of Advanced Model Checking Joost-Pieter Katoen Lehrstuhl 2: Software Modeling & Verification E-mail: katoen@cs.rwth-aachen.de December 13, 2016 c JPK

More information

Temporal logics and explicit-state model checking. Pierre Wolper Université de Liège

Temporal logics and explicit-state model checking. Pierre Wolper Université de Liège Temporal logics and explicit-state model checking Pierre Wolper Université de Liège 1 Topics to be covered Introducing explicit-state model checking Finite automata on infinite words Temporal Logics and

More information

Design of Distributed Systems Melinda Tóth, Zoltán Horváth

Design of Distributed Systems Melinda Tóth, Zoltán Horváth Design of Distributed Systems Melinda Tóth, Zoltán Horváth Design of Distributed Systems Melinda Tóth, Zoltán Horváth Publication date 2014 Copyright 2014 Melinda Tóth, Zoltán Horváth Supported by TÁMOP-412A/1-11/1-2011-0052

More information

an efficient procedure for the decision problem. We illustrate this phenomenon for the Satisfiability problem.

an efficient procedure for the decision problem. We illustrate this phenomenon for the Satisfiability problem. 1 More on NP In this set of lecture notes, we examine the class NP in more detail. We give a characterization of NP which justifies the guess and verify paradigm, and study the complexity of solving search

More information

Recent results on Timed Systems

Recent results on Timed Systems Recent results on Timed Systems Time Petri Nets and Timed Automata Béatrice Bérard LAMSADE Université Paris-Dauphine & CNRS berard@lamsade.dauphine.fr Based on joint work with F. Cassez, S. Haddad, D.

More information

Computation Tree Logic

Computation Tree Logic Chapter 6 Computation Tree Logic Pnueli [88] has introduced linear temporal logic to the computer science community for the specification and verification of reactive systems. In Chapter 3 we have treated

More information

Software Verification with Abstraction-Based Methods

Software Verification with Abstraction-Based Methods Software Verification with Abstraction-Based Methods Ákos Hajdu PhD student Department of Measurement and Information Systems, Budapest University of Technology and Economics MTA-BME Lendület Cyber-Physical

More information

In this episode of The Verification Corner, Rustan Leino talks about Loop Invariants. He gives a brief summary of the theoretical foundations and

In this episode of The Verification Corner, Rustan Leino talks about Loop Invariants. He gives a brief summary of the theoretical foundations and In this episode of The Verification Corner, Rustan Leino talks about Loop Invariants. He gives a brief summary of the theoretical foundations and shows how a program can sometimes be systematically constructed

More information

Logic in Automatic Verification

Logic in Automatic Verification Logic in Automatic Verification Javier Esparza Sofware Reliability and Security Group Institute for Formal Methods in Computer Science University of Stuttgart Many thanks to Abdelwaheb Ayari, David Basin,

More information

Lecture 2: Symbolic Model Checking With SAT

Lecture 2: Symbolic Model Checking With SAT Lecture 2: Symbolic Model Checking With SAT Edmund M. Clarke, Jr. School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 (Joint work over several years with: A. Biere, A. Cimatti, Y.

More information

Undecidable Problems. Z. Sawa (TU Ostrava) Introd. to Theoretical Computer Science May 12, / 65

Undecidable Problems. Z. Sawa (TU Ostrava) Introd. to Theoretical Computer Science May 12, / 65 Undecidable Problems Z. Sawa (TU Ostrava) Introd. to Theoretical Computer Science May 12, 2018 1/ 65 Algorithmically Solvable Problems Let us assume we have a problem P. If there is an algorithm solving

More information

Petri nets. s 1 s 2. s 3 s 4. directed arcs.

Petri nets. s 1 s 2. s 3 s 4. directed arcs. Petri nets Petri nets Petri nets are a basic model of parallel and distributed systems (named after Carl Adam Petri). The basic idea is to describe state changes in a system with transitions. @ @R s 1

More information

LTL Model Checking. Wishnu Prasetya.

LTL Model Checking. Wishnu Prasetya. LTL Model Checking Wishnu Prasetya wishnu@cs.uu.nl www.cs.uu.nl/docs/vakken/pv Overview This pack : Abstract model of programs Temporal properties Verification (via model checking) algorithm Concurrency

More information

NP-Completeness. A language B is NP-complete iff B NP. This property means B is NP hard

NP-Completeness. A language B is NP-complete iff B NP. This property means B is NP hard NP-Completeness A language B is NP-complete iff B NP A NP A P B This property means B is NP hard 1 3SAT is NP-complete 2 Result Idea: B is known to be NP complete Use it to prove NP-Completeness of C IF

More information

CTL Model checking. 1. finite number of processes, each having a finite number of finite-valued variables. Model-Checking

CTL Model checking. 1. finite number of processes, each having a finite number of finite-valued variables. Model-Checking CTL Model checking Assumptions:. finite number of processes, each having a finite number of finite-valued variables.. finite length of CTL formula Problem:Determine whether formula f 0 is true in a finite

More information

Temporal & Modal Logic. Acronyms. Contents. Temporal Logic Overview Classification PLTL Syntax Semantics Identities. Concurrency Model Checking

Temporal & Modal Logic. Acronyms. Contents. Temporal Logic Overview Classification PLTL Syntax Semantics Identities. Concurrency Model Checking Temporal & Modal Logic E. Allen Emerson Presenter: Aly Farahat 2/12/2009 CS5090 1 Acronyms TL: Temporal Logic BTL: Branching-time Logic LTL: Linear-Time Logic CTL: Computation Tree Logic PLTL: Propositional

More information

Overview. Discrete Event Systems Verification of Finite Automata. What can finite automata be used for? What can finite automata be used for?

Overview. Discrete Event Systems Verification of Finite Automata. What can finite automata be used for? What can finite automata be used for? Computer Engineering and Networks Overview Discrete Event Systems Verification of Finite Automata Lothar Thiele Introduction Binary Decision Diagrams Representation of Boolean Functions Comparing two circuits

More information

NP and Computational Intractability

NP and Computational Intractability NP and Computational Intractability 1 Polynomial-Time Reduction Desiderata'. Suppose we could solve X in polynomial-time. What else could we solve in polynomial time? don't confuse with reduces from Reduction.

More information

The Complexity of Computing the Behaviour of Lattice Automata on Infinite Trees

The Complexity of Computing the Behaviour of Lattice Automata on Infinite Trees The Complexity of Computing the Behaviour of Lattice Automata on Infinite Trees Karsten Lehmann a, Rafael Peñaloza b a Optimisation Research Group, NICTA Artificial Intelligence Group, Australian National

More information

Revising UNITY Programs: Possibilities and Limitations 1

Revising UNITY Programs: Possibilities and Limitations 1 Revising UNITY Programs: Possibilities and Limitations 1 Ali Ebnenasir, Sandeep S. Kulkarni, and Borzoo Bonakdarpour Software Engineering and Network Systems Laboratory Department of Computer Science and

More information

Logic Model Checking

Logic Model Checking Logic Model Checking Lecture Notes 10:18 Caltech 101b.2 January-March 2004 Course Text: The Spin Model Checker: Primer and Reference Manual Addison-Wesley 2003, ISBN 0-321-22862-6, 608 pgs. the assignment

More information

Timo Latvala. March 7, 2004

Timo Latvala. March 7, 2004 Reactive Systems: Safety, Liveness, and Fairness Timo Latvala March 7, 2004 Reactive Systems: Safety, Liveness, and Fairness 14-1 Safety Safety properties are a very useful subclass of specifications.

More information

Introduction to Temporal Logic. The purpose of temporal logics is to specify properties of dynamic systems. These can be either

Introduction to Temporal Logic. The purpose of temporal logics is to specify properties of dynamic systems. These can be either Introduction to Temporal Logic The purpose of temporal logics is to specify properties of dynamic systems. These can be either Desired properites. Often liveness properties like In every infinite run action

More information

Propositional and First Order Reasoning

Propositional and First Order Reasoning Propositional and First Order Reasoning Terminology Propositional variable: boolean variable (p) Literal: propositional variable or its negation p p Clause: disjunction of literals q \/ p \/ r given by

More information

Bounded LTL Model Checking with Stable Models

Bounded LTL Model Checking with Stable Models Bounded LTL Model Checking with Stable Models Keijo Heljanko and Ilkka Niemelä Helsinki University of Technology Dept. of Computer Science and Engineering Laboratory for Theoretical Computer Science P.O.

More information

Timed Automata. Chapter Clocks and clock constraints Clock variables and clock constraints

Timed Automata. Chapter Clocks and clock constraints Clock variables and clock constraints Chapter 10 Timed Automata In the previous chapter, we have discussed a temporal logic where time was a discrete entities. A time unit was one application of the transition relation of an LTS. We could

More information

In recent years CTL and LTL logics have been used with considerable industrial success.

In recent years CTL and LTL logics have been used with considerable industrial success. Modelchecking In recent years CTL and LTL logics have been used with considerable industrial success. For example microprocessors manufacturers (like Intel, Motorola) use programs which automatically can

More information

SAT, NP, NP-Completeness

SAT, NP, NP-Completeness CS 473: Algorithms, Spring 2018 SAT, NP, NP-Completeness Lecture 22 April 13, 2018 Most slides are courtesy Prof. Chekuri Ruta (UIUC) CS473 1 Spring 2018 1 / 57 Part I Reductions Continued Ruta (UIUC)

More information

Announcements. Friday Four Square! Problem Set 8 due right now. Problem Set 9 out, due next Friday at 2:15PM. Did you lose a phone in my office?

Announcements. Friday Four Square! Problem Set 8 due right now. Problem Set 9 out, due next Friday at 2:15PM. Did you lose a phone in my office? N P NP Completeness Announcements Friday Four Square! Today at 4:15PM, outside Gates. Problem Set 8 due right now. Problem Set 9 out, due next Friday at 2:15PM. Explore P, NP, and their connection. Did

More information

SAT in Formal Hardware Verification

SAT in Formal Hardware Verification SAT in Formal Hardware Verification Armin Biere Institute for Formal Models and Verification Johannes Kepler University Linz, Austria Invited Talk SAT 05 St. Andrews, Scotland 20. June 2005 Overview Hardware

More information

Algorithmic verification

Algorithmic verification Algorithmic verification Ahmed Rezine IDA, Linköpings Universitet Hösttermin 2018 Outline Overview Model checking Symbolic execution Outline Overview Model checking Symbolic execution Program verification

More information

Probabilistic Model Checking and Strategy Synthesis for Robot Navigation

Probabilistic Model Checking and Strategy Synthesis for Robot Navigation Probabilistic Model Checking and Strategy Synthesis for Robot Navigation Dave Parker University of Birmingham (joint work with Bruno Lacerda, Nick Hawes) AIMS CDT, Oxford, May 2015 Overview Probabilistic

More information

NP-Completeness Part II

NP-Completeness Part II NP-Completeness Part II Please evaluate this course on Axess. Your comments really do make a difference. Announcements Problem Set 8 due tomorrow at 12:50PM sharp with one late day. Problem Set 9 out,

More information

Revising Distributed UNITY Programs is NP-Complete

Revising Distributed UNITY Programs is NP-Complete Revising Distributed UNITY Programs is NP-Complete Borzoo Bonakdarpour and Sandeep S. Kulkarni Department of Computer Science and Engineering Michigan State University East Lansing, MI 48824, U.S.A. {borzoo,sandeep}@cse.msu.edu

More information

Comp487/587 - Boolean Formulas

Comp487/587 - Boolean Formulas Comp487/587 - Boolean Formulas 1 Logic and SAT 1.1 What is a Boolean Formula Logic is a way through which we can analyze and reason about simple or complicated events. In particular, we are interested

More information

Introduction to Model Checking. Debdeep Mukhopadhyay IIT Madras

Introduction to Model Checking. Debdeep Mukhopadhyay IIT Madras Introduction to Model Checking Debdeep Mukhopadhyay IIT Madras How good can you fight bugs? Comprising of three parts Formal Verification techniques consist of three parts: 1. A framework for modeling

More information

Model Checking, Theorem Proving, and Abstract Interpretation: The Convergence of Formal Verification Technologies

Model Checking, Theorem Proving, and Abstract Interpretation: The Convergence of Formal Verification Technologies Model Checking, Theorem Proving, and Abstract Interpretation: The Convergence of Formal Verification Technologies Tom Henzinger EPFL Three Verification Communities Model checking: -automatic, but inefficient

More information

Modeling Concurrent Systems

Modeling Concurrent Systems Modeling Concurrent Systems Wolfgang Schreiner Wolfgang.Schreiner@risc.uni-linz.ac.at Research Institute for Symbolic Computation (RISC) Johannes Kepler University, Linz, Austria http://www.risc.uni-linz.ac.at

More information

Temporal Logic Model Checking

Temporal Logic Model Checking 18 Feb, 2009 Thomas Wahl, Oxford University Temporal Logic Model Checking 1 Temporal Logic Model Checking Thomas Wahl Computing Laboratory, Oxford University 18 Feb, 2009 Thomas Wahl, Oxford University

More information

Snapshots. Chandy-Lamport Algorithm for the determination of consistent global states <$1000, 0> <$50, 2000> mark. (order 10, $100) mark

Snapshots. Chandy-Lamport Algorithm for the determination of consistent global states <$1000, 0> <$50, 2000> mark. (order 10, $100) mark 8 example: P i P j (5 widgets) (order 10, $100) cji 8 ed state P i : , P j : , c ij : , c ji : Distributed Systems

More information

Turing Machines and Time Complexity

Turing Machines and Time Complexity Turing Machines and Time Complexity Turing Machines Turing Machines (Infinitely long) Tape of 1 s and 0 s Turing Machines (Infinitely long) Tape of 1 s and 0 s Able to read and write the tape, and move

More information

Model Checking of Safety Properties

Model Checking of Safety Properties Model Checking of Safety Properties Orna Kupferman Hebrew University Moshe Y. Vardi Rice University October 15, 2010 Abstract Of special interest in formal verification are safety properties, which assert

More information

A Symbolic Approach to Safety LTL Synthesis

A Symbolic Approach to Safety LTL Synthesis A Symbolic Approach to Safety LTL Synthesis Shufang Zhu 1 Lucas M. Tabajara 2 Jianwen Li Geguang Pu 1 Moshe Y. Vardi 2 1 East China Normal University 2 Rice Lucas M. Tabajara (Rice University) 2 University

More information

The efficiency of identifying timed automata and the power of clocks

The efficiency of identifying timed automata and the power of clocks The efficiency of identifying timed automata and the power of clocks Sicco Verwer a,b,1,, Mathijs de Weerdt b, Cees Witteveen b a Eindhoven University of Technology, Department of Mathematics and Computer

More information

SAT-Based Verification of Safe Petri Nets

SAT-Based Verification of Safe Petri Nets SAT-Based Verification of Safe Petri Nets Shougo Ogata, Tatsuhiro Tsuchiya, and Tohru Kiuno Department of Information Systems Engineering Graduate School of Information Science and Technology, Osaa University

More information

Lecture 7 Synthesis of Reactive Control Protocols

Lecture 7 Synthesis of Reactive Control Protocols Lecture 7 Synthesis of Reactive Control Protocols Richard M. Murray Nok Wongpiromsarn Ufuk Topcu California Institute of Technology AFRL, 25 April 2012 Outline Review: networked control systems and cooperative

More information

Verification. Arijit Mondal. Dept. of Computer Science & Engineering Indian Institute of Technology Patna

Verification. Arijit Mondal. Dept. of Computer Science & Engineering Indian Institute of Technology Patna IIT Patna 1 Verification Arijit Mondal Dept. of Computer Science & Engineering Indian Institute of Technology Patna arijit@iitp.ac.in Introduction The goal of verification To ensure 100% correct in functionality

More information

Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods

Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods Sanjit A. Seshia and Randal E. Bryant Computer Science Department Carnegie Mellon University Verifying Timed Embedded Systems

More information

Probabilistic verification and approximation schemes

Probabilistic verification and approximation schemes Probabilistic verification and approximation schemes Richard Lassaigne Equipe de Logique mathématique, CNRS-Université Paris 7 Joint work with Sylvain Peyronnet (LRDE/EPITA & Equipe de Logique) Plan 1

More information

Axiomatic Semantics: Verification Conditions. Review of Soundness and Completeness of Axiomatic Semantics. Announcements

Axiomatic Semantics: Verification Conditions. Review of Soundness and Completeness of Axiomatic Semantics. Announcements Axiomatic Semantics: Verification Conditions Meeting 12, CSCI 5535, Spring 2009 Announcements Homework 4 is due tonight Wed forum: papers on automated testing using symbolic execution 2 Questions? Review

More information

Intro to Theory of Computation

Intro to Theory of Computation Intro to Theory of Computation LECTURE 25 Last time Class NP Today Polynomial-time reductions Adam Smith; Sofya Raskhodnikova 4/18/2016 L25.1 The classes P and NP P is the class of languages decidable

More information

Satisfiability and SAT Solvers. CS 270 Math Foundations of CS Jeremy Johnson

Satisfiability and SAT Solvers. CS 270 Math Foundations of CS Jeremy Johnson Satisfiability and SAT Solvers CS 270 Math Foundations of CS Jeremy Johnson Conjunctive Normal Form Conjunctive normal form (products of sums) Conjunction of clauses (disjunction of literals) For each

More information

Chapter 3 Deterministic planning

Chapter 3 Deterministic planning Chapter 3 Deterministic planning In this chapter we describe a number of algorithms for solving the historically most important and most basic type of planning problem. Two rather strong simplifying assumptions

More information

Semantic Equivalences and the. Verification of Infinite-State Systems 1 c 2004 Richard Mayr

Semantic Equivalences and the. Verification of Infinite-State Systems 1 c 2004 Richard Mayr Semantic Equivalences and the Verification of Infinite-State Systems Richard Mayr Department of Computer Science Albert-Ludwigs-University Freiburg Germany Verification of Infinite-State Systems 1 c 2004

More information

Correctness of Dijkstra s algorithm

Correctness of Dijkstra s algorithm Correctness of Dijkstra s algorithm Invariant: When vertex u is deleted from the priority queue, d[u] is the correct length of the shortest path from the source s to vertex u. Additionally, the value d[u]

More information

Principles of Computing, Carnegie Mellon University. The Limits of Computing

Principles of Computing, Carnegie Mellon University. The Limits of Computing The Limits of Computing Intractability Limits of Computing Announcement Final Exam is on Friday 9:00am 10:20am Part 1 4:30pm 6:10pm Part 2 If you did not fill in the course evaluations please do it today.

More information

CS 267: Automated Verification. Lecture 1: Brief Introduction. Transition Systems. Temporal Logic LTL. Instructor: Tevfik Bultan

CS 267: Automated Verification. Lecture 1: Brief Introduction. Transition Systems. Temporal Logic LTL. Instructor: Tevfik Bultan CS 267: Automated Verification Lecture 1: Brief Introduction. Transition Systems. Temporal Logic LTL. Instructor: Tevfik Bultan What do these people have in common? 2013 Leslie Lamport 2007 Clarke, Edmund

More information

Analysis and Optimization of Discrete Event Systems using Petri Nets

Analysis and Optimization of Discrete Event Systems using Petri Nets Volume 113 No. 11 2017, 1 10 ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu ijpam.eu Analysis and Optimization of Discrete Event Systems using Petri Nets

More information

POLYNOMIAL SPACE QSAT. Games. Polynomial space cont d

POLYNOMIAL SPACE QSAT. Games. Polynomial space cont d T-79.5103 / Autumn 2008 Polynomial Space 1 T-79.5103 / Autumn 2008 Polynomial Space 3 POLYNOMIAL SPACE Polynomial space cont d Polynomial space-bounded computation has a variety of alternative characterizations

More information

NP-Completeness and Boolean Satisfiability

NP-Completeness and Boolean Satisfiability NP-Completeness and Boolean Satisfiability Mridul Aanjaneya Stanford University August 14, 2012 Mridul Aanjaneya Automata Theory 1/ 49 Time-Bounded Turing Machines A Turing Machine that, given an input

More information

MODEL CHECKING. Arie Gurfinkel

MODEL CHECKING. Arie Gurfinkel 1 MODEL CHECKING Arie Gurfinkel 2 Overview Kripke structures as models of computation CTL, LTL and property patterns CTL model-checking and counterexample generation State of the Art Model-Checkers 3 SW/HW

More information

Intelligent Agents. Formal Characteristics of Planning. Ute Schmid. Cognitive Systems, Applied Computer Science, Bamberg University

Intelligent Agents. Formal Characteristics of Planning. Ute Schmid. Cognitive Systems, Applied Computer Science, Bamberg University Intelligent Agents Formal Characteristics of Planning Ute Schmid Cognitive Systems, Applied Computer Science, Bamberg University Extensions to the slides for chapter 3 of Dana Nau with contributions by

More information

Symbolic Model Checking Property Specification Language*

Symbolic Model Checking Property Specification Language* Symbolic Model Checking Property Specification Language* Ji Wang National Laboratory for Parallel and Distributed Processing National University of Defense Technology *Joint Work with Wanwei Liu, Huowang

More information

Notes. Corneliu Popeea. May 3, 2013

Notes. Corneliu Popeea. May 3, 2013 Notes Corneliu Popeea May 3, 2013 1 Propositional logic Syntax We rely on a set of atomic propositions, AP, containing atoms like p, q. A propositional logic formula φ Formula is then defined by the following

More information

Automata, Logic and Games: Theory and Application

Automata, Logic and Games: Theory and Application Automata, Logic and Games: Theory and Application 1. Büchi Automata and S1S Luke Ong University of Oxford TACL Summer School University of Salerno, 14-19 June 2015 Luke Ong Büchi Automata & S1S 14-19 June

More information

Tecniche di Verifica. Introduction to Propositional Logic

Tecniche di Verifica. Introduction to Propositional Logic Tecniche di Verifica Introduction to Propositional Logic 1 Logic A formal logic is defined by its syntax and semantics. Syntax An alphabet is a set of symbols. A finite sequence of these symbols is called

More information

Failure Diagnosis of Discrete Event Systems With Linear-Time Temporal Logic Specifications

Failure Diagnosis of Discrete Event Systems With Linear-Time Temporal Logic Specifications Failure Diagnosis of Discrete Event Systems With Linear-Time Temporal Logic Specifications Shengbing Jiang and Ratnesh Kumar Abstract The paper studies failure diagnosis of discrete event systems with

More information

3-Valued Abstraction-Refinement

3-Valued Abstraction-Refinement 3-Valued Abstraction-Refinement Sharon Shoham Academic College of Tel-Aviv Yaffo 1 Model Checking An efficient procedure that receives: A finite-state model describing a system A temporal logic formula

More information

Easy Problems vs. Hard Problems. CSE 421 Introduction to Algorithms Winter Is P a good definition of efficient? The class P

Easy Problems vs. Hard Problems. CSE 421 Introduction to Algorithms Winter Is P a good definition of efficient? The class P Easy Problems vs. Hard Problems CSE 421 Introduction to Algorithms Winter 2000 NP-Completeness (Chapter 11) Easy - problems whose worst case running time is bounded by some polynomial in the size of the

More information

Symbolic Computation and Theorem Proving in Program Analysis

Symbolic Computation and Theorem Proving in Program Analysis Symbolic Computation and Theorem Proving in Program Analysis Laura Kovács Chalmers Outline Part 1: Weakest Precondition for Program Analysis and Verification Part 2: Polynomial Invariant Generation (TACAS

More information

Notes for Lecture 3... x 4

Notes for Lecture 3... x 4 Stanford University CS254: Computational Complexity Notes 3 Luca Trevisan January 14, 2014 Notes for Lecture 3 In this lecture we introduce the computational model of boolean circuits and prove that polynomial

More information

New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations

New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations (Extended Abstract) Gaoyan Xie, Cheng Li and Zhe Dang School of Electrical Engineering and

More information

Verification Using Temporal Logic

Verification Using Temporal Logic CMSC 630 February 25, 2015 1 Verification Using Temporal Logic Sources: E.M. Clarke, O. Grumberg and D. Peled. Model Checking. MIT Press, Cambridge, 2000. E.A. Emerson. Temporal and Modal Logic. Chapter

More information

An On-the-fly Tableau Construction for a Real-Time Temporal Logic

An On-the-fly Tableau Construction for a Real-Time Temporal Logic #! & F $ F ' F " F % An On-the-fly Tableau Construction for a Real-Time Temporal Logic Marc Geilen and Dennis Dams Faculty of Electrical Engineering, Eindhoven University of Technology P.O.Box 513, 5600

More information

Lecture 25: Cook s Theorem (1997) Steven Skiena. skiena

Lecture 25: Cook s Theorem (1997) Steven Skiena.   skiena Lecture 25: Cook s Theorem (1997) Steven Skiena Department of Computer Science State University of New York Stony Brook, NY 11794 4400 http://www.cs.sunysb.edu/ skiena Prove that Hamiltonian Path is NP

More information