Nanowire Addressing with Randomized-Contact Decoders

Transcription

1 Nanowire Addressing with Randomized-Contact Decoders Eric Rachlin and John E. Savage Computer Science, Brown University Providence, RI Introduction The dream of nanoscale computing was first articulated by Richard Feynman in his 1959 speech to the American Physical Society. He argued that no physical law prevented the room-sized computers of the 1950 s from being replaced with vastly more powerful pin-sized computers built from billions of nanoscale devices. Since then computers have become orders of magnitude smaller, faster and more powerful. Their wires and gates, however, have not yet reached the nanoscale (i.e., the dimensions of individual molecules). Although individual nanoscale devices have been demonstrated, we lack the ability to place these devices with nanoscale precision. As a result, near-term nanoscale architectures will be assembled stochastically. The range of device variation these architectures must tolerate makes them fundamentally different from today s CMOS. Our approach to nanoscale circuit design must change accordingly. For the past 30 years, chips with ever shrinking features have been produced using photolithography. Wires and gates are defined using light on a silicon substrate. This allows many copies of a chip to be produced from a single set of costly masks. Although

2 OC OC Nanowires Mesowires OC OC Nanowires PMs OC OC Mesowires OC OC Fig. 1. A crossbar formed from two orthogonal sets of NWs with programmable molecules (PMs) at the crosspoints defined by intersecting NWs. NWs are divided into contact groups by connecting them to ohmic contacts (OCs). To activate a NW in one dimension, a contact group is activated and MWs are used to deactivate all but one NW in that group. Data is stored at a crosspoint by applying a large electric field across it. Data is sensed with a smaller field. photolithography allows for a very wide range of circuit designs, the wavelength of light (193nm or greater) is too large to allow for features on the order of a few nanometers, the range considered in this paper. Nanoscale architectures require new manufacturing technology. A particularly viable basis for nanoscale architectures that has received significant attention in the physical science and engineering communities is the nanowire crossbar [1,2] (See Figure 1). Here a grid of nanowires (NWs) provides control over molecular devices that reside at their crosspoints. Like traditional crossbars, NW crossbars can act as memories (such as RAM) and circuits (such as PLAs) [3,4]. Unlike traditional crossbars, however, their assembly is stochastic. This results in three very important challenges: (1) NWs are randomly assigned physical addresses. (2) A testing procedure is required to configure a crossbar s control circuitry. (3) Permanent and transient faults must be tolerated. 2

3 To overcome these challenges, nanoscale crossbar-based architectures rely on stochastically assembled NW decoders. A nanowire decoder is any device capable of controlling the resistances of individual NWs using larger lithographically-produced mesoscale wires (MWs) and ohmic contacts (OCs). In Section 2 we explain how NW decoders can be used to control a NW crossbar-based memory. To date, all proposed NW decoders rely on a stochastic assembly process. Three types of NW decoder have been analyzed probabilistically, encoded NW decoders, mask-based decoders, and randomized-contact decoders. In Section 3 we describe these decoders and summarize their performance. We also provide a new bound on the number of MWs an encoded NW decoder requires to control a large fraction of all NWs. In Section 4 we examine in detail the addressing of NWs by MWs and derive conditions that must be met by the resistances of NW/MW junctions in order to address NWs correctly. This allows us to give a model of NW decoders that it explicitly takes manufacturing errors into account. In Section 5 we use this model to derive probabilistic bounds on the number of MWs needed to address NWs with the randomizedcontact decoder (RCD). We bound the number of MWs needed to address all NWs connected to a single OC. We also bound the number of MWs required to address some fixed fraction of NWs across all OCs. Our analysis demonstrates that RCDs are efficient and robust. They can reliably control a large number of NWs using a small number of MWs, even when some fraction of contacts between MWs and NWs are defective. Our bounds improve upon the analysis of [5]. They take errors into account and also make explicit the probability that the bounds hold. Additionally, their derivation is more precise, as it avoids an unnecessary independence approximation (see Section 3.3). This ensures that our bounds apply even to small 3

4 groups of NWs connected to OCs. In the case of a large number of NWs connected to an OC, our bound on the number of MWs required to address all NWs agrees with the asymptotic analysis in in [5]. We also note that previous work on coping with manufacturing defects in NW decoders has focused on the use of error correcting codes [6 8]. In these coding-based approaches, a specific error correcting code is used to determine which subsets of MWs have the ability to address NWs. Viewed in this light, the bounds of Section 5 show that even randomly generated codes provide good defect-tolerance with only constant factor overhead. This is a significant insight, since it eliminates the requirement that a NW decoder provide designers with a great deal of control over which subsets of MWs can control NWs. This level of control is present in encoded NW decoders [8], or programmable NW decoders [9,7] (which themselves require a second NW decoder to configure), but is not present in RCDs, which are arguably simpler to manufacture. Since we cannot predict in advance which MWs will control which NWs, NW addresses must be discovered after an RCD is assembled. These addresses must then be stored and mapped to fixed binary addresses using programmable circuitry. Strategies for implementing this mapping and a method for estimating the area used by a crossbar as well as its addressing circuitry are discussed in Section 6. The need for such circuitry is also mentioned in [3], but the varying overhead associated with specific mapping strategies is not considered. In [10] specific mappings are considered in the context of encoded NW decoders, but not the Almost All Wires Addressable and Take What You Get strategies presented here. The problem of discovering which subsets of MWs address NWs is discussed in Section 7. Exhaustive search is considered, as is a search randomized algorithm. The randomized algorithm is an- 4

5 alyzed in Section 8. Again, we improve on work done in [5], relaxing an assumption about what testing circuitry is present. We also correct an independence assumption that is not met unless the number of MWs used to control the NWs connected to an OC is much larger than what the bounds of Section 5 require. Conclusions are drawn in Section 9. 2 Crossbar Overview To motivate our analysis, we briefly describe how NW crossbars can be used as memories. This approach can be extended to circuits as well [4]. Since our research focuses on controlling individual NWs with MWs, crossbar-based memories offer sufficient motivation. 2.1 Crossbar Assembly There are multiple approaches to constructing a NW crossbar. Undifferentiated NWs can be stamped onto a chip, [11 13], or alternatively, many types of differentiated NWs can be grown off chip, collected in a large ensemble, then deposited fluidically [14,15]. In either approach, a molecular layer is deposited between two layers of parallel NWs. This layer can be comprised of molecular diodes that switch between a low and high resistance in a large electric field [16,17]. A layer of amorphous silicon has also been proposed as a storage medium [18]. Programmable devices that do not behave like diodes (e.g. nanoscale resistors or transistors) have also been considered [19,9]. Some of these alternatives have been compared to diodes with regard to their information storage capacity and ability to control NWs [20,7,21]. When used for information storage, resistors are inferior to other alternatives [20]. Once a NW crossbar is assembled, g OCs and M MWs can be 5

6 placed along each dimension of the crossbar using photolithography (see Figure 1). Although each MW controls (makes nonconducting) a subset of the NWs, these subsets cannot be chosen deterministically. For each NW, we can describe the subset of MWs that control it using a binary M-tuple. We call this a NW codeword. In the case of undifferentiated NWs, two methods have been proposed to control NWs with MWs. The first, the randomizedcontact decoder (RCD), is analyzed here. A proposed approach for producing an RCD is to randomly deposit nanometer-sized particles between NWs and MWs, making each NW/MW junction controlling with some fixed probability [5,22]. The second method for controlling undifferentiated NWs relies on randomly shifted lithographically-defined regions of high-k dielectric material between NWs and MWs [23,24]. Here again, each MW is made to control some random subset of the NWs. Additional methods for producing decoders are possible using differentiated NWs [25,26]. 2.2 Crossbar Operation In a crossbar memory, NWs along each dimension are divided up into g contact groups of N NWs each. NWs in each contact group are connected to a common OC. To use the crossbar as a memory, a voltage is applied to a single contact group of NWs along each dimension of the crossbar. Subsets of MWs along each dimension are then used to address NWs within each of the two groups. This operation can either read or write a single bit to the crosspoints of the NWs being addressed (See Figure 2). If multiple NWs connected to an OC are addressed by the same set of MWs, it may be acceptable to store the same bit at multiple crosspoints. In a write operation, the diodes at crosspoints are turned on or off by applying a large potential between one or more pairs of 6

7 OC OC OC OC OC OC OC OC OC OC OC OC OC OC Read OC OC Write OC Fig. 2. A crossbar-based memory in which OCs and MWs read and write data to programmable molecules at crosspoints. The darkened segments along each NW indicate lightly doped regions. These regions become nonconducting when the adjacent MW is turned on. In a read operation an OC at each end of a NW is disconnected from ground. Current flows through any conducting NW crosspoints that are addressed by MWs. The amount of current reveals the value stored at the crosspoints. In a write operation, NWs along each dimension apply a larger electric field across their crosspoints. The direction of the field determines the value stored at the crosspoints. In this figure, the same bit of information is stored at two crosspoints. orthogonal NWs by addressing (giving low resistance to) one or more NWs in each dimension. Both ends of the NWs are maintained at the same potential. The polarity of the potential determines the state of a crosspoint and the value written. In a read operation, a smaller voltage is used, allowing the decoder to detect the state of crosspoints. In a read operation each NW is disconnected from one of its ohmic contacts. Current will either flow or not flow through a crosspoint, depending on its state. The amount of current reveals the resistive state of the crosspoints, and thus the value being stored. Both read and write operations require that the NWs being addressed have a significantly lower resistance than the other NWs in the same contact group. This requirement is formalized at the beginning of Section Address Translation Circuitry When a memory is supplied with a particular external binary address, address translation circuitry (ATC) along each di- 7

8 mension of the crossbar maps that address to a contact group and MW input. This mapping depends on the stochastic assembly of the decoder. To ensure each external address addresses some NW, the ATC must store information about which MWs control which NWs. In the next subsection, we discuss how this information can be obtained. For now, assume it is known and consider the storage overhead required. In order to make address translation circuitry fast, reliable, and easy to manufacture, it may be implemented in CMOS. Any approximation of the area of the memory must take into account not just the area of MWs and ohmic contacts, but also the area used to store physical NW addresses using CMOS. We explicitly model the size of address translation circuitry in [10], but it has received less attention elsewhere. The appendix of [3], also estimates the area required for the ATC, but does so without exploring how different address mapping strategies affect area requirements. The prospect of implementing the ATC using nanoscale storage is considered in [9]. Most previous work on NW decoders has focused on the number of MWs required to control NWs. Although MWs are much wider than NWs, they are still relatively small. In an RCD, however, each NW/MW junction, corresponds to a bit of storage in address translation circuitry. As a result, these bits, when stored in mesoscale devices, collectively take up far more area than the NW/MW junctions. The ATC must associate a contact group and codeword with each external address. In the worst case, this requires log 2 g + M bits of storage per NW. In some cases fewer bits are required. For example, if all NWs can be addressed, and the number of NWs per contact group is a power of 2, the high order bits of an external address can be used to index a contact group. The address translation circuitry now requires only M bits of storage for each NW. The way in which external addresses are mapped to NWs is called an addressing strategy. Later, several addressing 8

9 strategies are discussed in detail. As we explain, some addressing strategies require more overall area than others. 2.4 Address Discovery We also explore the problem of testing. In an RCD, each NW has a physical address determined by which MWs control it. Since addresses are randomly generated during decoder assembly, they must be discovered. This is a difficult problem, as some addresses mask others, and faults make test outputs unreliable. We evaluate the effectiveness of several simple testing procedures that do not require read/write operations. In [10], an efficient testing procedure involving read/write operations was given for differentiated NW decoders. The algorithm s reliance on nanoscale storage devices is a drawback. Read/write operations are relatively time consuming, and possibly faulty. Also, in circuits, they may not be possible at all (as not all NWs will be used to control nanoscale storage devices). The testing algorithms we consider are only allowed to apply a voltage across a contact group, turn on a subset of the MWs, and observe if any NW remains conducting. This test does not reveal which NW is on, nor does it reveal if multiple NWs are on. Nonetheless, it is sufficiently powerful to determine which subsets of MWs address individual NWs. As it turns out, the algorithm in [10] can also be adapted to this model. Unfortunately it does not work for RCDs. A discovery algorithm for RCDs is given in [5], which we improve upon in Section 7 on this algorithm here. We also improve upon its analysis. 3 Decoding Technologies In this section we describe three types of NW decoder. Each type of decoder can itself be manufactured in multiple ways. As 9

10 shown in Section 4, however, all three decoders can be modeled in a unified way. Using this model, we analyze the number of MWs required by an RCD in Section 5. In Section 6 we estimate the total amount of area RCDs require. 3.1 The Encoded NW Decoder Encoded NW decoders work with two kinds of NWs, modulationdoped NWs [27,28], NWs with sequences of lightly and heavily doped regions, and radially encoded NWs [29], NWs with removable shells. In both cases many NW types are prepared separately, each with a different encoding. When modulation-doped NWs are used, encodings correspond to patterns of lightly and heavily doped regions. When radially encoded NWs are used, encodings correspond to sequences of shells. In either case many NWs of each type are all collected in a large ensemble then deposited onto a chip using fluidic methods that align the NWs in parallel [30]. When MWs are placed across the NWs, any NW/MW junction comprised of a lightly doped region forms a field effect transistor (FET). The application of an immobilizing electric field to the MW causes the resistance of the junction to become high. A NW is addressed by applying fields to all MWs that do not significantly increase its resistance. If doping sequences are properly chosen, only one type of NW will become nonconducting. (See Figures 1 and 2.) In practice, lightly doped NW regions will not align perfectly with MWs [29]. Consequently, a MW s control over a NW can be ambiguous. Several methods for encoding modulation-doped NWs are studied in [10]. The encoded NW decoder also works with radially encoded NWs, that is, NWs that have shells composed of differentially etchable NWs [29]. There are several ways to control these NWs with MWs. The simplest method uses one MW to control each type of NW. Each NW type is grown with a different sequence of s 10

11 shells surrounding a lightly doped core. Once NWs have been deposited, a different sequence of s shells are etched away in the space reserved for each MW. Under each MW, only the lightly doped cores of one NW type are exposed, and if shells are sufficiently thick, each MW controls only NWs with exposed cores. Radially encoded NWs do not suffer from misalignment but may require slightly larger radii than modulation-doped NWs Known Results In an encoded NW decoder, the number of controllable NWs depends on the number of differently-encoded NW types, C, being used. This in turn determines how many MWs, M, are required. In an encoded NW decoder, each NW is equally likely to contain each encoding. NWs with different encodings can be addressed separately. When NWs are encoded using binary reflected codes [10], M = 2 log 2 C. Using h-hot codes [25], M can be reduced to close to log 2 C. Despite using more MWs binary reflected codes require the same amount of ATC. The main advantage of binary reflected codes is that they allow for wildcarding, which in turn yields a simple testing algorithm [10]. If the N NWs in a given contact group each have a different encoding, these encodings can be discovered in time O(N M), which is optimal. The area required for an encoded NW decoder also depends on C. In order for all NWs in a contact group to be addressable with probability 1 ǫ, the number of NW types, C, must be at least N(N 1)/( 2 ln(1 ǫ)) [10]. Half of the NWs in a contact group are addressable with probability 1 ǫ if C is at least e (N 1 2 lnǫ)/(n+1) (N 1)/2 [10]. It was demonstrated in [10] that requiring half of the NWs be addressable requires significantly less total area than requiring that all NWs be addressable. Additionally, it requires fewer NW encodings be manufactured. As explained in [10], NWs in an encoded NW decoder are assigned encodings with equal probability. Since each encoding can 11

12 be addressed separately, the probability that a NW is individually addressable is (1 1/C) N 1, and the expected number of individually addressable NWs per contact group is N(1 1/C) N 1. This observation allows us to directly apply the derivations of theorem 5.2 and corollary 5.2 that appear in Section 5.1. Doing this gives following result, which does not appear elsewhere. Theorem 3.1 Let N a be the total number of individually addressable NWs in an encoded NW decoder with g contact groups, N NWs per contact group, N = gn NWs in total and M MWs. P(N a > κn ) 1 ǫ if κ (1 1/C) N 1 lnǫ/(2g ) where g = g(n/(n 1)) 2. Also, as mentioned in Section 2.1, it is not always necessary to address NWs individually. If two NWs have the same encoding (see Figure 2), they can still be addressed collectively and used to store the same bit at multiple NW crosspoints. In an encoded NW decoder, the expected number of different encodings per contact group is C(1 (1 1/C) N ). If addressing groups of NWs is acceptable, the above theorem can be modified. Theorem 3.2 Let N a be the total number of addresses in an encoded NW decoder with g contact groups, N NWs per contact group, N = gn NWs in total and M MWs. P(N a > κn ) 1 ǫ if κ (C/N)(1 (1 1/C) N ) ln ǫ/(2g ) where g = g(n/(n 1)) The Masked-Based Decoder Mask-based decoders [23] work with uniform NWs [13,31]. Lithograpically-defined high-k dielectric rectangles are deposited between NWs and MWs. A rectangle amplifies a MW s electric 12

13 a 1 a 1 a 2 a 2 a 3 a 3 a 4 a 4 a) b) Fig. 3. a) A masked-based NW decoder in which regions of high-k dielectric allow each MW to control a different subset of NWs. If arbitrarily small high-k dielectric regions could be manufactured and placed with nanoscale precision, 2log 2 (N) MWs could be used to address each of N NWs. b) Since this is not the case, many randomly shifted copies of the smallest manufacturable region can be used to gain control over individual NWs.) field, allowing it to increase the resistance of the lightly-doped NWs underneath. If rectangles can be as small as the pitch of NWs, they can be used with M = 2 log 2 N MWs to cause all but one NW to have high resistance, as suggested in Figure 3a. Unfortunately, rectangles cannot be made as small as the pitch of NWs. Instead, many randomly shifted copies of the smallest lithographically-defined rectangles can be deposited on a chip. The natural randomness in their locations provides control over NWs with high probability [23] (see Figure 3b). One difficulty, however, is that nanoscale misalignment of a high-k dielectric regions can cause a particular MW to only partially turn off a particular NW. A similar problem will arise if the boundary of a high-k dielectric regions is not sufficiently sharp, although [23] appears to indicate that nanoscale transitions between high-k and low-k dielectric regions are feasible Known Results The number of MWs, M, needed to control N NWs is estimated to be at least six times the number required with an encoded NW decoder [32]. Unless masks can be placed with sub-nw pitch accuracy, the number of MWs required for all N NWs in a contact group to be addressable with probability ǫ is approximately 2(N 1) ln(2(n 1)/ǫ). Even though M is large, each NW can be addressed using a small number of MWs. As a result, the area 13

14 required for ATC remains reasonable. 3.3 The Randomized-Contact Decoder A randomized-contact decoder is any decoder in which NW/MW connections can be modeled as independent random variables. In an RCD, a MW provides strong control over a NW with probability p, very weak or no control with probability q and intermediate or ambiguous control with probability r = 1 (p + q). Since this third case models a manufacturing error, we do not assume that p + q = 1. This is a very practical generalization of the error-free model given in [5]. In Section 5 we bound the number of MWs M required to tolerate a given error rate. Williams and Kuekes first proposed the randomized-contact decoder (RCD) in [33]. There are a number of ways an RCD might be produced. One approach is to randomly deposit impurities (such as gold particles) onto undifferentiated NWs (see Figure 4). Another approach is to randomly deposit small regions of high-k dielectric. An RCD can also be constructed from axially encoded NWs. If many sets of axially encoded NWs are produced with randomly placed lightly doped regions, each NW/MW junction can be treated as an independent random variable. As a result, analysis of RCDs provides bounds that apply to axial (and similarly radial) decoders. There is also another interesting relationship between RCDs, encoded NW decoders, and masked-based decoders. In a maskedbased decoder, there is significant correlation regarding which NWs a given MW controls. In an encoded NW decoder there is correlation between which MWs control a given NW. In an RCD, neither correlation should exist, although in practice a small amount of spacial correlation between NW/MW junctions might be present. Hogg et al [5] have explored the conditions under which most 14

15 Fig. 4. A randomized-contact decoder in which random particle deposition causes each MW to control certain NWs. of the N NWs in an RCD can be controlled by a set of M MWs. They demonstrate through simulation that when M passes a threshold, which is around 4.8 log 2 N, the probability that all NWs are addressable grows rapidly as N increases. This is in agreement with our Corollary 5.3. Their asymptotic analysis doesn t make explicit the dependence of M on N and the probability ǫ of failing to having all NWs be addressable. It also fails to capture the impact of manufacturing errors. We develop tight bounds for both purposes in Section 5, and do so without the independence approximation used in [5], namely that pairs of NWs can be analyzed independently with regard to whether or not each can be controlled separately. We also give a more careful analysis of the value of M required for at least some fixed fraction of NWs to be addressable. 4 Decoder Requirements In Section 5, we bound the number of MWs, M, required by RCDs with N NWs per OC to control many individual NWs. To derive these bounds, we first define the requirements that decoders must meet. The conditions we obtain in this section apply to other types of decoders as well. 4.1 Nanowire Addressing As explained in Section 1, read/write operations are performed in a NW crossbar-based memory by employing an address decoder 15

16 Fig. 5. On the left, the crosspoint being read has a high resistance, but all other crosspoints have a low resistance. On the right, however, the crosspoint being read has a low resistance, but all other crosspoints have a high resistance. To correctly determine the state of the crosspoint, the amount of current flowing from one dimension of the crossbar to the other must be greater on the the right than the left. in each dimension of the memory. If each decoder addresses at least D disjoint sets of NWs, they collectively control D 2 disjoint sets of NW crosspoints each of which can store a bit. Since each of the two decoders is comprised of g contact groups, D = g i=1 D i, where D i is the number of disjoint sets of NWs that can be addressed within the ith contact group. Let R i be the resistance of NW n i. When a decoder addresses a set S of NWs within a single contact group, each NW in S has a low resistance, while the NWs not in S have a high resistance. In a write operation, every NW in S must have a much lower resistance than every NW not in S, that is, max(r i n i S) min(r i n i S). This ensures that the bits associated with NWs in S are written whereas those not in S are not written. A read operation requires that the combined resistance of all NWs in S, R IN, be much less than the combined resistance of NWs not in S, R OUT, that is 1/R OUT 1/R IN. Consider the two extremes illustrated in Figure 5. Since the resistance R of a set of n resistances, R 1,..., R n, placed in parallel satisfies 1/R = 1/R /R n, this is equivalent to n i S 1/R i n i S 1/R i. Definition 4.1 A set, S, of NWs is addressed if and only if a) every NW not in S has a resistance that is at least α times that of every NW in S and b) the combined resistance of all NWs 16

17 not in S is at least α times that of the combined resistance of all NWs in S, where α 1. In general, the choice of an actual value of α is application specific. A larger value, for example, would be required to read data from molecular devices with poor on/off ratios. A larger value would also facilitate reading data more quickly or more reliably. Following the above analysis, if R i R L when n i S and R i R H when n i S, the condition on writing is satisfied when R H αr L and that on reading is satisfied when R H /(N S ) αr L / S. This read condition is hardest to meet when S = 1 in which case R H α(n 1)R L. This is clearly stronger than the write condition R H αr L. 4.2 Resistive and Ideal Models of Control A NW decoder addresses a set of NWs by applying an electric field to a subset of the MWs. These MWs are said to be activated. The set of activated MWs is called an activation pattern. A particular activation pattern, a, is represented as a binary vector where a j = 1 if and only if the jth MW is activated. Each activated MW increases each NW s resistance by some amount (possibly 0). More formally, NWs behave as follows. Definition 4.2 In the resistive model of NW control, each NW n i has initial resistance η i when no MWs are activated. Associated with each NW is a length-m vector of reals, or a realvalued nanowire codeword, r i. The jth entry of r i, r i j, is the amount by which the jth MW increases the resistance of n i when activated. When the decoder is supplied with a, the resistance of NW n i is η i +a r i where a r i is the inner product of activation pattern a and codeword r i. When the jth MW provides strong control over NW n i, rj i is large. rj i is small when the jth MW provides weak control over 17

18 n i. In the ideal case each rj i is either 0 or and a codeword is associated with each NW. Note that multiple NWs may have the same codeword. Definition 4.3 In the ideal model of NW control, each NW, n i is assigned a binary codeword, c i, where c i j = 1 if and only if rj i =. For a particular activation pattern, a, a c i > 0 if and only if a r i =. A set S of NWs is addressed when a c i = 0 for NWs in S and a c j 1 for NWs not in S. In either model of control, a set, S, of NWs is considered addressable if there is some activation pattern such that S is addressed. Similarly, a particular NW n i is individually addressable if there is an activation pattern such that {n i } is addressed. A codeword c i is individually addressable if each NW with that codeword is individually addressable. Notice that in the ideal model of NW control, if a binary codeword is addressable, the NWs with that codeword are addressed by activation pattern a = c i. Furthermore, if c i is not addressable, there is some other codeword c k such that for each j it is not true that c i j = 0 and c k j = 1. This is the mathematical definition of implication; that is, c k j implies ci j. When this condition holds for all values of j, we say that c k implies c i, and write c k c i. The following is immediate. Lemma 4.1 In a simple NW decoder in the ideal model of control, a NW codeword c i is addressable if and only if no other codeword that is present implies c i. The decoder can address D disjoint sets of NWs if and only if D distinct NW codewords are addressable. 4.3 Modeling Errors If each r i j takes value r low = 0 or r high =, each real-valued codeword can be mapped to a binary codeword, which are simple 18

19 to work with. When r low and r high don t hold these extreme values we map r i to c i such that: c i j = 0 if r i j r low c i j = 1 if r high r i j c i j = e if r low r i j r high, meaning that c i j is in error. Our goal is to choose values for r low and r high so that a set S of NWs is addressed by an activation pattern a if the following conditions hold: for n i S, c i j = 0 when a j = 1, for n k S, there exists j such that c k j = 1 and a j = 1. Consider an activation pattern a that meets these two conditions. Let r base = max i η i. Observe that every NW in S has resistance at most R L = r base + (M 1)r low because at most M 1 MWs are activated. Also, note that every NW not in S has resistance at least R H = r high. From Definition 4.1 and the discussion that follows it is clear that S is addressed if R H α(n 1)R L or r high α(n 1)(r base +(M 1)r low ). To simplify the discussion, let r low = cr base for some constant c > 0. Then, S is addressed if r high α(n 1)(cM c + 1)r base where α >> 1. In the above model with errors we say that NW n i is addressable if for each NW n k there is at least one index (MW) j such that c i j = 0 and ck j = 1. The ensures that ci has low resistance while c k has high resistance. When this condition fails, c i may still be addressable but this cannot be guaranteed. We say that a codeword c i fails to be addressable if there exists a codeword c k such that the conditions c i j = 0 and ck j = 1 fail to be satisfied for some j. In this case, and by analogy with the ideal model, we say that codeword c k possibly implies c i, denoted c k? c i. If c k? c i, there is no guarantee that n i can be addressed separately from n k. 19

20 Lemma 4.2 In a simple decoder in the model with errors, a codeword, c i, is addressable if for no other codeword c k does c k? c i. The decoder can address D disjoint sets of NWs if and only if D distinct NW codewords are addressable. If r high is too low or r low is too high to be realized using a particular manufacturing technology, NWs can still be addressed if we set r low = cr base and r high = (α/d)(n 1)(cM c + 1)r base, but instead require that each NW is addressed by an activation pattern that activates at least d high resistance junctions in the other NWs. This ensure that R H = dr high. It is possible for an RCD to be realized with diodes instead of FETs. The decoder model with errors can also be used in this case to capture diodes with imperfect behavior. 5 Analysis of the RCD In an RCD, consider a simple decoder consisting of single contact group with N NWs and M MWs. As mentioned, we assume that NW/MW junctions are controlling (i.e. c i j = 1) with probability p, noncontrolling (i.e. c i j = 0) with probability q, and ambiguous (i.e. c i j is in error) with probability r = 1 p q. We also assume that these events are statistically independent and identically distributed. We now bound N a, the number of individually addressable NWs in each contact group in terms of M, the number of MWs. Recall that for a NW with codeword c i to be individually addressable there must be no other codeword c k such that c k? c i (see Lemma 4.2). We take two approaches to deriving bounds on M. First, in Theorem 5.1 we bound the expected value of N a, E[N a ]. This allows us to apply Hoeffding s Inequality and derive a lower bound on M such that the total number of individually addressable NWs 20

21 across all g contact groups is some at least a fixed fraction of gn, with probability 1 ǫ. Second, in Theorem 5.3, we use the principle of inclusion-exclusion to derive upper and lower bounds on M such that all NWs in all (or almost all) contact groups are independently addressable. The first bound is used to evalute the Take What You Get addressing strategy evaluated in Section 6. The second is used to evaluate the All Wires Addressable and Almost All Wires Addressable strategies. 5.1 Bounds Using Expectation We now bound the mean number of individually addressable NWs. We use this to bound the fraction of NWs in a compound RCD that are addressable with high probability. Theorem 5.1 In an RCD, let N a be the number of independently addressable NWs in a contact group with N NWs and M MWs. N(1 (N 1)(1 pq) M ) E[N a ] N(1 (1 pq) M ) Proof Let x i = 1 if NW n i is independently addressable and 0 otherwise. Since N a = N i=1 x i, E[N a ] = N i=1 E[x i ]. Also, since the {x i } are identically distributed 0-1 random variables, E[N a ] = NE[x 1 ] = NP(x 1 = 1). Let E k,i be the event that c k? c i. P(x 1 = 1) = 1 P(x 1 = 0) = 1 P(E 2,1 E 3,1... E N,1 ). Since P(E 2,1 ) P(E 2,1 E 3,1... E N,1 ) N k=2 P(E k,1 ) and P(E 2,1 ) = P(E 3,1 ) =... = P(E N,1 ), 1 (N 1)P(E 2,1 ) P(x 1 = 1) 1 P(E 2,1 ). c 2? c 1 if for all 1 j M it is not the case that both c 1 j = 0 and c 2 j = 1, thus P(E 2,1) = (1 pq) M and 1 (N 1)(1 pq) M P(x 1 = 1) 1 (1 pq) M. 21

22 Corollary 5.1 Let N = gn be the total number of NWs contained in the g contact groups of a RCD, and let N a be the number of those NWs that are individually addressable. Then,. N (1 (N 1)(1 pq) M ) E[N a] N (1 (1 pq) M ) Proof N a is the sum of the number of individually addressable NWs in each contact group. Since each contact group has N NWs, E[N a ] = ge[n a]. Substituting the bounds from Theorem 5.1 yields the desired result. Let S = n 1 +n n t be the sum of t independent random variables, where each n i ranges from a i to b i. Hoeffding s Inequality [34] states that P (E[S] S d) e 2d2 / c 2 i where c i = b i a i, and d 0. We use this to bound the total number of independently addressable NWs with high probabilty. Theorem 5.2 Let N a be the total number of addressable NWs in an RCD with g contact groups, N NWs per contact group, and N = gn NWs in total. P(N a E[N a ] N k) e 2k2 N N/(N 1) 2 = e 2k2 g for any k 0 where g = g(n/(n 1)) 2. Proof In Hoeffding s Inequality, let t = g, d = N k, S = N a and c i = (N 1). This gives P(E[N a] N a N k) e 2(N k) 2 /g(n 1) 2 = e 2k2 N N/(N 1) 2. We can then rewrite P(E[N a] N a N k) as P(N a E[N a ] N k). From this we obtain a corollary Corollary 5.2 Let N a be the total number of addressable NWs in an RCD with g contact groups, N NWs per contact group, 22

23 N = gn NWs in total and M MWs. P(N a > κn ) 1 ǫ if κ 1 lnǫ/(2g ) (N 1)(1 pq) M where g = g(n/(n 1)) 2. Proof From Corollary 5.1 we have E[N a] N (1 (N 1)(1 pq) M ) and by the above theorem, P(N a N (1 (N 1)(1 pq) M ) N k) e 2k2 g Thus, if k = (1 (N 1)(1 pq) M ) κ, then P(N a κn ) e 2g (1 (N 1)(1 pq) M κ) 2 Thus, when e 2g (1 (N 1)(1 pq) M κ) 2 ǫ the desired conclusion follows. This occurs when lnǫ 2g (1 (N 1)(1 pq) M κ) 2 or ln ǫ/(2g ) (1 κ) (N 1)(1 pq) M. As an example, suppose p = q = 1/2, g = 175, N = 8, N = 1400, ǫ =.01, and κ =.733. When M = 13, κ = ln.01/(2 175 (8/7)2 ) 7 (3/4) 13. Thus at least = 1027 NWs are addressable with probability.99. If errors occur, that is, when p + q < 1, but g is held fixed, M must increase to keep κ constant. For example, if pq =.2 rather than pq =.25 in the error-free case, M must grow by a factor of ln(4/3)/ ln(5/4) = If pq =.1, the factor is ln(4/3)/ ln(10/9) = Even for relatively high error rates, M is not prohibitively large. 5.2 Bounds Using Inclusion/Exclusion In this section we derive bounds on the number of MWs required for all NWs to be individually addressable with high probability. Theorem 5.3 In an RCD, let Γ be the probability that M NWs fail to control all N NWs in a single contact group. Γ satisfies the following bounds 23

24 Q(1 Q/2) Γ Q (1) where Q = N(N 1)µ M 1 and = 2N(N 1)(N 2) ( µ M 3 + µm 5 ) 2µ2M 1 and µ 1 = (1 pq), µ 3 = (1 pq(p+2q)), and µ 5 = (1 pq(2p+q)). Proof See Appendix This theorem implies upper and lower bounds on M in terms of N and Γ. For the cases examined below when p = q and Γ is small, these bounds are tight, meaning the upper and lower bounds they give on M agree. Slightly weaker but simpler bounds are given in the following corollary, in which upper and lower bounds on M differ by ln(2)/ ln(1 pq). Corollary 5.3 In an RCD, the minimum value of M such that all N NWs in a contact group are individually addressable with probability 1 ǫ satisfies the following. ln(n(n 1)/2ǫ) ln(1 pq) M ln(n(n 1)/ǫ) ln(1 pq) Where the lower bound holds when ǫ.05 and the actual minimum value of M is itself at least (1 pq)/(pq min(p, q)). Proof The upper bound follows from (1). For the lower bound, assume Q 0.1, which implies that M ln(10n(n 1))/( lnµ 1 ). This is less than ln(n(n 1)/2ǫ/( ln(1 pq)) when ǫ.05. In drop the last term and replace µ M 3 + µ M 5 by 2 max(µ 3, µ 5 ) M. Since µ 3 = µ 1 pq 2 and µ 5 = µ 1 p 2 q, max(µ 3, µ 5 ) = µ 1 (1 min(pq 2, p 2 q)/µ 1 ). The lower bound on Γ becomes Γ Q(.95 4N(1 pq min(p, q)/µ 1 ) M ). Using the inequality (1 x) n 1 nx, the lower bound is at least Q/2 if M (1.45/4N)(1 pq)/(pq min(p, q)) which is less than (1 pq)/(pq min(p, q)). In this corollary, when ǫ.05, the second condition associated with our lower always holds when p and q are fairly close to 1/2. To see why, consider the extreme case when N = 2. Here the minimum value of M such that neither NW implies the other must satisfy (1 pq) M ǫ, or equivalently M ln(ǫ)/ ln(1 pq). 24

25 It is easy to verify numerically that ln(.05)/ ln(1 pq) (1 pq)/(pq min(p, q)) when pq.21. Corollary 5.4 In an RCD with N NWs divided into g contact groups, all NWs are independently addressable with probability (1 ǫ) if M ln(n ((N /g) 1)/ǫ)/( ln(1 pq)). Proof Let δ be the probability of failure of all NWs in a contact group to be individually addressable. Then, the probability that one or more contact groups fails to have all its NWs be individually addressable is at most gδ. If gδ ǫ, the probability that all N NWs are addressable is at least 1 ǫ. We use the upper bound on M given in Corollary 5.3 when N is replaced by N /g and ǫ by ǫ/g. When N = 1, 024, g = 128 and M 47, all N NWs will be individually addressable with probability 0.99 or better. In fact, evaluating Theorem 5.3 numerically shows this threshold value of M to be exact. These parameters apply to the All Wires Addressable addressing strategy in which every NW address is used. The number of MWs is reduced if we don t require that all NWs in each contact group be individually addressable. We illustrate this with an example. Corollary 5.3 says that a failure rate of at most ǫ =.01 can be achieved with a simple RCD when p = q =.5 and N = 8 if M 30. (As above, this threshold value of M is exact.) The number of individually addressable NWs in each contact group is statistically independent. If all N NWs in a particular contact group are individually addressable with probability 1 ǫ, the probability that f or fewer contact groups fail to have all NWs addressable is φ(ǫ, f, g) = ( f g i=0 i) ǫ i (1 ǫ) g i. Let ǫ =.01, g = 133 and f = 5. Because φ(.01, 5, 133).99, at least 128 of g = 133 contact groups have all NWs addressable with probability

26 In summary, when M = 30, g = 133, and N = = 1064, N a = = 1, 024 NWs are individually addressable with probability These parameters apply to the Almost All Wires Addressable addressing strategy in which almost every NW address is used. As discussed at the end Section 5.1, manufacturing errors only increase the number of required MWs by a small constant factor. 6 Addressing Strategies We now use the bounds on M to estimate the total area required for a crossbar-based memory that uses RCDs. As explained in Section 2.3, this area estimate depends not just on the number of MWs used but also on the size of an ATC. In this section we consider three addressing strategies, that is, ways of using an ATC to map an external binary address E of b = E bits to an internal NW address consisting of a contact group σ and an activation pattern a on M MWs. All Wires Addressable: Here we choose M so that, with probability (1 ǫ), all NWs in every contact group are individually addressable. If we assume that the number of NWs in each contact group is 2 k, we can simply use the first b k bits of E to select σ. This fixed mapping does not depend on the particular NW codewords that are present, although the mapping of E to a does. To execute the second mapping, the ATC stores each NW codeword that is present in a lookup table. This requires N a M bits of storage where N a is the number of addressable NWs in the decoder. All Wires Almost Always Addressable: Here we choose M so that with probability (1 ǫ), all NWs in nearly all contact groups are addressable. Contact groups in which not all NWs are addressable are not used. Since the particular contact groups that are not used will vary from decoder to decoder, the ATC 26

27 cannot use a fixed mapping from E to contact groups σ. Instead, a lookup table is used to obtain an integer to be added to the first b k bits of E so that it corresponds to the proper contact group. Let g be the number of contact groups and g be the number for which all NWs are addressable. Then g g is an upper bound on the values in the table. We also use a lookup table to map E to a. The two tables combined require approximately g log 2 g g + N a M bits. Take What You Get: Here we choose M so that a fixed fraction of the NWs are individually addressable. In this case, some contact groups may have all NWs addressable, but some may not. Since the number of addressable NWs per contact group varies, we can no longer map fixed blocks of binary memory addresses to a particular contact group. Instead, we store a value of σ and a for each addressable NW. This requires N a( log 2 g + M) bits. 6.1 Area Estimate To estimate the total area, A T, required to produce a crossbar memory using each of the three strategies, we use the approach of [10] and write: A T 2χβ + 2λ 2 mesog log 2 g + (λ meso M + λ nano N ) 2 Here λ meso and λ nano denote the pitch of MWs and NWs respectively, that is, the center-to-center distance between wires. Also, χ denotes the area of a mesoscale memory cell, and β denotes the number bits stored in each dimension of the crossbar s ATC. Thus, 2χβ approximates the amount of programmable storage required, 2λ 2 mesog log 2 g approximates the area required to implement a standard demultiplexer used to activate contact groups, and (λ meso M + λ nano N ) 2 approximates the area occupied by the NW crossbar. 27

28 6.2 Comparison of Strategies To compare the three addressing strategies, we estimate their area when used to produce a memory with a given storage capacity. In our comparison, we fix ǫ, the probability of failure, and N/g, the number of NWs per contact group. Given these values, we would ideally like to also fix N a, the number of addressable NWs along each dimension of the crossbar, then estimate A T for all three strategies. Unfortunately, for a given strategy, it is difficult to choose M and N to yield an exact value for N a, but in all three cases we show that about 1, 024 NWs are individually addressable along each dimension. To compare the strategies, we consider the case when p = q = 1/2 and use the numerical results given above. All Wires Addressable: Here M = 47, g = 128, and N = N a = 1024 with probability at least.99. The ATC requires β = N am = 47, 990 bits. This gives A T 95, 982χ + λ 2 meso 1, (λ meso49 + λ nano 1, 600) 2 All Wires Almost Always Addressable: Here M = 30, g = 133, and N = 1, 064 yields N a = 1, 024 and g = 128 with probability at least.99. The ATC requires β = g log g g + N AM = 31, 104 bits. This gives A T 62, 208χ + 1, 877λ 2 meso+(λ meso 30 + λ nano 1, 064) 2 Take What You Get: Here M = 13, g = 175 and N = 1400, yields N a of 1,027 with probability at least.99. The ATC requires β = N a( log g + M) = 21, 567 bits. This gives A T 43, 134χ + 2, 800λ 2 meso + (λ meso13 + λ nano 1, 400) 2 Since the parameter χ, the area of a mesoscale memory unit, will be many times λ 2 meso, and it is expected that λ meso 10λ nano, 28

29 the Take What You Get addressing strategy is clearly best. 7 Codeword Discovery Although required of all NW decoders, codeword discovery has received significantly less attention than NW addressing. In this section, we consider several codeword discovery algorithms that do not require the addition of specialized testing circuitry. We make three assumptions: (a) the ideal decoder model applies so no NW/MW junctions are in error; (b) arbitrary subsets of MWs can be activated; and (c) for any subset of MWs the total amount of current flowing across all NWs in a contact group can be measured, but not with high precision. In Section 7.5 we re-examine (a). Even when many or all NWs are individually addressable, their codewords (or at least some portion of their codewords) must be discovered to properly configure the ATC. It is not feasible to individually probe each NW/MW junction. In the ideal model if all MWs in a contact group are activated and all NWs are controlled by at least one MW, no current will flow. As MWs are turned off one by one, one or more NWs will become conducting. At this point, current is detected. In theory, accurate current measurements and knowledge of NW resistances could allow a testing procedure to estimate how many NWs are conducting, but we avoid this assumption. In [5] it is assumed that one can distinguish how between all NWs being off, one NW being addressed, and two or more NWs being addressed. We avoid this assumption and assume only the ability to distinguish between all NWs being off and at least on NW being on. Since α in Definition 4.1 is much greater than 1, this is a very reasonable assumption. It is already met, for example, by circuitry used to read data from a crossbar-based memory. 29

30 We also examine the number of tests a discovery algorithm must perform. In doing so, we point out an important flaw in the less rigorous analysis given in [5]. 7.1 Exhaustive Search The simplest codeword discovery algorithm is exhaustive search. For each contact group, we determine whether current flows for every possible MW activation pattern. The outputs of all 2 M tests are reviewed offline to determine which codewords are present on individually addressable NWs. Suppose codeword c i is present on the ith NW. Activation pattern a = c i turns on n i and turns off all other NWs. Also, any other activation pattern, a, that turns on a strictly larger subset of MWs turns off all NWs. For this reason we call a maximal. An activation pattern a is maximal if and only if c i = a is individually addressable. Once exhaustive testing is complete, the set of maximal activation patterns can be identified. 7.2 Parallel Exhaustive Search The runtime of this algorithm is exponential in M, but as shown in the previous section M may be relatively small. In our analysis of the Take What You Get addressing strategy, we demonstrated through analysis that a M = 13 suffices. Smaller values of M are also possible if one is willing to tolerate a smaller fraction of addressable NWs. The exponential running time of exhaustive search can be amortized across contact groups if all contact groups can be tested in parallel. If current measurements for each contact group can be taken simultaneously, each of the algorithm s 2 M tests can be performed on all contact groups at once. 30